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9838 Commits

Author SHA1 Message Date
Evan Cheng
ec34226c2b Revert BuildVectorSDNode related patches: 65426, 65427, and 65296. 
llvm-svn: 65482
 2009-02-25 22:49:59 +00:00
Nick Lewycky
8672fb675c Add a totally synthetic situation I came up with while looking at a bug in 
related code.

llvm-svn: 65437
 2009-02-25 06:52:48 +00:00
Scott Michel
29d7559c09 Remove all "cached" data from BuildVectorSDNode, preferring to retrieve 
results via reference parameters.

This patch also appears to fix Evan's reported problem supplied as a
reduced bugpoint test case.

llvm-svn: 65426
 2009-02-25 03:12:50 +00:00
Bill Wendling
9d4eb136da Overhaul my earlier submission due to feedback. It's a large patch, but most of 
them are generic changes.

- Use the "fast" flag that's already being passed into the asm printers instead
  of shoving it into the DwarfWriter.

- Instead of calling "MI->getParent()->getParent()" for every MI, set the
  machine function when calling "runOnMachineFunction" in the asm printers.

llvm-svn: 65379
 2009-02-24 08:30:20 +00:00
Dan Gohman
3766eeea36 Fast-isel can't do TLS yet, so it should fall back to SDISel 
if it sees TLS addresses.

llvm-svn: 65341
 2009-02-23 22:03:08 +00:00
Evan Cheng
dd139e795c Only v1i16 (i.e. _m64) is returned via RAX / RDX. 
llvm-svn: 65313
 2009-02-23 09:03:22 +00:00
Nate Begeman
e0093d2501 Generate better code for v8i16 shuffles on SSE2 
Generate better code for v16i8 shuffles on SSE2 (avoids stack)
Generate pshufb for v8i16 and v16i8 shuffles on SSSE3 where it is fewer uops.
Document the shuffle matching logic and add some FIXMEs for later further
  cleanups.
New tests that test the above.

Examples:

New:
_shuf2:
	pextrw	$7, %xmm0, %eax
	punpcklqdq	%xmm1, %xmm0
	pshuflw	$128, %xmm0, %xmm0
	pinsrw	$2, %eax, %xmm0

Old:
_shuf2:
	pextrw	$2, %xmm0, %eax
	pextrw	$7, %xmm0, %ecx
	pinsrw	$2, %ecx, %xmm0
	pinsrw	$3, %eax, %xmm0
	movd	%xmm1, %eax
	pinsrw	$4, %eax, %xmm0
	ret

=========

New:
_shuf4:
	punpcklqdq	%xmm1, %xmm0
	pshufb	LCPI1_0, %xmm0

Old:
_shuf4:
	pextrw	$3, %xmm0, %eax
	movsd	%xmm1, %xmm0
	pextrw	$3, %xmm1, %ecx
	pinsrw	$4, %ecx, %xmm0
	pinsrw	$5, %eax, %xmm0

========

New:
_shuf1:
	pushl	%ebx
	pushl	%edi
	pushl	%esi
	pextrw	$1, %xmm0, %eax
	rolw	$8, %ax
	movd	%xmm0, %ecx
	rolw	$8, %cx
	pextrw	$5, %xmm0, %edx
	pextrw	$4, %xmm0, %esi
	pextrw	$3, %xmm0, %edi
	pextrw	$2, %xmm0, %ebx
	movaps	%xmm0, %xmm1
	pinsrw	$0, %ecx, %xmm1
	pinsrw	$1, %eax, %xmm1
	rolw	$8, %bx
	pinsrw	$2, %ebx, %xmm1
	rolw	$8, %di
	pinsrw	$3, %edi, %xmm1
	rolw	$8, %si
	pinsrw	$4, %esi, %xmm1
	rolw	$8, %dx
	pinsrw	$5, %edx, %xmm1
	pextrw	$7, %xmm0, %eax
	rolw	$8, %ax
	movaps	%xmm1, %xmm0
	pinsrw	$7, %eax, %xmm0
	popl	%esi
	popl	%edi
	popl	%ebx
	ret

Old:
_shuf1:
	subl	$252, %esp
	movaps	%xmm0, (%esp)
	movaps	%xmm0, 16(%esp)
	movaps	%xmm0, 32(%esp)
	movaps	%xmm0, 48(%esp)
	movaps	%xmm0, 64(%esp)
	movaps	%xmm0, 80(%esp)
	movaps	%xmm0, 96(%esp)
	movaps	%xmm0, 224(%esp)
	movaps	%xmm0, 208(%esp)
	movaps	%xmm0, 192(%esp)
	movaps	%xmm0, 176(%esp)
	movaps	%xmm0, 160(%esp)
	movaps	%xmm0, 144(%esp)
	movaps	%xmm0, 128(%esp)
	movaps	%xmm0, 112(%esp)
	movzbl	14(%esp), %eax
	movd	%eax, %xmm1
	movzbl	22(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm1, %xmm2
	movzbl	42(%esp), %eax
	movd	%eax, %xmm1
	movzbl	50(%esp), %eax
	movd	%eax, %xmm3
	punpcklbw	%xmm1, %xmm3
	punpcklbw	%xmm2, %xmm3
	movzbl	77(%esp), %eax
	movd	%eax, %xmm1
	movzbl	84(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm1, %xmm2
	movzbl	104(%esp), %eax
	movd	%eax, %xmm1
	punpcklbw	%xmm1, %xmm0
	punpcklbw	%xmm2, %xmm0
	movaps	%xmm0, %xmm1
	punpcklbw	%xmm3, %xmm1
	movzbl	127(%esp), %eax
	movd	%eax, %xmm0
	movzbl	135(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm0, %xmm2
	movzbl	155(%esp), %eax
	movd	%eax, %xmm0
	movzbl	163(%esp), %eax
	movd	%eax, %xmm3
	punpcklbw	%xmm0, %xmm3
	punpcklbw	%xmm2, %xmm3
	movzbl	188(%esp), %eax
	movd	%eax, %xmm0
	movzbl	197(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm0, %xmm2
	movzbl	217(%esp), %eax
	movd	%eax, %xmm4
	movzbl	225(%esp), %eax
	movd	%eax, %xmm0
	punpcklbw	%xmm4, %xmm0
	punpcklbw	%xmm2, %xmm0
	punpcklbw	%xmm3, %xmm0
	punpcklbw	%xmm1, %xmm0
	addl	$252, %esp
	ret

llvm-svn: 65311
 2009-02-23 08:49:38 +00:00
Bill Wendling
3151437f5c Propagate debug loc info through prologue/epilogue. 
llvm-svn: 65298
 2009-02-23 00:42:30 +00:00
Scott Michel
3f8637305f Introduce the BuildVectorSDNode class that encapsulates the ISD::BUILD_VECTOR 
instruction. The class also consolidates the code for detecting constant
splats that's shared across PowerPC and the CellSPU backends (and might be
useful for other backends.) Also introduces SelectionDAG::getBUID_VECTOR() for
generating new BUILD_VECTOR nodes.

llvm-svn: 65296
 2009-02-22 23:36:09 +00:00
Evan Cheng
3ea8bd42f3 Add a note. 
llvm-svn: 65275
 2009-02-22 08:13:45 +00:00
Evan Cheng
4385f393f7 Be bug compatible with gcc by returning MMX values in RAX. 
llvm-svn: 65274
 2009-02-22 08:05:12 +00:00
Evan Cheng
9d9688ec15 Do not consider MMX_MOVD64rr a move instructions. The source register is in GR32, the destination is VR64. They are not compatible. 
llvm-svn: 65273
 2009-02-22 08:04:23 +00:00
Anton Korobeynikov
5df82e3e25 Drop bunch of half-working stuff in the ext_weak linkage support. 
Now we're using one gross, but quite robust hack :) (previous ones
did not work, for example, when ext_weak symbol was used deep inside
constant expression in the initializer).

The proper fix of this problem will require some quite huge asmprinter
changes and that's why was postponed. This fixes PR3629 by the way :)

llvm-svn: 65230
 2009-02-21 11:53:32 +00:00
Bill Wendling
bfc216c45a Make sure this doesn't access .end() too. 
llvm-svn: 65213
 2009-02-21 01:11:36 +00:00
Bill Wendling
96430050a5 Make sure we don't dereference the .end() of the container. 
llvm-svn: 65211
 2009-02-21 01:07:26 +00:00
Bill Wendling
66c3ffa2de Propagate more debug loc infos. This also includes some code cleaning. 
llvm-svn: 65207
 2009-02-21 00:43:56 +00:00
Bill Wendling
09289bc433 We need to propagate the debug location information even when dealing with the 
prologue/epilogue.

llvm-svn: 65206
 2009-02-21 00:32:08 +00:00
Evan Cheng
c40c3e28f7 Support return of MMX values in 64-bit mode. 
llvm-svn: 65152
 2009-02-20 20:43:02 +00:00
Torok Edwin
b399b47942 add note about sin 
llvm-svn: 65137
 2009-02-20 18:42:06 +00:00
Bill Wendling
306b992133 Put code that generates debug labels into TableGen so that it can be used by 
everyone.

llvm-svn: 64978
 2009-02-18 23:12:06 +00:00
Dan Gohman
30770ee7b3 Add explicit keywords. 
llvm-svn: 64915
 2009-02-18 16:37:45 +00:00
Nate Begeman
5e78e558ff Add support to the JIT for true non-lazy operation. When a call to a function 
that has not been JIT'd yet, the callee is put on a list of pending functions
to JIT.  The call is directed through a stub, which is updated with the address
of the function after it has been JIT'd.  A new interface for allocating and
updating empty stubs is provided.

Add support for removing the ModuleProvider the JIT was created with, which
would otherwise invalidate the JIT's PassManager, which is initialized with the
ModuleProvider's Module.

Add support under a new ExecutionEngine flag for emitting the infomration 
necessary to update Function and GlobalVariable stubs after JITing them, by
recording the address of the stub and the name of the GlobalValue.  This allows
code to be copied from one address space to another, where libraries may live
at different virtual addresses, and have the stubs updated with their new
correct target addresses.

llvm-svn: 64906
 2009-02-18 08:31:02 +00:00
Dan Gohman
9c258bd2ec Factor out the code to add a MachineOperand to a MachineInstrBuilder. 
llvm-svn: 64891
 2009-02-18 05:45:50 +00:00
Evan Cheng
bd63a1f40d GV with null value initializer shouldn't go to BSS if it's meant for a mergeable strings section. Currently it only checks for Darwin. Someone else please check if it should apply to other targets as well. 
llvm-svn: 64877
 2009-02-18 02:19:52 +00:00
Scott Michel
4c5fa6c982 Remove trailing whitespace to reduce later commit patch noise. 
(Note: Eventually, commits like this will be handled via a pre-commit hook that
 does this automagically, as well as expand tabs to spaces and look for 80-col
 violations.)

llvm-svn: 64827
 2009-02-17 22:15:04 +00:00
Chris Lattner
3b67310686 add a horrible note 
llvm-svn: 64719
 2009-02-17 01:16:14 +00:00
Bill Wendling
266c8bc98f --- Merging (from foreign repository) r64714 into '.': 
U    include/llvm/CodeGen/DebugLoc.h
U    lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp

Enable debug location generation at -Os. This goes with the reapplication of the
r63639 patch.

llvm-svn: 64715
 2009-02-17 01:04:54 +00:00
Dan Gohman
f23a24ce3d Delete trailing whitespace. 
llvm-svn: 64694
 2009-02-16 23:14:14 +00:00
Dan Gohman
856736a187 MachineLICM now handles these cases. 
llvm-svn: 64620
 2009-02-15 23:24:52 +00:00
Dan Gohman
684359ea96 The x86-64 red zone is now being used. 
llvm-svn: 64535
 2009-02-14 03:30:05 +00:00
Evan Cheng
9041a71923 Teach x86 target -soft-float. 
llvm-svn: 64496
 2009-02-13 22:36:38 +00:00
Dale Johannesen
329e01b91b Remove non-DebugLoc versions of BuildMI from IA64, Mips. 
llvm-svn: 64438
 2009-02-13 02:34:39 +00:00
Dale Johannesen
560b03bbcd Remove non-DebugLoc versions of BuildMI from X86. 
There were some that might even matter in X86FastISel.

llvm-svn: 64437
 2009-02-13 02:33:27 +00:00
Dale Johannesen
0336a2cfd0 missed file 
llvm-svn: 64436
 2009-02-13 02:32:04 +00:00
Dale Johannesen
bf9e91b0b9 Remove non-DebugLoc versions of buildMI from Sparc. 
llvm-svn: 64435
 2009-02-13 02:31:35 +00:00
Dale Johannesen
a0069695df Remove non-DebugLoc versions of BuildMI from Alpha and Cell. 
llvm-svn: 64433
 2009-02-13 02:30:42 +00:00
Dale Johannesen
9c596981ed Remove refs to non-DebugLoc version of BuildMI from XCore, PIC16. 
llvm-svn: 64432
 2009-02-13 02:29:03 +00:00
Dale Johannesen
428a8fcc3d Remove refs to non-DebugLoc version of BuildMI from PowerPC. 
llvm-svn: 64431
 2009-02-13 02:27:39 +00:00
Dale Johannesen
986cfc3338 and one more file 
llvm-svn: 64430
 2009-02-13 02:26:21 +00:00
Dale Johannesen
a91dca7b45 Remove refs to non-DebugLoc versions of BuildMI from ARM. 
llvm-svn: 64429
 2009-02-13 02:25:56 +00:00
Bill Wendling
40e4b271af Revert this. It was breaking stuff. 
llvm-svn: 64428
 2009-02-13 02:16:35 +00:00
Bill Wendling
83b6edd760 Turn off the old way of handling debug information in the code generator. Use 
the new way, where all of the information is passed on SDNodes and machine
instructions.

llvm-svn: 64427
 2009-02-13 02:01:04 +00:00
Dale Johannesen
df5d8dfbcb Check in missing file. 
llvm-svn: 64410
 2009-02-12 23:24:44 +00:00
Dale Johannesen
5a21722625 Eliminate a couple of non-DebugLoc BuildMI variants. 
Modify callers.

llvm-svn: 64409
 2009-02-12 23:08:38 +00:00
Dale Johannesen
47321cf01f Arrange to print constants that match "n" and "i" constraints 
in inline asm as signed (what gcc does).  Add partial support
for x86-specific "e" and "Z" constraints, with appropriate
signedness for printing.

llvm-svn: 64400
 2009-02-12 20:58:09 +00:00
Chris Lattner
c1488eea4b fix PR3538 for ARM. 
llvm-svn: 64384
 2009-02-12 17:38:23 +00:00
Chris Lattner
aeec838015 fix PR3538 for PPC 
llvm-svn: 64383
 2009-02-12 17:37:15 +00:00
Chris Lattner
1174b80823 fix the X86 backend to just drop llvm.declare nodes for VLAs instead of 
leaving them in the DAG and then getting selection errors.  This is a 
fix for PR3538.

llvm-svn: 64382
 2009-02-12 17:33:11 +00:00
Bill Wendling
d31cb3d5aa Move debug loc info along when the spiller creates new instructions. 
llvm-svn: 64342
 2009-02-12 00:02:55 +00:00
Bill Wendling
49baa5465c Propagate DebugLoc info for spiller call-backs. 
llvm-svn: 64329
 2009-02-11 21:51:19 +00:00
Dan Gohman
2decb4495d Don't try to set an EFLAGS operand to dead if no instruction was created. 
This fixes a bug introduced by r61215.

llvm-svn: 64316
 2009-02-11 19:50:24 +00:00
Evan Cheng
cdb35e3f0f Handle llvm.x86.sse2.maskmov.dqu in 64-bit. 
llvm-svn: 64240
 2009-02-10 22:06:28 +00:00
Evan Cheng
a1b9cf3143 80 col violations. 
llvm-svn: 64237
 2009-02-10 21:39:44 +00:00
Sanjiv Gupta
abf1d4e9db Function temporaries can not overlap with retval or args.See the comment in source code to know the reason. Anything having .auto. in its name is local to a function in nature irrespective of the linkage specified. print static local variables in module level IDATA section. 
llvm-svn: 64199
 2009-02-10 04:20:26 +00:00
Evan Cheng
3b84024598 Implement FpSET_ST1_*. 
llvm-svn: 64186
 2009-02-09 23:32:07 +00:00
Dan Gohman
548d7c9145 Use doxygen comment syntax. 
llvm-svn: 64150
 2009-02-09 18:12:09 +00:00
Evan Cheng
9dc1507838 Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty 
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.

llvm-svn: 64124
 2009-02-09 07:14:22 +00:00
Chris Lattner
a50a554333 add a note. 
llvm-svn: 64093
 2009-02-08 20:44:19 +00:00
Dale Johannesen
b22cb23f6f Use getDebugLoc forwarder instead of getNode()->getDebugLoc. 
No functional change.

llvm-svn: 64026
 2009-02-07 19:59:05 +00:00
Dan Gohman
4105a38248 Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing 
ScheduleDAG's TLI member to use const.

llvm-svn: 64018
 2009-02-07 16:15:20 +00:00
Dale Johannesen
a068079e5f Needs this file too. 
llvm-svn: 63993
 2009-02-07 00:56:46 +00:00
Dale Johannesen
a259483aae Get rid of the last non-DebugLoc versions of getNode! 
Many targets build placeholder nodes for special operands, e.g.
GlobalBaseReg on X86 and PPC for the PIC base.  There's no
sensible way to associate debug info with these.  I've left
them built with getNode calls with explicit DebugLoc::getUnknownLoc operands. 
I'm not too happy about this but don't see a good improvement;
I considered adding a getPseudoOperand or something, but it
seems to me that'll just make it harder to read.

llvm-svn: 63992
 2009-02-07 00:55:49 +00:00
Dan Gohman
8437b9efa1 Refactor some repeated logic into a separate function. 
llvm-svn: 63989
 2009-02-07 00:43:41 +00:00
Dan Gohman
8aeae15ebd Make a comment a doxygen comment. 
llvm-svn: 63988
 2009-02-07 00:42:54 +00:00
Dale Johannesen
1580ab6b7f Remove more non-DebugLoc getNode variants. Use 
getCALLSEQ_{END,START} to permit passing no DebugLoc
there.  UNDEF doesn't logically have DebugLoc; add
getUNDEF to encapsulate this.

llvm-svn: 63978
 2009-02-06 23:05:02 +00:00
Dale Johannesen
c405486235 Remove more non-DebugLoc versions of getNode. 
llvm-svn: 63969
 2009-02-06 21:50:26 +00:00
Bill Wendling
2c7f47d1d4 Record debug location information in the Dwarf writer. 
A simple test program shows that debugging works. :-)

llvm-svn: 63968
 2009-02-06 21:45:08 +00:00
Dan Gohman
a2f300f26d Use .size and .type on ELF systems; this helps tools that map 
addresses to symbols.

llvm-svn: 63962
 2009-02-06 21:15:52 +00:00
Dale Johannesen
7099fa18a4 Eliminate remaining non-DebugLoc version of getTargetNode. 
llvm-svn: 63951
 2009-02-06 19:16:40 +00:00
Sanjiv Gupta
90fd43f44d Print globl directive for variables with external linkage (global variables). 
llvm-svn: 63943
 2009-02-06 18:24:59 +00:00
Evan Cheng
e00df1d39c Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo. 
llvm-svn: 63938
 2009-02-06 17:43:24 +00:00
Evan Cheng
381b2df5ff Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook. 
llvm-svn: 63936
 2009-02-06 17:17:30 +00:00
Dale Johannesen
cda84103ff get rid of some non-DebugLoc getTargetNode variants. 
llvm-svn: 63909
 2009-02-06 02:08:06 +00:00
Dale Johannesen
e95c76b65e Get rid of one more non-DebugLoc getNode and 
its corresponding getTargetNode.  Lots of
caller changes.

llvm-svn: 63904
 2009-02-06 01:31:28 +00:00
Dale Johannesen
c96091a672 Remove a non-DebugLoc version of getNode. 
llvm-svn: 63889
 2009-02-05 22:07:54 +00:00
Evan Cheng
87def37f67 A few more isAsCheapAsAMove. 
llvm-svn: 63852
 2009-02-05 08:42:55 +00:00
Dale Johannesen
fa28929927 Reapply 63765. Patches for clang and llvm-gcc to follow. 
llvm-svn: 63812
 2009-02-05 01:49:45 +00:00
Dale Johannesen
c901d013fb Get rid of 3 non-DebugLoc getNode variants. 
llvm-svn: 63808
 2009-02-05 01:01:16 +00:00
Dale Johannesen
c2896f9310 Remove non-DebugLoc versions of getMergeValues, ZeroExtendInReg. 
llvm-svn: 63800
 2009-02-05 00:20:09 +00:00
Dale Johannesen
d27bc65e74 Remove non-DebugLoc forms of CopyToReg and CopyFromReg. 
Adjust callers.

llvm-svn: 63789
 2009-02-04 23:02:30 +00:00
Dale Johannesen
f6e1822ccd Reverting 63765. This broke the build of both clang 
and llvm-gcc.

llvm-svn: 63786
 2009-02-04 22:47:25 +00:00
Dale Johannesen
15a801f11d Remove non-DebugLoc versions of getLoad and getStore. 
Adjust the many callers of those versions.

llvm-svn: 63767
 2009-02-04 20:06:27 +00:00
Nate Begeman
66f10b55ed New feature: add support for target intrinsics being defined in the 
target directories themselves.  This also means that VMCore no longer
needs to know about every target's list of intrinsics.  Future work
will include converting the PowerPC target to this interface as an
example implementation.

llvm-svn: 63765
 2009-02-04 19:47:21 +00:00
Chris Lattner
feb6b56242 Bill implemented this. 
llvm-svn: 63752
 2009-02-04 19:09:07 +00:00
Chris Lattner
eae4653469 add a note, this is why we're faster at SciMark-MonteCarlo with 
SSE disabled.

llvm-svn: 63751
 2009-02-04 19:08:01 +00:00
Dan Gohman
1cd89d625c Minor code cleanups; no functionality change. 
llvm-svn: 63740
 2009-02-04 17:28:58 +00:00
Dale Johannesen
19fc835580 Remove non-DebugLoc forms of the exotic forms 
of Lod and Sto; patch uses.

llvm-svn: 63716
 2009-02-04 02:34:38 +00:00
Dale Johannesen
52d1d8d5a0 Remove some more non-DebugLoc versions of construction 
functions, with callers adjusted to fit.

llvm-svn: 63705
 2009-02-04 01:48:28 +00:00
Dale Johannesen
2c4af04551 Remove a few non-DebugLoc versions of node creation 
functions.

llvm-svn: 63703
 2009-02-04 01:17:06 +00:00
Mon P Wang
430525dc4f Fixes a case where we generate an incorrect mask for pshfhw in the presence 
of undefs and incorrectly determining if we have punpckldq.

llvm-svn: 63702
 2009-02-04 01:16:59 +00:00
Dale Johannesen
fa244d6e2d Patch up omissions in DebugLoc propagation. 
llvm-svn: 63693
 2009-02-04 00:33:20 +00:00
Dale Johannesen
f9b2746030 Need this file too. 
llvm-svn: 63674
 2009-02-03 22:26:34 +00:00
Dale Johannesen
b7f2857776 Add some DL propagation to places that didn't 
have it yet.  More coming.

llvm-svn: 63673
 2009-02-03 22:26:09 +00:00
Dale Johannesen
45009f127b DebugLoc propgation 
llvm-svn: 63664
 2009-02-03 21:48:12 +00:00
Dale Johannesen
358418bb3d DebugLoc propagation. done with file. 
llvm-svn: 63656
 2009-02-03 20:21:25 +00:00
Dale Johannesen
6c8c315519 DebugLoc propagation. 2/3 through file. 
llvm-svn: 63650
 2009-02-03 19:33:06 +00:00
Dan Gohman
7d19e6cd6d Tevert part of the x86 subtarget logic changes: when -march=x86-64 
is given, override the subtarget settings and enable 64-bit support.
This restores the earlier behavior, and fixes regressions on
Non-64-bit-capable x86-32 hosts.

This isn't necessarily the best approach, but the most obvious
alternative is to require -mcpu=x86-64 or -mattr=+64bit to be used
with -march=x86-64 when the host doesn't have 64-bit support. This
makes things little more consistent, but it's less convenient, and
it has the practical drawback of requiring lots of test changes, so
I opted for the above approach for now.

llvm-svn: 63642
 2009-02-03 18:53:21 +00:00
Bill Wendling
5b177df8e9 Create DebugLoc information in FastISel. Several temporary methods were 
created. Specifically, those BuildMIs which use
"DebugLoc::getUnknownLoc()". I'll remove them soon.

llvm-svn: 63584
 2009-02-03 00:55:04 +00:00
Dan Gohman
2170150035 Change Feature64Bit to not imply FeatureSSE2. All x86-64 hardware has 
SSE2, however it's possible to disable SSE2, and the subtarget support
code thinks that if 64-bit implies SSE2 and SSE2 is disabled then
64-bit should also be disabled. Instead, just mark all the 64-bit
subtargets as explicitly supporting SSE2.

Also, move the code that makes -march=x86-64 enable 64-bit support by
default to only apply when there is no explicit subtarget. If you
need to specify a subtarget and you want 64-bit code, you'll need to
select a subtarget that supports 64-bit code.

llvm-svn: 63575
 2009-02-03 00:04:43 +00:00
Torok Edwin
2bc41a36ba Only force SSE level if it is not correct. 
Add an assert to check HasX86_64 status.

llvm-svn: 63552
 2009-02-02 21:57:34 +00:00
Torok Edwin
c1017185a5 remove #if 0 code on Bill's request. 
llvm-svn: 63542
 2009-02-02 20:23:02 +00:00
Sanjiv Gupta
c47a19b23e Made the common case of default address space directive as non-virtual for performance reasons. Provide a single virtual interface for directives of all sizes in non-default address spaces. 
llvm-svn: 63521
 2009-02-02 16:53:06 +00:00
Evan Cheng
16c8f917fb ADD / SUB / SMUL / UMUL with overflow second result top bits must be zero. 
llvm-svn: 63509
 2009-02-02 09:15:04 +00:00
Evan Cheng
e8dfbb5884 Add comment. 
llvm-svn: 63506
 2009-02-02 08:19:07 +00:00
Evan Cheng
483bbd1643 Teach LowerBRCOND to recognize (xor (setcc x), 1). The xor inverts the condition. It's normally transformed by the dag combiner, unless the condition is set by a arithmetic op with overflow. 
llvm-svn: 63505
 2009-02-02 08:07:36 +00:00
Torok Edwin
b4c9a6097f Implement -mno-sse: if SSE is disabled on x86-64, don't store XMM on stack for 
var-args, and don't allow FP return values

llvm-svn: 63495
 2009-02-01 18:15:56 +00:00
Duncan Sands
cac6cf74f9 Fix PR3453 and probably a bunch of other potential 
crashes or wrong code with codegen of large integers:
eliminate the legacy getIntegerVTBitMask and
getIntegerVTSignBit methods, which returned their
value as a uint64_t, so couldn't handle huge types.

llvm-svn: 63494
 2009-02-01 18:06:53 +00:00
Dale Johannesen
39738b1ff8 Make LowerCallTo and LowerArguments take a DebugLoc 
argument.  Adjust all callers and overloaded versions.

llvm-svn: 63444
 2009-01-30 23:10:59 +00:00
Bill Wendling
67737da99b Get rid of the non-DebugLoc-ified getNOT() method. 
llvm-svn: 63442
 2009-01-30 23:03:19 +00:00
Sanjiv Gupta
11d082d56e Fixed the comment. No functionality change. 
llvm-svn: 63387
 2009-01-30 09:01:44 +00:00
Sanjiv Gupta
b4cf873468 Use sublw for comparison with literals instead of subwf. 
llvm-svn: 63382
 2009-01-30 07:55:25 +00:00
Mon P Wang
5db99442e4 When PerformBuildVectorCombine, avoid creating a X86ISD::VZEXT_LOAD of 
an illegal type.

llvm-svn: 63380
 2009-01-30 07:07:40 +00:00
Sanjiv Gupta
e442452ade Enable emitting of constant values in non-default address space as well. The APIs emitting constants now take an additional parameter signifying the address space in which to emit. The APIs like getData8BitsDirective() etc are made virtual enabling targets to be able to define appropirate directivers for various sizes and address spaces. 
llvm-svn: 63377
 2009-01-30 04:25:10 +00:00
Dan Gohman
9d120d6d8f Make x86's BT instruction matching more thorough, and add some 
dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.

llvm-svn: 63266
 2009-01-29 01:59:02 +00:00
Mon P Wang
8abb07a527 Fixed lowering of v816 shuffles. 
llvm-svn: 63252
 2009-01-28 23:11:14 +00:00
Duncan Sands
aee16d4916 Rename getAnalysisToUpdate to getAnalysisIfAvailable. 
llvm-svn: 63198
 2009-01-28 13:14:17 +00:00
Evan Cheng
2a965124b7 The memory alignment requirement on some of the mov{h|l}p{d|s} patterns are 16-byte. That is overly strict. These instructions read / write f64 memory locations without alignment requirement. 
llvm-svn: 63195
 2009-01-28 08:35:02 +00:00
Mon P Wang
e1c886f775 Add shuffle splat pattern for x86 sse shifts. 
llvm-svn: 63193
 2009-01-28 08:12:05 +00:00
Evan Cheng
31f8d3639f Suppress a compile time warning. 
llvm-svn: 63161
 2009-01-28 00:53:34 +00:00
Anton Korobeynikov
7e63f1aae6 Treat [1 x i8] zeroinitializer as a C string, placing such stuff into 
mergeable string section. I don't see any bad impact of such decision
(rather then placing it into mergeable const section, as it was before),
but at least Darwin linker won't complain anymore.

The problem in LLVM is that we don't have special type for string constants
(like gcc does). Even more, we have two separate types: ConstatArray for non-null
strings and ConstantAggregateZero for null stuff.... It's a bit weird :)

llvm-svn: 63142
 2009-01-27 22:29:24 +00:00
Dan Gohman
c017343459 Reformat the allocation-order arrays to a more conventional style. 
llvm-svn: 63121
 2009-01-27 19:25:38 +00:00
Dan Gohman
f7e8bf0511 Respect the DisableRedZone flag on PowerPC. 
llvm-svn: 63119
 2009-01-27 19:19:28 +00:00
Dan Gohman
7d80f8688e Simplify findNonImmUse; return the result using the return value 
instead of via a by-reference argument. No functionality change.

llvm-svn: 63118
 2009-01-27 19:04:30 +00:00
Evan Cheng
a05436f739 Implement multiple with overflow by 2 with an add instruction. 
llvm-svn: 63090
 2009-01-27 03:30:42 +00:00
Dan Gohman
2e0343e321 Eliminate unnecessary operands-list traversals. 
llvm-svn: 63088
 2009-01-27 02:37:43 +00:00
Dan Gohman
f3c2ac3497 Enable the red zone on x86-64 by default. 
llvm-svn: 63078
 2009-01-27 00:58:47 +00:00
Dan Gohman
4ad174b236 Fix the Red Zone calculation for functions with frame pointers. 
Don't use the Red Zone when dynamic stack realignment is needed.
This could be implemented, but most x86-64 ABIs don't require
dynamic stack realignment so it isn't urgent.

llvm-svn: 63074
 2009-01-27 00:40:06 +00:00
Scott Michel
e00d746487 CellSPU: 
- Update DWARF debugging support.

llvm-svn: 63059
 2009-01-26 22:33:37 +00:00
Scott Michel
56fa9ba0b6 Make the Dwarf macro information section optional; CellSPU's assembler 
doesn't support it. The default is set to 'true', so this should not
impact any other target backends.

llvm-svn: 63058
 2009-01-26 22:32:51 +00:00
Dan Gohman
3a51d8e847 Implement Red Zone utilization on x86-64. This is currently 
disabled by default; I'll enable it when I hook it up with
the llvm-gcc flag which controls it.

llvm-svn: 63056
 2009-01-26 22:22:31 +00:00
Evan Cheng
ec03e0cd3b Enhance logic in X86DAGToDAGISel::PreprocessForRMW which move load inside callseq_start to allow it to be folded into a call. It was not considering the cases where a token factor is between the load and the callseq_start. 
llvm-svn: 63022
 2009-01-26 18:43:34 +00:00
Dan Gohman
4abaebae0c Take the next steps in making SDUse more consistent with LLVM Use, and 
tidy up SDUse and related code.
 - Replace the operator= member functions with a set method, like
   LLVM Use has, and variants setInitial and setNode, which take
   care up updating use lists, like LLVM Use's does. This simplifies
   code that calls these functions.
 - getSDValue() is renamed to get(), as in LLVM Use, though most
   places can either use the implicit conversion to SDValue or the
   convenience functions instead.
 - Fix some more node vs. value terminology issues.

Also, eliminate the one remaining use of SDOperandPtr, and
SDOperandPtr itself.

llvm-svn: 62995
 2009-01-26 04:35:06 +00:00
Scott Michel
af51520775 Untabify code. 
llvm-svn: 62991
 2009-01-26 03:37:41 +00:00
Scott Michel
da9360e77e CellSPU: 
- Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll
- Fix select_bits.ll test
- Capitulate to the DAGCombiner and move i64 constant loads to instruction
  selection (SPUISelDAGtoDAG.cpp).

  <rant>DAGCombiner will insert all kinds of 64-bit optimizations after
  operation legalization occurs and now we have to do most of the work that
  instruction selection should be doing twice (once to determine if v2i64
  build_vector can be handled by SelectCode(), which then runs all of the
  predicates a second time to select the necessary instructions.) But,
  CellSPU is a good citizen.</rant>

llvm-svn: 62990
 2009-01-26 03:31:40 +00:00
Nate Begeman
48639fe6dc Fix a typo 
llvm-svn: 62989
 2009-01-26 03:15:54 +00:00
Nate Begeman
d2f708eca5 De-identifying per sabre review 
llvm-svn: 62988
 2009-01-26 03:15:31 +00:00
Nate Begeman
92efc4f0ce Map address space 256 to gs; similar mappings could be supported for the 
other x86 segments.  address space 0 is stack/default, 1-255 are reserved for
client use.

llvm-svn: 62980
 2009-01-26 01:24:32 +00:00
Nate Begeman
81d70f3f54 Support pattern matching various x86 sse shifts. 
llvm-svn: 62979
 2009-01-26 00:52:55 +00:00
Chris Lattner
e7bf6037e2 silence a warning when assertions are disabled. 
llvm-svn: 62976
 2009-01-25 23:08:00 +00:00
Torok Edwin
6f715ebe85 should have removed the + when manually applying a patch! 
llvm-svn: 62973
 2009-01-25 20:29:34 +00:00
Torok Edwin
3f54410405 revert this patch for now, because Codegen does still want to generate SSE code, 
for example in the case of va-args. XFAIL associated tests.

llvm-svn: 62972
 2009-01-25 20:21:24 +00:00
Torok Edwin
49b1d3e3cc If user explicitly asks not to use SSE, don't force it. This fixes LLVM part of PR3402. 
llvm-svn: 62967
 2009-01-25 17:58:56 +00:00
Evan Cheng
71ca3e2bdb Private linkage support for PPC / Darwin. 
llvm-svn: 62955
 2009-01-25 06:32:01 +00:00
Nate Begeman
48f3fe9199 Fix an indent and a typo. 
llvm-svn: 62940
 2009-01-24 22:12:48 +00:00
Torok Edwin
6dd79be128 add note about possible GEP improvement with fields of size 0. 
llvm-svn: 62925
 2009-01-24 19:30:25 +00:00
Chris Lattner
97b6f6a674 hopefully address PR3379 by making the P modifier work in x86 inline asm. 
llvm-svn: 62887
 2009-01-23 22:33:40 +00:00
Bob Wilson
186046e657 Add SelectionDAG::getNOT method to construct bitwise NOT operations, 
corresponding to the "not" and "vnot" PatFrags.  Use the new method
in some places where it seems appropriate.

llvm-svn: 62768
 2009-01-22 17:39:32 +00:00
Evan Cheng
c971801ae1 Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead. 
llvm-svn: 62762
 2009-01-22 09:10:11 +00:00
Chris Lattner
fcf56e7fbe add a note 
llvm-svn: 62760
 2009-01-22 07:16:03 +00:00
Dan Gohman
29b575c6cd Recognize inline asm for bswap on x86-64 GLIBC. This allows it 
to be supported in the JIT.

llvm-svn: 62730
 2009-01-21 23:40:54 +00:00
Evan Cheng
43d680b0d8 Also favors NOT64r. 
llvm-svn: 62710
 2009-01-21 19:45:31 +00:00
Chris Lattner
2b6b947b4f fix warning in release-asserts mode and spelling of assert. 
llvm-svn: 62699
 2009-01-21 18:38:18 +00:00
Dan Gohman
704f0d5879 Fix a recent regression. ClrOpcode is not set for i8; for i8, if 
we want to clear %ah to zero before a division, just use a
zero-extending mov to %al. This fixes PR3366.

llvm-svn: 62691
 2009-01-21 14:50:16 +00:00
Sanjiv Gupta
ebef67f13c Fixed build warnings. Restoring changes done in 62600, they were lost in 62655. 
llvm-svn: 62681
 2009-01-21 09:02:46 +00:00
Duncan Sands
392dc77fc6 Cleanup whitespace and comments, and tweak some 
prototypes, in operand type legalization.  No
functionality change.

llvm-svn: 62680
 2009-01-21 09:00:29 +00:00
Sanjiv Gupta
37fdb5ca11 Implement LowerOperationWrapper for legalizer. 
Also a few signed comparison fixes.

llvm-svn: 62665
 2009-01-21 05:44:05 +00:00
Scott Michel
c80e71ac35 CellSPU: 
- Ensure that (operation) legalization emits proper FDIV libcall when needed.
- Fix various bugs encountered during llvm-spu-gcc build, along with various
  cleanups.
- Start supporting double precision comparisons for remaining libgcc2 build.
  Discovered interesting DAGCombiner feature, which is currently solved via
  custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner
  insists on inserting one anyway.)
- Update README.

llvm-svn: 62664
 2009-01-21 04:58:48 +00:00
Evan Cheng
0ed6a9d7e0 Favors generating "not" over "xor -1". For example. 
unsigned test(unsigned a) {
  return ~a;
}
llvm used to generate:
movl    $4294967295, %eax
xorl    4(%esp), %eax

Now it generates:
movl      4(%esp), %eax
notl      %eax

It's 3 bytes shorter.

llvm-svn: 62661
 2009-01-21 02:09:05 +00:00
Evan Cheng
b3c82db63d Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well. 
llvm-svn: 62600
 2009-01-20 19:12:24 +00:00
Dan Gohman
7663e08915 Add a README entry noticed while investigating PR3216. 
llvm-svn: 62558
 2009-01-20 01:07:33 +00:00
Evan Cheng
06cfade044 DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it. 
llvm-svn: 62519
 2009-01-19 19:06:11 +00:00
Evan Cheng
3c00875658 Fix 80 col violations. 
llvm-svn: 62518
 2009-01-19 18:57:29 +00:00
Evan Cheng
2f50b49f22 Handle ISD::DECLARE with PIC relocation model. 
llvm-svn: 62516
 2009-01-19 18:31:51 +00:00
Evan Cheng
a14fd26a8b Minor tweak to LowerUINT_TO_FP_i32. Bias (after scalar_to_vector) has two uses so we should make it the second source operand of ISD::OR so 2-address pass won't have to be smart about commuting. 
%reg1024<def> = MOVSDrm %reg0, 1, %reg0, <cp#0>, Mem:LD(8,8) [ConstantPool + 0]
%reg1025<def> = MOVSD2PDrr %reg1024
%reg1026<def> = MOVDI2PDIrm <fi#-1>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack-1 + 0]
%reg1027<def> = ORPSrr %reg1025<kill>, %reg1026<kill>
%reg1028<def> = MOVPD2SDrr %reg1027<kill>
%reg1029<def> = SUBSDrr %reg1028<kill>, %reg1024<kill>
%reg1030<def> = CVTSD2SSrr %reg1029<kill>
MOVSSmr <fi#0>, 1, %reg0, 0, %reg1030<kill>, Mem:ST(4,4) [FixedStack0 + 0]
%reg1031<def> = LD_Fp32m80 <fi#0>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack0 + 0]
RET %reg1031<kill>, %ST0<imp-use,kill>

The reason 2-addr pass isn't smart enough to commute the ORPSrr is because it can't look pass the MOVSD2PDrr instruction.

llvm-svn: 62505
 2009-01-19 08:19:57 +00:00
Evan Cheng
53e83a2eb9 Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't 
optimize it to a SINT_TO_FP when the sign bit is known zero. X86 isel should perform the optimization itself.

llvm-svn: 62504
 2009-01-19 08:08:22 +00:00
Bill Wendling
ce30a8cab9 Extend thi 
llvm-svn: 62415
 2009-01-17 07:40:19 +00:00
Evan Cheng
182d9c4c9f Fix MatchAddress bug that's preventing negative displacement from being folded in 64-bit mode. 
llvm-svn: 62413
 2009-01-17 07:09:27 +00:00
Bill Wendling
ddd55bdfec Temporarily revert my last change. It is causing a bootstrap failure. 
llvm-svn: 62405
 2009-01-17 04:23:51 +00:00
Bill Wendling
d18c38c0f2 Implement a special algorithm for converting uint_to_fp for i32 values on 
X86. This code:

void f() {
  uint32_t x;
  float y = (float)x;
}

used to be:

     movl     %eax, -8(%ebp)
     movl     [2^52 double], -4(%ebp)
     movsd    -8(%ebp), %xmm0
     subsd    [2^52 double], %xmm0
     cvtsd2ss %xmm0, %xmm0

Is now:

   movsd        [2^52 double], %xmm0
   movsd        %xmm0, %xmm1
   movd         %ecx, %xmm2
   orps         %xmm2, %xmm1
   subsd        %xmm0, %xmm1
   cvtsd2ss     %xmm1, %xmm0

This is faster on X86. Note that there's an extra load of %xmm0 into %xmm1. That
will be fixed in a later coalescer fix.

llvm-svn: 62404
 2009-01-17 03:56:04 +00:00
Oscar Fuentes
ee36d9ce83 CMake: Add lib/Target/IA64/IA64Subtarget.cpp 
llvm-svn: 62394
 2009-01-17 01:50:32 +00:00
Evan Cheng
d7cc550900 Fix PPC ISD::Declare isel and eliminate the need for PPCTargetLowering::LowerGlobalAddress to check if isVerifiedDebugInfoDesc() is true. Given the recent changes, it would falsely return true for a lot of GlobalAddressSDNode's. 
llvm-svn: 62373
 2009-01-16 22:57:32 +00:00
Dan Gohman
cb207179b1 Give IA64 a TargetSubtarget subclass, so that it can 
implement getSubtargetImpl.

llvm-svn: 62369
 2009-01-16 22:49:36 +00:00
Bill Wendling
c9e856fbfd Add support for non-zero __builtin_return_address values on X86. 
llvm-svn: 62338
 2009-01-16 19:25:27 +00:00
Evan Cheng
c58653bd6e ARMCompilationCallback should not save / restore vfp registers if vfp is not available. 
llvm-svn: 62299
 2009-01-16 02:16:37 +00:00
Dan Gohman
c5b1dbdb4e Initial hazard recognizer support in post-pass scheduling. This includes 
a new toy hazard recognizier heuristic which attempts to direct the
scheduler to avoid clumping large groups of loads or stores too densely.

llvm-svn: 62291
 2009-01-16 01:33:36 +00:00
Dan Gohman
3e0dcbbd15 Generalize the HazardRecognizer interface so that it can be used 
to support MachineInstr-based scheduling in addition to
SDNode-based scheduling.

llvm-svn: 62284
 2009-01-15 22:18:12 +00:00
Rafael Espindola
46b374f55b Fix Alpha test and support for private linkage. 
llvm-svn: 62282
 2009-01-15 21:51:46 +00:00
Mon P Wang
4cfe965df2 Expand insert/extract of a <4 x i32> with a variable index. 
llvm-svn: 62281
 2009-01-15 21:10:20 +00:00
Rafael Espindola
0aba6c9435 Add the private linkage. 
llvm-svn: 62279
 2009-01-15 20:18:42 +00:00
Dan Gohman
6fcee67989 Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph 
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.

To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.

llvm-svn: 62275
 2009-01-15 19:20:50 +00:00
Dan Gohman
0b06dcbf4b Add load-folding table entries for BT*ri8 instructions. 
llvm-svn: 62267
 2009-01-15 17:57:09 +00:00
Dan Gohman
37d7b5be33 Make getWidenVectorType const. 
llvm-svn: 62265
 2009-01-15 17:34:08 +00:00
Dan Gohman
ab89b888e8 Const-qualify getPreIndexedAddressParts and friends. 
llvm-svn: 62259
 2009-01-15 16:29:45 +00:00
Richard Osborne
ce265d8cf9 Don't fold address calculations which use negative offsets into 
the ADDRspii addressing mode.

llvm-svn: 62258
 2009-01-15 11:32:30 +00:00
Richard Osborne
71ffa94e3f Update the operands used when building LDAWSP instructions to match the .td 
changes in the last commit.

llvm-svn: 62257
 2009-01-15 11:18:53 +00:00
Scott Michel
b4699590f0 - Convert remaining i64 custom lowering into custom instruction emission 
sequences in SPUDAGToDAGISel.cpp and SPU64InstrInfo.td, killing custom
  DAG node types as needed.
- i64 mul is now a legal instruction, but emits an instruction sequence
  that stretches tblgen and the imagination, as well as violating laws of
  several small countries and most southern US states (just kidding, but
  looking at a function with 80+ parameters is really weird and just plain
  wrong.)
- Update tests as needed.

llvm-svn: 62254
 2009-01-15 04:41:47 +00:00
Richard Osborne
12b88f2fae Add pseudo instructions to the XCore for (load|store|load address) of a 
frame index. eliminateFrameIndex will replace these instructions with
(LDWSP|STWSP|LDAWSP) or (LDW|STW|LDAWF) if a frame pointer is in use.

This fixes PR 3324. Previously we used LDWSP, STWSP, LDAWSP before frame
pointer elimination. However since they were marked as implicitly using
SP they could not be rematerialised.

llvm-svn: 62238
 2009-01-14 18:26:46 +00:00
Nuno Lopes
b5a8a4b4dd fix memleaks 
llvm-svn: 62198
 2009-01-13 23:35:49 +00:00
Dan Gohman
6f5847ccfc BT appears to be available on all >= i386 chips. 
llvm-svn: 62196
 2009-01-13 23:27:15 +00:00
Dan Gohman
9c2ee40c1c Don't use a BT instruction if the AND has multiple uses. 
llvm-svn: 62195
 2009-01-13 23:25:30 +00:00
Dan Gohman
8c835f6285 Disable the register+memory forms of the bt instructions for now. Thanks 
to Eli for pointing out that these forms don't ignore the high bits of
their index operands, and as such are not immediately suitable for use
by isel.

llvm-svn: 62194
 2009-01-13 23:23:30 +00:00
Dan Gohman
15e69a394a Add bt instructions that take immediate operands. 
llvm-svn: 62180
 2009-01-13 20:33:23 +00:00
Dan Gohman
e84cfeac5f Fix a few more JIT encoding issues in the BT instructions. 
llvm-svn: 62179
 2009-01-13 20:32:45 +00:00
Sanjiv Gupta
b712a41535 Checking in conditionals, function call, arrays and libcalls implementation. 
llvm-svn: 62174
 2009-01-13 19:18:47 +00:00
Chris Lattner
50de4f0704 make -march=cpp handle the nocapture attribute, make it assert if it 
sees attributes it doesn't know.

llvm-svn: 62155
 2009-01-13 07:22:22 +00:00
Devang Patel
eed0505ed8 Use DebugInfo interface to lower dbg_* intrinsics. 
llvm-svn: 62127
 2009-01-13 00:35:13 +00:00
Duncan Sands
bcdbfb63dc Rename getABITypeSize to getTypePaddedSize, as 
suggested by Chris.

llvm-svn: 62099
 2009-01-12 20:38:59 +00:00
Evan Cheng
ce292ad389 80 col violation. 
llvm-svn: 62024
 2009-01-10 03:33:22 +00:00
Misha Brukman
71c7e40966 Removed trailing whitespace from Makefiles. 
llvm-svn: 61991
 2009-01-09 16:44:42 +00:00
Dan Gohman
a487b137a8 Add load-folding table entries for MOVDQA. 
llvm-svn: 61972
 2009-01-09 02:40:34 +00:00
Dan Gohman
0e86745357 Whitespace and other minor adjustments to make SSE instructions have 
the same formatting as their corresponding SSE2 instructions, for
consistency.

llvm-svn: 61971
 2009-01-09 02:27:34 +00:00
Devang Patel
747d4b38ad Convert DwarfWriter into a pass. 
Now Users request DwarfWriter through getAnalysisUsage() instead of creating an instance of DwarfWriter object directly.

llvm-svn: 61955
 2009-01-08 23:40:34 +00:00
Chris Lattner
fe3e114d7a add some more crazy strlen and memcpy stuff I noticed in spec. 
llvm-svn: 61918
 2009-01-08 07:34:55 +00:00
Chris Lattner
304f33297f add some notes about strlen craziness in eon. 
llvm-svn: 61917
 2009-01-08 06:52:57 +00:00
Misha Brukman
6338af14f6 Fix off-by-one error in traversing an array; this fixes a test. 
The error was reported by gcc-4.3.0 during compilation.

llvm-svn: 61896
 2009-01-07 23:07:29 +00:00
Dan Gohman
ca4475dd7b Add patterns to match conditional moves with loads folded 
into their left operand, rather than their right. Do this
by commuting the operands and inverting the condition.

llvm-svn: 61842
 2009-01-07 01:00:24 +00:00
Dan Gohman
ab00fbad9d Add load-folding table entries for cmovno too. 
llvm-svn: 61841
 2009-01-07 00:44:53 +00:00
Dan Gohman
e78fdaec67 Define instructions for cmovo and cmovno. 
llvm-svn: 61836
 2009-01-07 00:35:10 +00:00
Dan Gohman
2682e8745c X86_COND_C and X86_COND_NC are alternate mnemonics for 
X86_COND_B and X86_COND_AE, respectively.

llvm-svn: 61835
 2009-01-07 00:15:08 +00:00
Dan Gohman
e033f7c41e Revert r42653 and forward-port the code that lets INC64_32r be 
converted to LEA64_32r in x86's convertToThreeAddress. This
replaces code like this:
   movl  %esi, %edi
   inc   %edi
with this:
   lea   1(%rsi), %edi
which appears to be beneficial.

llvm-svn: 61830
 2009-01-06 23:34:46 +00:00
Scott Michel
54f7f6d67f CellSPU: 
- Add preliminary support for v2i32; load/store generates the right code but
  there's a lot work to be done to make this vector type operational.

llvm-svn: 61829
 2009-01-06 23:10:38 +00:00
Scott Michel
147ab93be5 CellSPU: Update the README 
llvm-svn: 61785
 2009-01-06 03:51:14 +00:00
Scott Michel
c30557841b CellSPU: 
- Fix bugs 3194, 3195: i128 load/stores produce correct code (although, we
  need to ensure that i128 is 16-byte aligned in real life), and 128 zero-
  extends are supported.
- New td file: SPU128InstrInfo.td: this is where all new i128 support should
  be put in the future.
- Continue to hammer on i64 operations and test cases; ensure that the only
  remaining problem will be i64 mul.

llvm-svn: 61784
 2009-01-06 03:36:14 +00:00
Bill Wendling
891f9abdbb Revert r61415 and r61484. Duncan was correct that these weren't needed. 
llvm-svn: 61765
 2009-01-05 22:53:45 +00:00
Dan Gohman
8271066844 Tidy up #includes, deleting a bunch of unnecessary #includes. 
llvm-svn: 61715
 2009-01-05 17:59:02 +00:00
Devang Patel
689e130117 squash warnings. 
llvm-svn: 61707
 2009-01-05 17:31:22 +00:00
Evan Cheng
d2ffa1f122 Atom and Core i7 do not have same model number after all. 
llvm-svn: 61686
 2009-01-05 08:45:01 +00:00
Scott Michel
733d5f71a0 CellSPU: 
- Teach SPU64InstrInfo.td about the remaining signed comparisons, update tests
  accordingly.

llvm-svn: 61672
 2009-01-05 04:05:53 +00:00
Scott Michel
0d9d939406 CellSPU: 
- Fix (brcond (setq ...)) bug, where BRNZ should have been used vice BRZ.
- Kill unused/unnecessary nodes in SPUNodes.td
- Beef out the i64operations.c test harness to use a lot of unaligned
  loads, test loops and LLVM loop/basic block optimizations; run the
  test harness successfully on real Cell hardware.

llvm-svn: 61664
 2009-01-05 01:34:35 +00:00
Evan Cheng
540a7a5e9b Add Intel processors core i7 and atom. 
llvm-svn: 61603
 2009-01-03 04:24:44 +00:00
Evan Cheng
c477e19c19 Fix PR3210: Detect more Intel processors. Patch by Torok Edwin. 
llvm-svn: 61602
 2009-01-03 04:04:46 +00:00
Scott Michel
0309418000 CellSPU: 
- Remove custom lowering for BRCOND
- Add remaining functionality for branches in SPUInstrInfo, such as branch
  condition reversal and load/store folding. Updated BrCond test to reflect
  branch reversal.

llvm-svn: 61597
 2009-01-03 00:27:53 +00:00
Scott Michel
57a5503c5a - Make copyRegToReg use the "LR" assembler synonym for "OR". Makes finding 
register copies a little easier to pick out from the output.
- Fix bug 3192.

llvm-svn: 61591
 2009-01-02 20:52:08 +00:00
Evan Cheng
c52f942d67 Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register. 
llvm-svn: 61557
 2009-01-02 05:35:45 +00:00
Evan Cheng
f460ec040c Fix x86 CPU id detection to identify Penryn (and future processors). 
llvm-svn: 61556
 2009-01-02 05:29:20 +00:00
Evan Cheng
57115c1887 Use movaps / movd to extract vector element 0 even with sse4.1. It's still cheaper than pextrw especially if the value is in memory. 
llvm-svn: 61555
 2009-01-02 05:29:08 +00:00
Duncan Sands
190d6bc636 Fix PR3274: when promoting the condition of a BRCOND node, 
promote from i1 all the way up to the canonical SetCC type.
In order to discover an appropriate type to use, pass
MVT::Other to getSetCCResultType.  In order to be able to
do this, change getSetCCResultType to take a type as an
argument, not a value (this is also more logical).

llvm-svn: 61542
 2009-01-01 15:52:00 +00:00
Chris Lattner
1cfa9f47db add a note 
llvm-svn: 61513
 2008-12-31 00:54:13 +00:00
Scott Michel
cdcae67887 - Start moving target-dependent nodes that could be represented by an 
instruction sequence and cannot ordinarily be simplified by DAGcombine
  into the various target description files or SPUDAGToDAGISel.cpp.

  This makes some 64-bit operations legal.

- Eliminate target-dependent ISD enums.

- Update tests.

llvm-svn: 61508
 2008-12-30 23:28:25 +00:00
Bill Wendling
067c48f7a6 Linux wants the FDE initial location and address range to be forced to 32-bit. 
Darwin doesn't. Make this optional for platforms.

llvm-svn: 61484
 2008-12-29 22:12:11 +00:00
Misha Brukman
00d6a6ed4e Fixed spelling, removed trailing whitespace. 
llvm-svn: 61477
 2008-12-29 20:08:23 +00:00
Scott Michel
e555efe94d - Various '#if 0' cleanups. 
- Move v4i32, i32 mul into SPUInstrInfo.td, with a few more instruction
  cleanups there as well.
- Make SMUL_LOHI, UMUL_LOHI competely illegal for Cell SPU, to better
  assist Chris to see the problem in bug 3101.

llvm-svn: 61464
 2008-12-29 03:23:36 +00:00
Scott Michel
bf224860c8 - Remove Tilmann's custom truncate lowering: it completely hosed over 
DAGcombine's ability to find reasons to remove truncates when they were not
  needed. Consequently, the CellSPU backend would produce correct, but _really
  slow and horrible_, code.

  Replaced with instruction sequences that do the equivalent truncation in
  SPUInstrInfo.td.

- Re-examine how unaligned loads and stores work. Generated unaligned
  load code has been tested on the CellSPU hardware; see the i32operations.c
  and i64operations.c in CodeGen/CellSPU/useful-harnesses.  (While they may be
  toy test code, it does prove that some real world code does compile
  correctly.)

- Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc
  fault because i64 ult is not yet implemented.)

- Added i64 eq and neq for setcc and select/setcc; started new instruction
  information file for them in SPU64InstrInfo.td. Additional i64 operations
  should be added to this file and not to SPUInstrInfo.td.

llvm-svn: 61447
 2008-12-27 04:51:36 +00:00
Chris Lattner
fde038935b Add a simple pattern for matching 'bt'. 
llvm-svn: 61426
 2008-12-25 05:34:37 +00:00
Chris Lattner
062ed6e3dd Fix some JIT encodings. 
llvm-svn: 61425
 2008-12-25 01:32:49 +00:00
Chris Lattner
f34b843728 BT memory operands load from their address operand. 
llvm-svn: 61424
 2008-12-25 01:27:10 +00:00
Chris Lattner
e9229dc899 translateX86CC can never fail. Simplify it based on this. 
llvm-svn: 61423
 2008-12-24 23:53:05 +00:00
Bill Wendling
044248aad1 Darwin likes for the EH frame to be non-local. 
llvm-svn: 61420
 2008-12-24 08:05:17 +00:00
Bill Wendling
6add893a14 GCC doesn't emit DW_EH_PE_sdata4 for the FDE encoding on Darwin. I'm not sure 
about other platforms.

llvm-svn: 61415
 2008-12-24 05:25:49 +00:00
Dan Gohman
7ff343fe6c Fix a compiler-abort on a testcase where the stack-pointer is added to 
a symbolic constant. This is unlikely to be intentional, but it
shouldn't crash the compiler.

llvm-svn: 61408
 2008-12-24 00:27:51 +00:00
Chris Lattner
ca08c532f7 indentation 
llvm-svn: 61407
 2008-12-24 00:11:37 +00:00
Chris Lattner
c20dd60a21 simplify some control flow and reduce indentation, no functionality change. 
llvm-svn: 61404
 2008-12-23 23:42:27 +00:00
Dan Gohman
1ba93ac6be Add instruction patterns and encodings for the x86 bt instructions. 
llvm-svn: 61400
 2008-12-23 22:45:23 +00:00
Devang Patel
d4aebdfa3f Silence unused variable warnings. 
llvm-svn: 61392
 2008-12-23 21:56:28 +00:00
Dan Gohman
a0f1fc06c4 Clean up the atomic opcodes in SelectionDAG. 
This removes all the _8, _16, _32, and _64 opcodes and replaces each
group with an unsuffixed opcode. The MemoryVT field of the AtomicSDNode
is now used to carry the size information. In tablegen, the size-specific
opcodes are replaced by size-independent opcodes that utilize the
ability to compose them with predicates.

This shrinks the per-opcode tables and makes the code that handles
atomics much more concise.

llvm-svn: 61389
 2008-12-23 21:37:04 +00:00
Chris Lattner
bb08a35f9e add some notes for simplifylibcalls optimizations 
llvm-svn: 61385
 2008-12-23 20:52:52 +00:00
Mon P Wang
7b9b2770bb Fixed code generation for v8i16 and v16i8 splats on X86. 
Fixed lowering of v8i16 shuffles for v8i16 when we fall back to extract/insert.

llvm-svn: 61365
 2008-12-23 04:03:27 +00:00
Dan Gohman
faf474af38 Make the fuse-failed debug output human-readable. 
llvm-svn: 61356
 2008-12-23 00:19:20 +00:00
Dan Gohman
c9f244842c Fix fast-isel to not emit invalid assembly when presented with a 
constant shift count that doesn't fit in the shift instruction's
immediate field. This fixes PR3242.

llvm-svn: 61281
 2008-12-20 17:19:40 +00:00
Dan Gohman
22b7b328a4 Move the patterns which have i8 immediates before the patterns 
that have i32 immediates so that they get selected first. This
currently only matters in the JIT, as assemblers will
automatically use the smallest encoding.

llvm-svn: 61250
 2008-12-19 18:25:21 +00:00