.. |
AsmParser
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[AMDGPU][MC] Corrected dst/data size for MIMG opcodes with d16 modifier
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2018-02-05 14:18:53 +00:00 |
Disassembler
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[AMDGPU][MC] Corrected dst/data size for MIMG opcodes with d16 modifier
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2018-02-05 14:18:53 +00:00 |
InstPrinter
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[AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32
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2018-01-15 18:49:15 +00:00 |
MCTargetDesc
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[AMDGPU][MC][GFX9] Enable inline constants for SDWA operands
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2018-01-17 14:00:48 +00:00 |
TargetInfo
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Add backend name to Target to enable runtime info to be fed back into TableGen
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2017-11-15 23:55:44 +00:00 |
Utils
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[AMDGPU][MC] Corrected dst/data size for MIMG opcodes with d16 modifier
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2018-02-05 14:18:53 +00:00 |
AMDGPU.h
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[AMDGPU] Clean up symbols in the global namespace.
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2017-10-31 23:21:30 +00:00 |
AMDGPU.td
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[AMDGPU][MC] Added validation of d16 and r128 modifiers of MIMG opcodes
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2018-02-05 12:45:43 +00:00 |
AMDGPUAliasAnalysis.cpp
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[AMDGPU] calling conventions for AMDPAL OS type
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2017-09-29 09:51:22 +00:00 |
AMDGPUAliasAnalysis.h
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[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
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2017-08-08 23:53:55 +00:00 |
AMDGPUAlwaysInlinePass.cpp
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AMDGPU: Add option to stress calls
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2017-09-21 07:00:48 +00:00 |
AMDGPUAnnotateKernelFeatures.cpp
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[Analysis] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes. Also affected in files (NFC).
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2017-08-31 21:56:16 +00:00 |
AMDGPUAnnotateUniformValues.cpp
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AMDGPUArgumentUsageInfo.cpp
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[CodeGen] Rename functions PrintReg* to printReg*
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2017-11-28 12:42:37 +00:00 |
AMDGPUArgumentUsageInfo.h
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[AMDGPU] Fixed MSVC build break
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2017-08-04 10:53:07 +00:00 |
AMDGPUAsmPrinter.cpp
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[AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support
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2018-01-10 14:22:19 +00:00 |
AMDGPUAsmPrinter.h
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[AMDGPU] add labels to +DumpCode output
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2017-12-08 14:09:34 +00:00 |
AMDGPUCallingConv.td
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AMDGPU: Initial implementation of calls
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2017-08-01 19:54:18 +00:00 |
AMDGPUCallLowering.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
AMDGPUCallLowering.h
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AMDGPUCodeGenPrepare.cpp
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[IR] redefine 'UnsafeAlgebra' / 'reassoc' fast-math-flags and add 'trans' fast-math-flag
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2017-11-06 16:27:15 +00:00 |
AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h
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Move TargetFrameLowering.h to CodeGen where it's implemented
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2017-11-03 22:32:11 +00:00 |
AMDGPUGenRegisterBankInfo.def
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[GlobalISel] Make GlobalISel a non-optional library.
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2017-08-03 21:52:25 +00:00 |
AMDGPUInline.cpp
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[AMDGPU] Port of HSAIL inliner
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2017-09-20 04:25:58 +00:00 |
AMDGPUInstrInfo.cpp
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AMDGPU/SI: Adjust the encoding family for D16 buffer instructions when the target has UnpackedD16VMem feature.
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2018-02-01 18:41:33 +00:00 |
AMDGPUInstrInfo.h
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AMDGPU: Partially fix disassembly of MIMG instructions
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2017-12-13 21:07:51 +00:00 |
AMDGPUInstrInfo.td
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AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
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2018-01-31 20:18:04 +00:00 |
AMDGPUInstructions.td
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AMDGPU: Move ADDRIndirect complex pattern into R600Instructions.td
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2018-01-29 23:29:26 +00:00 |
AMDGPUInstructionSelector.cpp
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[GISel] Make constrainSelectedInstRegOperands() available to the legalizer. NFC
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2018-01-17 19:31:33 +00:00 |
AMDGPUInstructionSelector.h
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[globalisel][tablegen] Generate rule coverage and use it to identify untested rules
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2017-11-16 00:46:35 +00:00 |
AMDGPUIntrinsicInfo.cpp
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AMDGPUIntrinsicInfo.h
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AMDGPUIntrinsics.td
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AMDGPUISelDAGToDAG.cpp
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[AMDGPU] add LDS f32 intrinsics
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2018-01-17 14:05:05 +00:00 |
AMDGPUISelLowering.cpp
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AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
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2018-01-31 20:18:04 +00:00 |
AMDGPUISelLowering.h
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AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
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2018-01-31 20:18:04 +00:00 |
AMDGPULegalizerInfo.cpp
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[globalisel] Make LegalizerInfo::LegalizeAction available outside of LegalizerInfo. NFC
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2018-01-29 17:37:29 +00:00 |
AMDGPULegalizerInfo.h
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AMDGPULibCalls.cpp
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Make helpers static. NFC.
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2017-11-24 14:55:41 +00:00 |
AMDGPULibFunc.cpp
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[AMDGPU] Remove hardcoded address space value from AMDGPULibFunc
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2017-11-04 17:37:43 +00:00 |
AMDGPULibFunc.h
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[AMDGPU] Remove hardcoded address space value from AMDGPULibFunc
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2017-11-04 17:37:43 +00:00 |
AMDGPULowerIntrinsics.cpp
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AMDGPUMachineCFGStructurizer.cpp
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[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
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2017-12-07 10:40:31 +00:00 |
AMDGPUMachineFunction.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
AMDGPUMachineFunction.h
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AMDGPUMachineModuleInfo.cpp
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AMDGPUMachineModuleInfo.h
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AMDGPU: Handle more than one memory operand in SIMemoryLegalizer
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2017-09-07 16:14:21 +00:00 |
AMDGPUMacroFusion.cpp
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AMDGPUMacroFusion.h
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AMDGPUMCInstLower.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
AMDGPUMCInstLower.h
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AMDGPUOpenCLEnqueuedBlockLowering.cpp
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AMDGPU: Fix set but not used warnings related to AMDGPUAS
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2017-11-01 19:12:38 +00:00 |
AMDGPUOpenCLImageTypeLoweringPass.cpp
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[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
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2017-08-08 23:53:55 +00:00 |
AMDGPUPromoteAlloca.cpp
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AMDGPU: Fix assert on alloca of array of struct
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2017-09-14 18:02:29 +00:00 |
AMDGPUPTNote.h
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AMDGPU/NFC: Move AMDGPU specific note types to ELF.h
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2017-10-12 18:59:54 +00:00 |
AMDGPURegAsmNames.inc.cpp
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AMDGPURegisterBankInfo.cpp
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Fix a bunch more layering of CodeGen headers that are in Target
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2017-11-17 01:07:10 +00:00 |
AMDGPURegisterBankInfo.h
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AMDGPURegisterBanks.td
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AMDGPURegisterInfo.cpp
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[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
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2018-01-24 18:09:53 +00:00 |
AMDGPURegisterInfo.h
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[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
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2018-01-24 18:09:53 +00:00 |
AMDGPURegisterInfo.td
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AMDGPU: Move INDIRECT_BASE_ADDR definition out of common files
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2017-07-29 03:44:07 +00:00 |
AMDGPURewriteOutArguments.cpp
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[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
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2017-08-08 23:53:55 +00:00 |
AMDGPUSubtarget.cpp
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[AMDGPU][MC] Added validation of d16 and r128 modifiers of MIMG opcodes
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2018-02-05 12:45:43 +00:00 |
AMDGPUSubtarget.h
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[AMDGPU][MC] Added validation of d16 and r128 modifiers of MIMG opcodes
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2018-02-05 12:45:43 +00:00 |
AMDGPUTargetMachine.cpp
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[AMDGPU] Switch to the new addr space mapping by default
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2018-02-02 16:07:16 +00:00 |
AMDGPUTargetMachine.h
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(Re-landing) Expose a TargetMachine::getTargetTransformInfo function
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2017-12-22 18:21:59 +00:00 |
AMDGPUTargetObjectFile.cpp
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AMDGPU: Fix set but not used warnings related to AMDGPUAS
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2017-11-01 19:12:38 +00:00 |
AMDGPUTargetObjectFile.h
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AMDGPUTargetTransformInfo.cpp
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[AMDGPU] fix LDS f32 intrinsics
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2018-01-26 11:09:38 +00:00 |
AMDGPUTargetTransformInfo.h
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LSR: Check more intrinsic pointer operands
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2017-12-11 21:38:43 +00:00 |
AMDGPUUnifyDivergentExitNodes.cpp
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[Transforms] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
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2017-10-17 21:27:42 +00:00 |
AMDGPUUnifyMetadata.cpp
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[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
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2017-08-10 00:46:15 +00:00 |
AMDILCFGStructurizer.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
AMDKernelCodeT.h
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[AMDGPU] Revert r310429 changes in AMDKernelCodeT.h which broke some build bots.
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2017-08-09 00:06:29 +00:00 |
BUFInstructions.td
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AMDGPU/SI: Adjust the encoding family for D16 buffer instructions when the target has UnpackedD16VMem feature.
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2018-02-01 18:41:33 +00:00 |
CaymanInstructions.td
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[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
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2017-12-07 10:40:31 +00:00 |
CMakeLists.txt
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AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)
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2017-11-20 14:35:53 +00:00 |
DSInstructions.td
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[AMDGPU] add LDS f32 intrinsics
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2018-01-17 14:05:05 +00:00 |
EvergreenInstructions.td
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[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
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2017-12-07 10:40:31 +00:00 |
FLATInstructions.td
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[AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodes
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2017-11-27 17:14:35 +00:00 |
GCNHazardRecognizer.cpp
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[AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards().
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2017-12-07 20:34:25 +00:00 |
GCNHazardRecognizer.h
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[AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards().
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2017-12-07 20:34:25 +00:00 |
GCNILPSched.cpp
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AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)
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2017-11-20 14:35:53 +00:00 |
GCNIterativeScheduler.cpp
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[NFC] fix trivial typos in comments and documents
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2018-01-29 05:17:03 +00:00 |
GCNIterativeScheduler.h
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AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)
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2017-11-20 14:35:53 +00:00 |
GCNMinRegStrategy.cpp
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[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
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2017-08-08 23:53:55 +00:00 |
GCNProcessors.td
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AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
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2017-12-08 20:52:28 +00:00 |
GCNRegPressure.cpp
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Rename LiveIntervalAnalysis.h to LiveIntervals.h
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2017-12-13 02:51:04 +00:00 |
GCNRegPressure.h
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Rename LiveIntervalAnalysis.h to LiveIntervals.h
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2017-12-13 02:51:04 +00:00 |
GCNSchedStrategy.cpp
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[NFC] fix trivial typos in comments
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2018-01-22 05:54:46 +00:00 |
GCNSchedStrategy.h
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LLVMBuild.txt
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MIMGInstructions.td
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[AMDGPU][MC] Added support of 64-bit image atomics
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2018-01-26 15:43:29 +00:00 |
R600ClauseMergePass.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
R600ControlFlowFinalizer.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
R600Defines.h
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
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[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
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2017-08-10 00:46:15 +00:00 |
R600FrameLowering.cpp
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R600FrameLowering.h
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AMDGPU: Initial implementation of calls
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2017-08-01 19:54:18 +00:00 |
R600InstrFormats.td
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AMDGPU: Remove global isGCN predicates
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2017-10-03 00:06:41 +00:00 |
R600InstrInfo.cpp
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[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
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2018-01-24 18:09:53 +00:00 |
R600InstrInfo.h
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[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
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2018-01-24 18:09:53 +00:00 |
R600Instructions.td
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AMDGPU: Move ADDRIndirect complex pattern into R600Instructions.td
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2018-01-29 23:29:26 +00:00 |
R600Intrinsics.td
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R600ISelLowering.cpp
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AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction
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2017-12-04 23:07:28 +00:00 |
R600ISelLowering.h
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R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp
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R600MachineScheduler.h
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R600OptimizeVectorRegisters.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
R600Packetizer.cpp
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AMDGPU/R600: Initialize more passes
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2017-08-02 22:19:45 +00:00 |
R600Processors.td
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AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction
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2017-12-04 23:07:28 +00:00 |
R600RegisterInfo.cpp
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[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
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2018-01-24 18:09:53 +00:00 |
R600RegisterInfo.h
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R600RegisterInfo.td
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AMDGPU: Move INDIRECT_BASE_ADDR definition out of common files
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2017-07-29 03:44:07 +00:00 |
R600Schedule.td
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R700Instructions.td
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SIAnnotateControlFlow.cpp
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AMDGPU: Error in SIAnnotateControlFlow instead of assert
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2018-01-17 16:30:01 +00:00 |
SIDebuggerInsertNops.cpp
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SIDefines.h
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AMDGPU/SI: Add d16 support for image intrinsics.
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2018-01-18 22:08:53 +00:00 |
SIFixSGPRCopies.cpp
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[CodeGen] Unify MBB reference format in both MIR and debug output
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2017-12-04 17:18:51 +00:00 |
SIFixVGPRCopies.cpp
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SIFixWWMLiveness.cpp
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Rename LiveIntervalAnalysis.h to LiveIntervals.h
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2017-12-13 02:51:04 +00:00 |
SIFoldOperands.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
SIFrameLowering.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
SIFrameLowering.h
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[AMDGPU] AMDPAL scratch buffer support
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2017-09-29 09:49:35 +00:00 |
SIInsertSkips.cpp
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[AMDGPU] isRenamable fixes to support copy forwarding
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2018-01-30 17:37:39 +00:00 |
SIInsertWaitcnts.cpp
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[AMDGPU] Revert "[AMDGPU] Add options for waitcnt pass debugging; add instr count in debug output."
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2018-01-30 17:17:06 +00:00 |
SIInsertWaits.cpp
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[NFC] fix trivial typos in comments and documents
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2018-01-29 05:17:03 +00:00 |
SIInstrFormats.td
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[AMDGPU] isRenamable fixes to support copy forwarding
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2018-01-30 17:37:39 +00:00 |
SIInstrInfo.cpp
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AMDGPU: Fold inline offset for loads properly in moveToVALU on GFX9
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2018-01-31 20:18:11 +00:00 |
SIInstrInfo.h
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[NFC] fix trivial typos in comments
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2018-01-24 05:04:35 +00:00 |
SIInstrInfo.td
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[AMDGPU][MC] Corrected parsing of image opcode modifiers r128 and d16
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2018-01-29 14:20:42 +00:00 |
SIInstructions.td
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AMDGPU: Fix missing SCC def from s_xor_b64_term
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2018-01-31 22:54:27 +00:00 |
SIIntrinsics.td
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SIISelLowering.cpp
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AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
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2018-01-31 20:18:04 +00:00 |
SIISelLowering.h
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AMDGPU/SI: Add d16 support for buffer intrinsics.
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2018-01-12 21:12:19 +00:00 |
SILoadStoreOptimizer.cpp
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[AMDGPU] SI Load Store Optimizer: When merging with offset, use V_ADD_{I|U}32_e64
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2018-01-22 21:46:43 +00:00 |
SILowerControlFlow.cpp
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Rename LiveIntervalAnalysis.h to LiveIntervals.h
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2017-12-13 02:51:04 +00:00 |
SILowerI1Copies.cpp
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Rename LiveIntervalAnalysis.h to LiveIntervals.h
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2017-12-13 02:51:04 +00:00 |
SIMachineFunctionInfo.cpp
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AMDGPU: Use unique PSVs for buffer resources
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2017-12-29 17:18:21 +00:00 |
SIMachineFunctionInfo.h
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[AMDGPU] stop image_store being moved illegally
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2018-01-12 22:57:24 +00:00 |
SIMachineScheduler.cpp
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Rename LiveIntervalAnalysis.h to LiveIntervals.h
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2017-12-13 02:51:04 +00:00 |
SIMachineScheduler.h
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SIMemoryLegalizer.cpp
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AMDGPU/MemoryModel: Fix monotonic atomic loads
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2018-02-06 04:06:04 +00:00 |
SIOptimizeExecMasking.cpp
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[AMDGPU][X86][Mips] Make sure renamable bit not set for reserved regs
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2018-01-29 18:47:48 +00:00 |
SIOptimizeExecMaskingPreRA.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
SIPeepholeSDWA.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
SIRegisterInfo.cpp
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[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
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2018-01-24 18:09:53 +00:00 |
SIRegisterInfo.h
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[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
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2018-01-24 18:09:53 +00:00 |
SIRegisterInfo.td
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[AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support
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2018-01-10 14:22:19 +00:00 |
SISchedule.td
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SIShrinkInstructions.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
SIWholeQuadMode.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
SMInstructions.td
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AMDGPU: Set IntrReadMem on memtime intrinsics
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2017-12-08 20:01:02 +00:00 |
SOPInstructions.td
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AMDGPU: Add llvm.amdgcn.wqm.vote intrinsic
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2017-10-24 10:26:59 +00:00 |
VIInstrFormats.td
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VIInstructions.td
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VOP1Instructions.td
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[AMDGPU] Copy impdefs from pseudo to real instructions
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2018-01-15 17:55:35 +00:00 |
VOP2Instructions.td
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AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
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2018-01-31 20:18:04 +00:00 |
VOP3Instructions.td
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[AMDGPU] isRenamable fixes to support copy forwarding
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2018-01-30 17:37:39 +00:00 |
VOP3PInstructions.td
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AMDGPU: Add max-mix-insts subtarget feature
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2017-10-25 07:00:51 +00:00 |
VOPCInstructions.td
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[AMDGPU] Copy impdefs from pseudo to real instructions
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2018-01-15 17:55:35 +00:00 |
VOPInstructions.td
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[AMDGPU] isRenamable fixes to support copy forwarding
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2018-01-30 17:37:39 +00:00 |