..
AsmParser
[AMDGPU] Add VReg_192/VReg_224 support for MIMG instructions
2021-07-22 10:42:15 +09:00
Disassembler
[AMDGPU] Add VReg_192/VReg_224 support for MIMG instructions
2021-07-22 10:42:15 +09:00
MCTargetDesc
[AMDGPU] Handle s_branch to another section.
2021-07-13 12:17:47 +01:00
TargetInfo
Utils
[AMDGPU] Allow frontends to disable null export for pixel shaders
2021-07-22 10:20:46 +09:00
AMDGPU.h
[AMDGPU] Improve register computation for indirect calls
2021-07-20 13:48:50 +02:00
AMDGPU.td
[AMDGPU] Add maximum NSA size limit ISA feature
2021-07-23 16:16:06 +09:00
AMDGPUAliasAnalysis.cpp
[NFC][AA] Prepare to convert AliasResult to class with PartialAlias offset.
2021-04-09 12:54:22 +03:00
AMDGPUAliasAnalysis.h
AMDGPUAlwaysInlinePass.cpp
[AMDGPU] Disable forceful inline of non-kernel functions which use LDS.
2021-04-15 09:12:56 +05:30
AMDGPUAnnotateKernelFeatures.cpp
[AMDGPU] Do not annotate features for graphics
2021-05-03 10:33:11 +02:00
AMDGPUAnnotateUniformValues.cpp
[OpaquePtr] Clean up some uses of Type::getPointerElementType()
2021-05-31 09:54:57 -07:00
AMDGPUArgumentUsageInfo.cpp
[GlobalISel] NFC: Change LLT::vector to take ElementCount.
2021-06-24 11:26:12 +01:00
AMDGPUArgumentUsageInfo.h
AMDGPUAsmPrinter.cpp
[AMDGPU] Improve register computation for indirect calls
2021-07-20 13:48:50 +02:00
AMDGPUAsmPrinter.h
[AMDGPU] Improve register computation for indirect calls
2021-07-20 13:48:50 +02:00
AMDGPUAtomicOptimizer.cpp
[AMDGPU] Use reductions instead of scans in the atomic optimizer
2021-03-26 15:38:14 +00:00
AMDGPUCallingConv.td
AMDGPU: Promote signext/zeroext i16 shader returns
2021-07-13 11:04:51 -04:00
AMDGPUCallLowering.cpp
AMDGPU/GlobalISel: Preserve more memory types
2021-07-16 08:57:26 -04:00
AMDGPUCallLowering.h
AMDGPU/GlobalISel: Redo kernel argument load handling
2021-07-16 08:56:54 -04:00
AMDGPUCodeGenPrepare.cpp
[AMDGPU] [CodeGen] Fold negate llvm.amdgcn.class into test mask
2021-06-18 13:04:12 -06:00
AMDGPUCombine.td
AMDGPU/GlobalISel: Remove redundant G_FCANONICALIZE
2021-04-27 12:26:37 +02:00
AMDGPUExportClustering.cpp
AMDGPUExportClustering.h
AMDGPUFeatures.td
AMDGPUFixFunctionBitcasts.cpp
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUGenRegisterBankInfo.def
AMDGPUGISel.td
AMDGPU/GlobalISel: Add integer med3 combines
2021-04-27 11:52:23 +02:00
AMDGPUGlobalISelUtils.cpp
AMDGPUGlobalISelUtils.h
[ADT] Move DenseMapInfo for ArrayRef/StringRef into respective headers (NFC)
2021-06-03 18:34:36 +02:00
AMDGPUHSAMetadataStreamer.cpp
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
AMDGPUHSAMetadataStreamer.h
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
AMDGPUInstCombineIntrinsic.cpp
AMDGPUInstrInfo.cpp
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td
AMDGPU: Move zeroed FP high bits optimization to patterns
2021-06-22 12:47:56 -04:00
AMDGPUInstructions.td
[AMDGPU] Simplify tablegen files. NFC.
2021-07-07 09:19:23 +01:00
AMDGPUInstructionSelector.cpp
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
AMDGPUInstructionSelector.h
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
AMDGPUISelDAGToDAG.cpp
AMDGPU: Fix high 16-bit optimization on gfx9
2021-06-22 13:16:45 -04:00
AMDGPUISelLowering.cpp
[AMDGPU] Stop mulhi from doing 24 bit mul for uniform values
2021-07-05 10:33:23 +01:00
AMDGPUISelLowering.h
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
AMDGPULateCodeGenPrepare.cpp
[OpaquePtr] Remove uses of CreateConstGEP1_64() without element type
2021-07-17 16:43:20 +02:00
AMDGPULegalizerInfo.cpp
[AMDGPU] Add maximum NSA size limit ISA feature
2021-07-23 16:16:06 +09:00
AMDGPULegalizerInfo.h
[AMDGPU] Remove dead declaration (NFC).
2021-05-25 16:04:04 +05:30
AMDGPULibCalls.cpp
[llvm] Rename StringRef _lower() method calls to _insensitive()
2021-06-25 00:22:01 +03:00
AMDGPULibFunc.cpp
[amdgpu] Add -enable-ocl-mangling-mismatch-workaround.
2021-06-08 15:42:27 -04:00
AMDGPULibFunc.h
AMDGPULowerIntrinsics.cpp
AMDGPULowerKernelArguments.cpp
[CodeGen] Add missing includes (NFC)
2021-06-06 15:48:27 +02:00
AMDGPULowerKernelAttributes.cpp
[AMDGPU] Fix pass name of AMDGPULowerKernelAttributes. NFC.
2021-07-06 15:03:31 -07:00
AMDGPULowerModuleLDSPass.cpp
[AMDGPU] Disable LDS lowering for GFX shaders
2021-07-20 02:55:25 -07:00
AMDGPUMachineCFGStructurizer.cpp
AMDGPUMachineFunction.cpp
[AMDGPU] Fix module LDS selection
2021-05-20 15:59:01 -07:00
AMDGPUMachineFunction.h
AMDGPUMachineModuleInfo.cpp
AMDGPUMachineModuleInfo.h
AMDGPUMacroFusion.cpp
AMDGPUMacroFusion.h
AMDGPUMCInstLower.cpp
AMDGPUMIRFormatter.cpp
AMDGPUMIRFormatter.h
AMDGPUOpenCLEnqueuedBlockLowering.cpp
AMDGPUPerfHintAnalysis.cpp
[AMDGPU] Tune perfhint analysis to account access width
2021-07-21 12:46:10 -07:00
AMDGPUPerfHintAnalysis.h
[AMDGPU] Tune perfhint analysis to account access width
2021-07-21 12:46:10 -07:00
AMDGPUPostLegalizerCombiner.cpp
AMDGPU/GlobalISel: Remove redundant G_FCANONICALIZE
2021-04-27 12:26:37 +02:00
AMDGPUPreLegalizerCombiner.cpp
[GISel] Support llvm.memcpy.inline
2021-06-30 12:39:05 -07:00
AMDGPUPrintfRuntimeBinding.cpp
[AMDGPU] Simplify GEP construction (NFC)
2021-07-08 21:21:43 +02:00
AMDGPUPromoteAlloca.cpp
[OpaquePtr] Create API to make a copy of a PointerType with some address space
2021-06-01 16:52:32 -07:00
AMDGPUPropagateAttributes.cpp
Revert "[AMDGPU] [IndirectCalls] Don't propagate attributes to address taken functions and their callees"
2021-06-24 02:33:50 +01:00
AMDGPUPTNote.h
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
AMDGPURegBankCombiner.cpp
AMDGPU/GlobalISel: Add integer med3 combines
2021-04-27 11:52:23 +02:00
AMDGPURegisterBankInfo.cpp
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
AMDGPURegisterBankInfo.h
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
AMDGPURegisterBanks.td
[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
2021-06-24 12:41:22 +09:00
AMDGPUReplaceLDSUseWithPointer.cpp
[OpaquePtr] Remove uses of CreateGEP() without element type
2021-07-17 22:56:27 +02:00
AMDGPUResourceUsageAnalysis.cpp
[AMDGPU] Improve register computation for indirect calls
2021-07-20 13:48:50 +02:00
AMDGPUResourceUsageAnalysis.h
[AMDGPU] Fix running ResourceUsageAnalysis
2021-07-23 09:25:15 +02:00
AMDGPURewriteOutArguments.cpp
AMDGPUSearchableTables.td
AMDGPUSubtarget.cpp
[AMDGPU] Add maximum NSA size limit ISA feature
2021-07-23 16:16:06 +09:00
AMDGPUSubtarget.h
[AMDGPU] Stop mulhi from doing 24 bit mul for uniform values
2021-07-05 10:33:23 +01:00
AMDGPUTargetMachine.cpp
[AMDGPU] Move perfhint analysis
2021-07-21 13:06:49 -07:00
AMDGPUTargetMachine.h
[NewPM] Hide pass manager debug logging behind -debug-pass-manager-verbose
2021-05-07 21:51:47 -07:00
AMDGPUTargetObjectFile.cpp
AMDGPUTargetObjectFile.h
AMDGPUTargetTransformInfo.cpp
[TTI] Remove IsPairwiseForm from getArithmeticReductionCost
2021-07-09 11:51:16 +01:00
AMDGPUTargetTransformInfo.h
[TTI] Remove IsPairwiseForm from getArithmeticReductionCost
2021-07-09 11:51:16 +01:00
AMDGPUUnifyDivergentExitNodes.cpp
[AMDGPU] Don't handle export done when unify exit nodes
2021-07-14 14:54:37 +08:00
AMDGPUUnifyMetadata.cpp
AMDILCFGStructurizer.cpp
[NewPM] Cleanup IR printing instrumentation
2021-04-15 09:50:55 -07:00
AMDKernelCodeT.h
BUFInstructions.td
[AMDGPU] Simplify tablegen files. NFC.
2021-07-07 09:19:23 +01:00
CaymanInstructions.td
CMakeLists.txt
[AMDGPU] Improve register computation for indirect calls
2021-07-20 13:48:50 +02:00
DSInstructions.td
[AMDGPU] Set IsAtomicRet and IsAtomicNoRet on Real instructions
2021-06-16 12:23:29 +01:00
EvergreenInstructions.td
[AMDGPU] Inline FSHRPattern into its only use. NFC.
2021-03-26 09:32:02 +00:00
EXPInstructions.td
FLATInstructions.td
[AMDGPU] Set IsAtomicRet and IsAtomicNoRet on Real instructions
2021-06-16 12:23:29 +01:00
GCNDPPCombine.cpp
[AMDGPU] GCNDPPCombine: don't shrink V_ADD_CO_U32 if carry out is used
2021-04-20 09:17:52 +01:00
GCNHazardRecognizer.cpp
[AMDGPU] Limit runs of fixLdsBranchVmemWARHazard
2021-06-14 22:30:23 +02:00
GCNHazardRecognizer.h
[AMDGPU] Limit runs of fixLdsBranchVmemWARHazard
2021-06-14 22:30:23 +02:00
GCNILPSched.cpp
GCNIterativeScheduler.cpp
GCNIterativeScheduler.h
GCNMinRegStrategy.cpp
GCNNSAReassign.cpp
GCNPreRAOptimizations.cpp
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
GCNProcessors.td
[AMDGPU] Add gfx1035 target
2021-06-24 14:32:41 -04:00
GCNRegPressure.cpp
GCNRegPressure.h
GCNSchedStrategy.cpp
GCNSchedStrategy.h
GCNSubtarget.h
[AMDGPU] Add maximum NSA size limit ISA feature
2021-07-23 16:16:06 +09:00
InstCombineTables.td
MIMGInstructions.td
[AMDGPU] Add VReg_192/VReg_224 support for MIMG instructions
2021-07-22 10:42:15 +09:00
R600.td
R600AsmPrinter.cpp
R600AsmPrinter.h
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600FrameLowering.cpp
R600FrameLowering.h
R600InstrFormats.td
R600InstrInfo.cpp
R600InstrInfo.h
R600Instructions.td
R600ISelLowering.cpp
[DAG] Add a generic expansion for SHIFT_PARTS opcodes using funnel shifts
2021-05-07 13:12:30 +01:00
R600ISelLowering.h
Revert "[llvm][sve] Lowering for VLS truncating stores" because it
2021-07-19 11:03:33 -07:00
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OpenCLImageTypeLoweringPass.cpp
R600OptimizeVectorRegisters.cpp
R600Packetizer.cpp
R600Processors.td
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R600Subtarget.h
R700Instructions.td
SIAnnotateControlFlow.cpp
[AMDGPU] Set LoopInfo as preserved by SIAnnotateControlFlow
2021-07-08 09:34:43 -07:00
SIDefines.h
[AMDGPU] IsFlatScratch/Global -> FlatScratch/Global
2021-04-09 11:20:31 +02:00
SIFixSGPRCopies.cpp
SIFixVGPRCopies.cpp
SIFoldOperands.cpp
AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions
2021-06-22 13:42:49 -04:00
SIFormMemoryClauses.cpp
[AMDGPU][NFC] Fix typos in SIFormMemoryClauses description
2021-05-06 07:47:39 -07:00
SIFrameLowering.cpp
[AMDGPU] Init scratch only if necessary
2021-07-14 10:45:22 +02:00
SIFrameLowering.h
SIInsertHardClauses.cpp
[AMDGPU] Do not clause NSA instructions
2021-05-14 12:54:56 +09:00
SIInsertWaitcnts.cpp
[AMDGPU] Remove assert
2021-05-12 14:52:37 +02:00
SIInstrFormats.td
[AMDGPU] IsFlatScratch/Global -> FlatScratch/Global
2021-04-09 11:20:31 +02:00
SIInstrInfo.cpp
[AMDGPU] Add VReg_192/VReg_224 support for MIMG instructions
2021-07-22 10:42:15 +09:00
SIInstrInfo.h
[AMDGPU] Add TII::isIgnorableUse() to allow VOP rematerialization
2021-07-14 13:03:58 -07:00
SIInstrInfo.td
AMDGPU: Move zeroed FP high bits optimization to patterns
2021-06-22 12:47:56 -04:00
SIInstructions.td
[AMDGPU] Mark waterfall loops as SI_WATERFALL_LOOP
2021-07-13 12:15:08 +02:00
SIISelLowering.cpp
[AMDGPU] Add maximum NSA size limit ISA feature
2021-07-23 16:16:06 +09:00
SIISelLowering.h
[AMDGPU] NFC refactoring in isel for buffer access intrinsics
2021-07-21 11:12:49 +01:00
SILateBranchLowering.cpp
[AMDGPU] Allow frontends to disable null export for pixel shaders
2021-07-22 10:20:46 +09:00
SILoadStoreOptimizer.cpp
AMDGPU: Fix SILoadStoreOptimizer for gfx90a
2021-05-11 21:26:43 -04:00
SILowerControlFlow.cpp
[AMDGPU] Mark waterfall loops as SI_WATERFALL_LOOP
2021-07-13 12:15:08 +02:00
SILowerI1Copies.cpp
SILowerSGPRSpills.cpp
RegAlloc: Allow targets to split register allocation
2021-07-13 18:49:29 -04:00
SIMachineFunctionInfo.cpp
[AMDGPU] Init scratch only if necessary
2021-07-14 10:45:22 +02:00
SIMachineFunctionInfo.h
[AMDGPU] Serialize MFInfo::ScavengeFI
2021-05-07 11:15:25 +02:00
SIMachineScheduler.cpp
SIMachineScheduler.h
SIMemoryLegalizer.cpp
[AMDGPU] Update gfx90a memory model support
2021-06-30 04:05:22 +00:00
SIModeRegister.cpp
SIOptimizeExecMasking.cpp
SIOptimizeExecMaskingPreRA.cpp
[AMDGPU] SIOptimizeExecMaskingPreRA should check constant bus constraint when folds EXEC copy
2021-03-24 14:14:13 +03:00
SIOptimizeVGPRLiveRange.cpp
[AMDGPU] Improve killed check for vgpr optimization
2021-07-21 15:24:59 +02:00
SIPeepholeSDWA.cpp
SIPostRABundler.cpp
SIPreAllocateWWMRegs.cpp
[AMDGPU] Save WWM registers in functions
2021-04-23 18:09:24 +02:00
SIPreEmitPeephole.cpp
[AMDGPU] Remove set_gpr_idx instructions in conditional blocks
2021-04-30 22:15:45 +01:00
SIProgramInfo.cpp
SIProgramInfo.h
SIRegisterInfo.cpp
[AMDGPU] Add VReg_192/VReg_224 support for MIMG instructions
2021-07-22 10:42:15 +09:00
SIRegisterInfo.h
RegAlloc: Allow targets to split register allocation
2021-07-13 18:49:29 -04:00
SIRegisterInfo.td
[AMDGPU] Tidy SReg/SGPR definitions using template class
2021-07-17 11:26:46 +09:00
SISchedule.td
Revert "[MCA] [AMDGPU] Adding an implementation to AMDGPUCustomBehaviour for handling s_waitcnt instructions."
2021-07-07 20:48:42 -07:00
SIShrinkInstructions.cpp
[AMDGPU] Add VReg_192/VReg_224 support for MIMG instructions
2021-07-22 10:42:15 +09:00
SIWholeQuadMode.cpp
[AMDGPU] Fix WQM failure with single block inactive demote
2021-05-06 21:02:26 +09:00
SMInstructions.td
[AMDGPU] Set IsAtomicRet and IsAtomicNoRet on Real instructions
2021-06-16 12:23:29 +01:00
SOPInstructions.td
[AMDGPU][MC] Added missing isCall/isBranch flags
2021-07-16 14:59:10 +03:00
VIInstrFormats.td
VOP1Instructions.td
[AMDGPU] Mark all relevant VOP1 instructions rematerializable
2021-07-21 14:05:32 -07:00
VOP2Instructions.td
[AMDGPU] Mark relevant rematerializable VOP2 instructions
2021-07-21 14:24:59 -07:00
VOP3Instructions.td
[AMDGPU] Mark relevant rematerializable VOP3 instructions
2021-07-21 14:44:13 -07:00
VOP3PInstructions.td
[AMDGPU] Set VOP3P flag on Real instructions
2021-06-16 15:00:45 +01:00
VOPCInstructions.td
[AMDGPU] Set SALU, VALU and other instruction type flags on Real instructions
2021-06-16 13:36:02 +01:00
VOPInstructions.td
[AMDGPU] Set SALU, VALU and other instruction type flags on Real instructions
2021-06-16 13:36:02 +01:00
