Daniel Neilson f59acc15ad Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) ... Summary: This is a resurrection of work first proposed and discussed in Aug 2015: http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html and initially landed (but then backed out) in Nov 2015: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151109/312083.html The @llvm.memcpy/memmove/memset intrinsics currently have an explicit argument which is required to be a constant integer. It represents the alignment of the dest (and source), and so must be the minimum of the actual alignment of the two. This change is the first in a series that allows source and dest to each have their own alignments by using the alignment attribute on their arguments. In this change we: 1) Remove the alignment argument. 2) Add alignment attributes to the source & dest arguments. We, temporarily, require that the alignments for source & dest be equal. For example, code which used to read: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 100, i32 4, i1 false) will now read call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %dest, i8* align 4 %src, i32 100, i1 false) Downstream users may have to update their lit tests that check for @llvm.memcpy/memmove/memset call/declaration patterns. The following extended sed script may help with updating the majority of your tests, but it does not catch all possible patterns so some manual checking and updating will be required. s~declare void @llvm\.mem(set|cpy|move)\.p([^(]*)\((.*), i32, i1\)~declare void @llvm.mem\1.p\2(\3, i1)~g s~call void @llvm\.memset\.p([^(]*)i8\(i8([^*]*)\* (.*), i8 (.*), i8 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.memset.p\1i8(i8\2* \3, i8 \4, i8 \5, i1 \6)~g s~call void @llvm\.memset\.p([^(]*)i16\(i8([^*]*)\* (.*), i8 (.*), i16 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.memset.p\1i16(i8\2* \3, i8 \4, i16 \5, i1 \6)~g s~call void @llvm\.memset\.p([^(]*)i32\(i8([^*]*)\* (.*), i8 (.*), i32 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.memset.p\1i32(i8\2* \3, i8 \4, i32 \5, i1 \6)~g s~call void @llvm\.memset\.p([^(]*)i64\(i8([^*]*)\* (.*), i8 (.*), i64 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.memset.p\1i64(i8\2* \3, i8 \4, i64 \5, i1 \6)~g s~call void @llvm\.memset\.p([^(]*)i128\(i8([^*]*)\* (.*), i8 (.*), i128 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.memset.p\1i128(i8\2* \3, i8 \4, i128 \5, i1 \6)~g s~call void @llvm\.memset\.p([^(]*)i8\(i8([^*]*)\* (.*), i8 (.*), i8 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.memset.p\1i8(i8\2* align \6 \3, i8 \4, i8 \5, i1 \7)~g s~call void @llvm\.memset\.p([^(]*)i16\(i8([^*]*)\* (.*), i8 (.*), i16 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.memset.p\1i16(i8\2* align \6 \3, i8 \4, i16 \5, i1 \7)~g s~call void @llvm\.memset\.p([^(]*)i32\(i8([^*]*)\* (.*), i8 (.*), i32 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.memset.p\1i32(i8\2* align \6 \3, i8 \4, i32 \5, i1 \7)~g s~call void @llvm\.memset\.p([^(]*)i64\(i8([^*]*)\* (.*), i8 (.*), i64 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.memset.p\1i64(i8\2* align \6 \3, i8 \4, i64 \5, i1 \7)~g s~call void @llvm\.memset\.p([^(]*)i128\(i8([^*]*)\* (.*), i8 (.*), i128 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.memset.p\1i128(i8\2* align \6 \3, i8 \4, i128 \5, i1 \7)~g s~call void @llvm\.mem(cpy|move)\.p([^(]*)i8\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i8 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.mem\1.p\2i8(i8\3* \4, i8\5* \6, i8 \7, i1 \8)~g s~call void @llvm\.mem(cpy|move)\.p([^(]*)i16\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i16 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.mem\1.p\2i16(i8\3* \4, i8\5* \6, i16 \7, i1 \8)~g s~call void @llvm\.mem(cpy|move)\.p([^(]*)i32\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i32 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.mem\1.p\2i32(i8\3* \4, i8\5* \6, i32 \7, i1 \8)~g s~call void @llvm\.mem(cpy|move)\.p([^(]*)i64\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i64 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.mem\1.p\2i64(i8\3* \4, i8\5* \6, i64 \7, i1 \8)~g s~call void @llvm\.mem(cpy|move)\.p([^(]*)i128\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i128 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.mem\1.p\2i128(i8\3* \4, i8\5* \6, i128 \7, i1 \8)~g s~call void @llvm\.mem(cpy|move)\.p([^(]*)i8\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i8 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.mem\1.p\2i8(i8\3* align \8 \4, i8\5* align \8 \6, i8 \7, i1 \9)~g s~call void @llvm\.mem(cpy|move)\.p([^(]*)i16\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i16 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.mem\1.p\2i16(i8\3* align \8 \4, i8\5* align \8 \6, i16 \7, i1 \9)~g s~call void @llvm\.mem(cpy|move)\.p([^(]*)i32\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i32 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.mem\1.p\2i32(i8\3* align \8 \4, i8\5* align \8 \6, i32 \7, i1 \9)~g s~call void @llvm\.mem(cpy|move)\.p([^(]*)i64\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i64 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.mem\1.p\2i64(i8\3* align \8 \4, i8\5* align \8 \6, i64 \7, i1 \9)~g s~call void @llvm\.mem(cpy|move)\.p([^(]*)i128\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i128 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.mem\1.p\2i128(i8\3* align \8 \4, i8\5* align \8 \6, i128 \7, i1 \9)~g The remaining changes in the series will: Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing source and dest alignments. Step 3) Update Clang to use the new IRBuilder API. Step 4) Update Polly to use the new IRBuilder API. Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API, and those that use use MemIntrinsicInst::[get|set]Alignment() to use getDestAlignment() and getSourceAlignment() instead. Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the MemIntrinsicInst::[get|set]Alignment() methods. Reviewers: pete, hfinkel, lhames, reames, bollu Reviewed By: reames Subscribers: niosHD, reames, jholewinski, qcolombet, jfb, sanjoy, arsenm, dschuff, dylanmckay, mehdi_amini, sdardis, nemanjai, david2050, nhaehnle, javed.absar, sbc100, jgravelle-google, eraman, aheejin, kbarton, JDevlieghere, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, llvm-commits Differential Revision: https://reviews.llvm.org/D41675 llvm-svn: 322965		2018-01-19 17:13:12 +00:00
..
autohvx	[Hexagon] Cast elements to correct type when creating constant vector	2018-01-11 18:03:23 +00:00
intrinsics	[Hexagon] Fix operand-swapping PatFrag for atomic stores	2017-12-15 20:13:57 +00:00
loop-idiom	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
vect	[Hexagon] Rewrite LowerVECTOR_SHUFFLE for 32-/64-bit vectors	2018-01-15 18:33:33 +00:00
absaddr-store.ll
absimm.ll
addaddi.ll	[Hexagon] Add extra pattern for S4_addaddi	2017-10-23 19:07:50 +00:00
adde.ll	[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG	2017-03-09 16:29:30 +00:00
addh-sext-trunc.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
addh-shifted.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
addh.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
addr-calc-opt.ll	[Hexagon] Improve balancing of address calculation	2016-07-29 15:15:35 +00:00
addrmode-globoff.mir	[Hexagon] Generate proper offset in opt-addr-mode	2017-04-19 15:15:51 +00:00
addrmode-indoff.ll	[Hexagon] Reorganize and update instruction patterns	2017-10-20 19:33:12 +00:00
addrmode-keepdeadphis.mir	[Hexagon] Keep all phi nodes when building DFG in addr-mode-opt	2017-06-29 15:55:59 +00:00
addrmode-rr-to-io.mir	[Hexagon] Fix store conversion from rr to io in optimize addressing modes	2017-10-19 16:59:22 +00:00
adjust-latency-stackST.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
alu64.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
always-ext.ll
anti-dep-partial.mir	Move .mir tests to appropriate directories	2016-12-09 19:08:15 +00:00
args.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
ashift-left-right.ll
Atomics.ll
avoid-predspill-calleesaved.ll	[Hexagon] Start using regmasks on calls	2017-02-17 22:14:51 +00:00
avoid-predspill.ll
bank-conflict-load.mir	[Hexagon] Check for potential bank conflicts in post-RA scheduling	2017-08-28 18:36:21 +00:00
barrier-flag.ll
base-offset-addr.ll
base-offset-post.ll
bit-bitsplit-at.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
bit-bitsplit-src.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
bit-bitsplit.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
bit-eval.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
bit-ext-sat.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
bit-extract-off.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
bit-extract.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
bit-extractu-half.ll
bit-gen-rseq.ll	MachinePipeliner pass that implements Swing Modulo Scheduling	2016-07-29 16:44:44 +00:00
bit-has.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
bit-loop-rc-mismatch.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
bit-loop.ll
bit-phi.ll	[Hexagon] Do not insert instructions before PHI nodes	2017-03-07 14:20:19 +00:00
bit-rie.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
bit-skip-byval.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
bit-validate-reg.ll	[Hexagon] Generate extract instructions more aggressively	2017-02-28 23:27:33 +00:00
bit-visit-flowq.ll	[Hexagon] Clear the flow queue after visiting a single instruction	2016-09-13 14:36:55 +00:00
bitconvert-vector.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
bitmanip.ll	[Hexagon] Patterns for CTPOP, BSWAP and BITREVERSE	2017-02-23 15:02:09 +00:00
block-addr.ll	[Hexagon] Reorganize and update instruction patterns	2017-10-20 19:33:12 +00:00
block-ranges-nodef.ll
branch-folder-hoist-kills.mir	[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.	2017-12-07 10:40:31 +00:00
branch-non-mbb.ll
branchfolder-insert-impdef.mir	Insert IMPLICIT_DEFS for undef uses in tail merging	2017-09-06 20:45:24 +00:00
branchfolder-keep-impdef.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
BranchPredict.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
brev_ld.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
brev_st.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
bugAsmHWloop.ll
build-vector-shuffle.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
build-vector-v4i8-zext.ll	[Hexagon] Make sure to zero-extend bytes before building a vector	2017-11-28 19:13:17 +00:00
builtin-expect.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
builtin-prefetch-offset.ll
builtin-prefetch.ll
call-ret-i1.ll	[Hexagon] Return the correct chain edge for i1 function calls	2017-10-23 19:35:25 +00:00
calling-conv-2.ll
callr-dep-edge.ll
cext-check.ll
cext-opt-basic.mir	MIR: Print the register class or bank in vreg defs	2017-10-24 18:04:54 +00:00
cext-opt-numops.mir	[Hexagon] Fix an incorrect assertion in HexagonConstExtenders.cpp	2017-10-27 18:52:28 +00:00
cext-opt-range-offset.mir	[Hexagon] Account for negative offset when limiting max deviation	2017-10-25 18:46:40 +00:00
cext-valid-packet1.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
cext-valid-packet2.ll
cext.ll
cexti16.ll
cfgopt-fall-through.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
cfi-late.ll
cfi-offset.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
checktabs.ll
circ_ld.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
circ_ldd_bug.ll	[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output	2017-11-30 12:12:19 +00:00
circ_ldw.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
circ_st.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
circ-load-isel.ll
clr_set_toggle.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
cmp_pred2.ll
cmp_pred_reg.ll
cmp_pred.ll
cmp-extend.ll
cmp-promote.ll
cmp-to-genreg.ll
cmp-to-predreg.ll
cmp.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
cmpb_pred.ll
cmpb-dec-imm.ll	[Hexagon] Add patterns for cmpb/cmph with immediate arguments	2017-10-13 15:43:12 +00:00
cmpb-eq.ll
cmph-gtu.ll	[Hexagon] Add patterns for cmpb/cmph with immediate arguments	2017-10-13 15:43:12 +00:00
combine_ir.ll
combine.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
common-gep-basic.ll
common-gep-icm.ll
common-gep-inbounds.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
compound.ll	[Hexagon] Start using regmasks on calls	2017-02-17 22:14:51 +00:00
const64.ll
const-pool-tf.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
constp-clb.ll	[Hexagon] Implement MI-level constant propagation	2016-07-28 20:01:59 +00:00
constp-combine-neg.ll	[Hexagon] Implement buildVector32 and buildVector64 as utility functions	2017-11-22 20:56:23 +00:00
constp-ctb.ll	[Hexagon] Implement MI-level constant propagation	2016-07-28 20:01:59 +00:00
constp-extract.ll	[Hexagon] Implement MI-level constant propagation	2016-07-28 20:01:59 +00:00
constp-physreg.ll	[Hexagon] Implement MI-level constant propagation	2016-07-28 20:01:59 +00:00
constp-rewrite-branches.ll	[Hexagon] Implement MI-level constant propagation	2016-07-28 20:01:59 +00:00
constp-rseq.ll	[Hexagon] Implement MI-level constant propagation	2016-07-28 20:01:59 +00:00
constp-vsplat.ll	[Hexagon] Implement MI-level constant propagation	2016-07-28 20:01:59 +00:00
convert_const_i1_to_i8.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
convert-to-dot-old.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
convertdptoint.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
convertdptoll.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
convertsptoint.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
convertsptoll.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
copy-to-combine-dbg.ll	[Hexagon] Check for block end when skipping debug instructions	2016-08-24 22:36:35 +00:00
csr-func-usedef.ll
ctor.ll
dadd.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
dead-store-stack.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
dmul.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
double.ll
doubleconvert-ieee-rnd-near.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
dsub.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
dualstore.ll
duplex-addi-global-imm.mir	[Hexagon] Fix typo in a testcase	2017-06-22 16:25:46 +00:00
duplex.ll	[CodeGen] Always use printReg to print registers in both MIR and debug	2017-11-30 16:12:24 +00:00
early-if-conversion-bug1.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
early-if-debug.mir	[CodeGen] Always use printReg to print registers in both MIR and debug	2017-11-30 16:12:24 +00:00
early-if-merge-loop.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
early-if-phi-i1.ll	[Hexagon] Add -march=hexagon to a testcase	2017-03-21 16:59:40 +00:00
early-if-spare.ll
early-if-vecpi.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
early-if-vecpred.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
early-if.ll
eh_return.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
eliminate-pred-spill.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
expand-condsets-basic.ll
expand-condsets-dead-bad.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
expand-condsets-dead-pred.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
expand-condsets-def-undef.mir	MIR: Print the register class or bank in vreg defs	2017-10-24 18:04:54 +00:00
expand-condsets-extend.ll	[Hexagon] Deal with undefs when extending live intervals	2016-09-01 13:59:35 +00:00
expand-condsets-imm.mir	MIR: Print the register class or bank in vreg defs	2017-10-24 18:04:54 +00:00
expand-condsets-impuse.mir	MIR: Print the register class or bank in vreg defs	2017-10-24 18:04:54 +00:00
expand-condsets-pred-undef.ll
expand-condsets-rm-reg.mir	[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output	2017-11-30 12:12:19 +00:00
expand-condsets-rm-segment.ll
expand-condsets-same-inputs.mir	[Hexagon] Don't expand mux instructions with both sources identical	2016-10-31 15:45:09 +00:00
expand-condsets-undef2.ll	[Hexagon] Check for empty live interval	2016-08-19 14:29:43 +00:00
expand-condsets-undef.ll
expand-condsets-undefvni.ll	Missed a check for UndefVI in r306466	2017-06-28 15:46:16 +00:00
expand-vselect-kill.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
expand-vstorerw-undef2.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
expand-vstorerw-undef.ll	[Hexagon] Allow construction of HVX vector predicates	2017-12-20 20:49:43 +00:00
extload-combine.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
extract-basic.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
fadd.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
fcmp.ll
find-loop-instr.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
fixed-spill-mutable.ll	Fixed spill stack objects are mutable	2016-08-31 13:52:17 +00:00
float-amode.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
float.ll
floatconvert-ieee-rnd-near.ll
fminmax.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
fmul.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
fpelim-basic.ll	[Hexagon] Implement frame pointer elimination with -fomit-frame-pointer	2017-06-30 21:21:40 +00:00
frame-offset-overflow.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
fsel.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
fsub.ll	[Hexagon] Preclude non-memory test from being optimized away. NFC.	2017-07-05 13:08:03 +00:00
fusedandshift.ll	[Hexagon] Generate extract instructions more aggressively	2017-02-28 23:27:33 +00:00
gp-plus-offset-load.ll
gp-plus-offset-store.ll
gp-rel.ll	[Hexagon] Adding gp+ to the syntax of gp-relative instructions	2017-02-06 23:18:57 +00:00
hasfp-crash1.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
hasfp-crash2.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
hexagon_vector_loop_carried_reuse_constant.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
hexagon_vector_loop_carried_reuse.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
hvx-nontemporal.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
hwloop1.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
hwloop2.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
hwloop3.ll
hwloop4.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
hwloop5.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
hwloop-cleanup.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
hwloop-const.ll
hwloop-crit-edge.ll	[LSR] Don't try and create post-inc expressions on non-rotated loops	2016-08-15 07:53:03 +00:00
hwloop-dbg.ll
hwloop-le.ll
hwloop-loop1.ll	[Hexagon] Reorganize and update instruction patterns	2017-10-20 19:33:12 +00:00
hwloop-lt1.ll
hwloop-lt.ll
hwloop-missed.ll
hwloop-ne.ll
hwloop-noreturn-call.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
hwloop-ph-deadcode.ll
hwloop-pos-ivbump1.ll
hwloop-preh.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
hwloop-preheader.ll
hwloop-range.ll
hwloop-recursion.ll
hwloop-redef-imm.mir	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
hwloop-wrap2.ll
hwloop-wrap.ll
i1_VarArg.ll
i8_VarArg.ll
i16_VarArg.ll
idxload-with-zero-offset.ll
ifcvt-common-kill.mir	[IfConversion] Remove kill flags from common instructions as well	2017-09-06 17:57:13 +00:00
ifcvt-diamond-bad.ll
ifcvt-diamond-bug-2016-08-26.ll	[Hexagon] Reorganize and update instruction patterns	2017-10-20 19:33:12 +00:00
ifcvt-edge-weight.ll	[CodeGen] Unify MBB reference format in both MIR and debug output	2017-12-04 17:18:51 +00:00
ifcvt-impuse-livein.mir	[IfConversion] More simple, correct dead/kill liveness handling	2017-09-14 15:53:11 +00:00
ifcvt-live-subreg.mir	[IfConversion] More simple, correct dead/kill liveness handling	2017-09-14 15:53:11 +00:00
ifcvt-simple-bprob.ll	[IfConversion] Only renormalize probabilities if branches are analyzable	2017-03-06 19:12:42 +00:00
indirect-br.ll
inline-asm-a.ll	[Hexagon] Add inline-asm constraint 'a' for modifier register class	2017-07-21 17:51:27 +00:00
inline-asm-bad-constraint.ll	[Hexagon] Report error instead of crashing on wrong inline-asm constraints	2017-10-20 20:24:44 +00:00
inline-asm-hexagon.ll	[Hexagon] Add support for proper handling of H and L constraints	2016-07-26 17:31:02 +00:00
inline-asm-i1.ll	[Hexagon] Add RUN line to test	2016-08-19 19:36:35 +00:00
inline-asm-qv.ll	[Hexagon] Remove trailing spaces, NFC	2017-11-22 20:43:00 +00:00
inline-asm-vecpred128.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
insert4.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
insert-basic.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
invalid-dotnew-attempt.mir	[Hexagon] Fix dependence check in the packetizer	2017-06-01 18:02:40 +00:00
is-legal-void.ll	[Hexagon] Do not check alignment for unsized types in isLegalAddressingMode	2016-08-03 15:06:18 +00:00
isel-combine-half.ll	[Hexagon] Add patterns to select A2_combine_ll and its variants	2017-11-22 20:55:41 +00:00
isel-exti1.ll	[Hexagon] Fix instruction selection for sign-extending i1 to i64	2017-02-28 22:37:01 +00:00
isel-i1arg-crash.ll	[Hexagon] Fix lowering of formal arguments of type i1	2017-03-01 17:30:10 +00:00
isel-op-zext-i1.ll	[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG	2017-03-09 16:29:30 +00:00
isel-prefer.ll	[Hexagon] Add patterns to select A2_combine_ll and its variants	2017-11-22 20:55:41 +00:00
isel-simplify-crash.ll	[Hexagon] Add a bitcast to required type in LowerHvxMul	2018-01-05 20:45:34 +00:00
jt-in-text.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
lit.local.cfg
livephysregs-add-pristines.mir	[IfConversion] More simple, correct dead/kill liveness handling	2017-09-14 15:53:11 +00:00
livephysregs-lane-masks2.mir	Insert IMPLICIT_DEFS for undef uses in tail merging	2017-09-06 20:45:24 +00:00
livephysregs-lane-masks.mir	[Hexagon] Add support for Hexagon V65	2017-12-11 18:57:54 +00:00
loadi1-G0.ll
loadi1-v4-G0.ll
loadi1-v4.ll
loadi1.ll
long-calls.ll	[Hexagon] Add target feature to generate long calls	2016-07-25 14:42:11 +00:00
loop-prefetch.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
lower-extract-subvector.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
macint.ll
maxd.ll
maxh.ll
maxud.ll
maxuw.ll
maxw.ll
mem-fi-add.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
memcpy-likely-aligned.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
memops1.ll
memops2.ll
memops3.ll
memops-stack.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
memops.ll
mind.ll
minu-zext-8.ll
minu-zext-16.ll
minud.ll
minuw.ll
minw.ll
misaligned_double_vector_store_not_fast.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
misaligned-access.ll
misched-top-rptracker-sync.ll
mpy.ll
mul64-sext.ll	[Hexagon] Improve code generation for 32x32-bit multiplication	2017-05-30 17:47:51 +00:00
mulh.ll	[Hexagon] Remove trailing spaces, NFC	2017-11-22 20:43:00 +00:00
mulhs.ll	[Hexagon] Add pattern for 64-bit mulhs	2016-08-08 19:24:25 +00:00
multi-cycle.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
mux-basic.ll
mux-kill1.mir	[Hexagon] Use LivePhysRegs to fix up kills in HexagonGenMux	2017-06-22 20:43:02 +00:00
mux-kill2.mir	[Hexagon] Use LivePhysRegs to fix up kills in HexagonGenMux	2017-06-22 20:43:02 +00:00
mux-kill3.mir	[Hexagon] Use LivePhysRegs to fix up kills in HexagonGenMux	2017-06-22 20:43:02 +00:00
mux-undef.ll	[Hexagon] Skip mux generation when predicate register is undefined	2017-06-08 20:56:36 +00:00
newify-crash.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
newvaluejump2.ll	[Hexagon] Remove trailing spaces, NFC	2017-11-22 20:43:00 +00:00
newvaluejump3.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
newvaluejump-c4.mir	[Hexagon] Recognize C4_cmpneqi, C4_cmpltei and C4_cmplteui in NewValueJump	2017-07-24 19:35:48 +00:00
newvaluejump-kill2.mir	[Hexagon] Update kills in hexagon-nvj even more properly than before	2017-06-27 18:37:16 +00:00
newvaluejump-kill.ll	[Hexagon] Properly update kill flags in HexagonNewValueJump	2017-06-22 21:11:44 +00:00
newvaluejump-solo.mir	[Hexagon] Fix wrong check in test/CodeGen/Hexagon/newvaluejump-solo.mir	2017-11-30 21:23:19 +00:00
newvaluejump.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
newvalueSameReg.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
newvaluestore.ll
NVJumpCmp.ll
opt-addr-mode.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
opt-fabs.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
opt-fneg.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
opt-spill-volatile.ll	Add address space mangling to lifetime intrinsics	2017-04-10 20:18:21 +00:00
packetize_cond_inst.ll
packetize-cfi-location.ll	[Hexagon] Insert CFI instructions before throwing calls	2016-07-28 19:13:46 +00:00
packetize-load-store-aliasing.mir	[Packetizer] Add function to check for aliasing between instructions	2017-10-20 22:08:40 +00:00
packetize-nvj-no-prune.mir	[Hexagon] Make sure that new-value jump is packetized with producer	2017-10-11 21:20:43 +00:00
packetize-return-arg.ll	[Hexagon] Packetize return value setup with the return instruction	2016-08-23 16:01:01 +00:00
packetize-tailcall-arg.ll
peephole-kill-flags.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
peephole-op-swap.ll
pic-jumptables.ll
pic-local.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
pic-regusage.ll
pic-simple.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
pic-static.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
plt-rel.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
post-inc-aa-metadata.ll	[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.	2017-12-07 10:40:31 +00:00
post-ra-kill-update.mir	ScheduleDAGInstrs: Fix fixupKills()	2017-05-27 02:50:50 +00:00
postinc-baseoffset.mir	[Hexagon] Fix a bug in r308502: post-inc offset is always 0	2017-07-19 19:17:32 +00:00
postinc-load.ll
postinc-offset.ll
postinc-store.ll
PR33749.ll	[Hexagon] Reorganize and update instruction patterns	2017-10-20 19:33:12 +00:00
pred-absolute-store.ll	[RDF] Remove the map of reaching defs from copy propagation	2017-03-10 22:44:24 +00:00
pred-gp.ll
pred-instrs.ll
predicate-copy.ll
predicate-logical.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
predicate-rcmp.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
propagate-vcombine.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
rdf-copy-undef2.ll	Add address space mangling to lifetime intrinsics	2017-04-10 20:18:21 +00:00
rdf-copy.ll	[Hexagon] Remove trailing spaces, NFC	2017-11-22 20:43:00 +00:00
rdf-cover-use.ll	[RDF] Remove covered parts of reached uses for phi and use in same block	2017-05-05 22:10:32 +00:00
rdf-dead-loop.ll
rdf-def-mask.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
rdf-ehlabel-live.mir	[Hexagon] Make sure that RDF does not remove EH_LABELs	2017-11-21 21:05:51 +00:00
rdf-extra-livein.ll	[RDF] Fix liveness propagation through shadows	2016-10-03 20:17:20 +00:00
rdf-filter-defs.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
rdf-ignore-undef.ll	[RDF] Ignore undef use operands	2016-09-06 17:03:13 +00:00
rdf-inline-asm-fixed.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
rdf-inline-asm.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
rdf-multiple-phis-up.ll	[RDF] Further improve handling of multiple phis reached from shadows	2016-09-08 20:48:42 +00:00
rdf-phi-shadows.ll	[RDF] Fix liveness analysis for phi nodes with shadow uses	2016-09-07 20:37:05 +00:00
rdf-phi-up.ll	Add address space mangling to lifetime intrinsics	2017-04-10 20:18:21 +00:00
rdf-reset-kills.ll
readcyclecounter.ll	[Hexagon] Implement @llvm.readcyclecounter()	2017-02-22 22:28:47 +00:00
reg-scavengebug-3.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
reg-scavenger-valid-slot.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
regalloc-bad-undef.mir	[MachineOperand][MIR] Add isRenamable to MachineOperand.	2017-12-12 17:53:59 +00:00
regalloc-block-overlap.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
regalloc-liveout-undef.mir	MIR: Print the register class or bank in vreg defs	2017-10-24 18:04:54 +00:00
relax.ll
remove_lsr.ll
remove-endloop.ll
restore-single-reg.ll
ret-struct-by-val.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
runtime-stkchk.ll	Add address space mangling to lifetime intrinsics	2017-04-10 20:18:21 +00:00
sdata-array.ll	[Hexagon] Reorganize and update instruction patterns	2017-10-20 19:33:12 +00:00
sdata-basic.ll
sdr-basic.ll
sdr-shr32.ll
section_7275.ll	[Hexagon] Adding gp+ to the syntax of gp-relative instructions	2017-02-06 23:18:57 +00:00
select-instr-align.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
sf-min-max.ll	[Hexagon] Add extra patterns for single-precision min/max instructions	2016-08-10 17:56:24 +00:00
sffms.ll	[Hexagon] Improvements to handling and generation of FP instructions	2016-08-19 13:34:31 +00:00
shrink-frame-basic.ll
signed_immediates.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
simple_addend.ll
simpletailcall.ll
split-const32-const64.ll	[Hexagon] Remove trailing spaces, NFC	2017-11-22 20:43:00 +00:00
stack-align1.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
stack-align2.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
stack-align-reset.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
stack-alloca1.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
stack-alloca2.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
static.ll	[Hexagon] Adding gp+ to the syntax of gp-relative instructions	2017-02-06 23:18:57 +00:00
store-imm-amode.ll	[Hexagon] Reorganize and update instruction patterns	2017-10-20 19:33:12 +00:00
store-imm-large-stack.ll	[Hexagon] Recognize potential offset overflow for store-imm to stack	2017-06-22 14:11:23 +00:00
store-imm-stack-object.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
store-shift.ll	[Hexagon] Reorganize and update instruction patterns	2017-10-20 19:33:12 +00:00
store-widen-aliased-load.ll
store-widen-negv2.ll
store-widen-negv.ll
store-widen.ll
storerd-io-over-rr.ll	[Hexagon] Prefer _io over _rr for 64-bit store with constant offset	2016-08-02 18:50:05 +00:00
storerinewabs.ll
struct_args_large.ll
struct_args.ll	[Hexagon] Bitwise operations for insert/extract word not simplified	2016-07-26 18:30:11 +00:00
sube.ll	[Hexagon] Propagate zext of i1 into arithmetic code in selection DAG	2017-03-09 16:29:30 +00:00
subi-asl.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
SUnit-boundary-prob.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
switch-lut-explicit-section.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
switch-lut-function-section.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
switch-lut-multiple-functions.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
switch-lut-text-section.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
swp-const-tc.ll	[LSR / TTI / SystemZ] Eliminate TargetTransformInfo::isFoldableMemAccess()	2017-08-09 11:28:01 +00:00
swp-dag-phi.ll	MachinePipeliner pass that implements Swing Modulo Scheduling	2016-07-29 16:44:44 +00:00
swp-epilog-phi10.ll	Fix two bugs in the pipeliner in renaming phis in the prolog and epilog	2016-12-22 18:49:55 +00:00
swp-epilog-reuse-1.ll	[Pipeliner] Fix an asssert due to invalid Phi in the epilog	2016-08-16 14:29:24 +00:00
swp-epilog-reuse.ll	MachinePipeliner pass that implements Swing Modulo Scheduling	2016-07-29 16:44:44 +00:00
swp-matmul-bitext.ll	[Hexagon] Use automatically-generated scheduling information for HVX	2017-05-03 20:10:36 +00:00
swp-max.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
swp-multi-loops.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
swp-order-copies.ll	[Pipeliner] Improve serialization order for post-increments	2017-10-11 15:51:44 +00:00
swp-prolog-phi4.ll	Fix two bugs in the pipeliner in renaming phis in the prolog and epilog	2016-12-22 18:49:55 +00:00
swp-stages4.ll	[Hexagon] Adjust patterns to reflect instruction selection preferences	2017-10-27 22:24:49 +00:00
swp-stages5.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
swp-vect-dotprod.ll	MachinePipeliner pass that implements Swing Modulo Scheduling	2016-07-29 16:44:44 +00:00
swp-vmult.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
swp-vsum.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
tail-call-mem-intrinsics.ll	Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)	2018-01-19 17:13:12 +00:00
tail-call-trunc.ll
tail-dup-subreg-abort.ll
tail-dup-subreg-map.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
tailcall_fastcc_ccc.ll	[Hexagon] Allow tail-call optimization when mixing C and fast calling conv	2016-08-19 15:02:18 +00:00
target-flag-ext.mir	[Hexagon] Fix check for HMOTF_ConstExtend operand flag	2017-07-10 18:38:52 +00:00
tfr-to-combine.ll	[Hexagon] Reorganize and update instruction patterns	2017-10-20 19:33:12 +00:00
tls_pic.ll	[Hexagon] Reorganize and update instruction patterns	2017-10-20 19:33:12 +00:00
tls_static.ll	[Hexagon] Reorganize and update instruction patterns	2017-10-20 19:33:12 +00:00
trap-unreachable.ll	[Hexagon] Add option to generate calls to "abort" for "unreachable"	2017-09-06 16:22:55 +00:00
two-crash.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
undo-dag-shift.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
union-1.ll
unreachable-mbb-phi-subreg.mir	MIR: Print the register class or bank in vreg defs	2017-10-24 18:04:54 +00:00
usr-ovf-dep.ll
v6vec-vprint.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
v60-cur.ll	[Hexagon] Allow construction of HVX vector predicates	2017-12-20 20:49:43 +00:00
v60-vsel1.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
v60Intrins.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
v60small.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
v60Vasr.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
vaddh.ll	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
validate-offset.ll
vassign-to-combine.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
vdmpy-halide-test.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
vec-pred-spill1.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
vec-vararg-align.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
vector-align.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
vector-ext-load.ll	[Hexagon] Expand sext- and zextloads of vector types, not just extloads	2016-09-08 17:42:14 +00:00
vload-postinc-sel.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
vmpa-halide-test.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
vpack_eo.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
vselect-pseudo.ll	[Hexagon] New HVX target features.	2017-10-18 18:07:07 +00:00
vsplat-isel.ll
zextloadi1.ll	[Hexagon] Minimize number of repeated constant extenders	2017-10-13 19:02:59 +00:00