2008-02-10 19:45:23 +01:00
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//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
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2005-04-21 22:59:05 +02:00
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//
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2003-10-20 22:19:47 +02:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:59:42 +01:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-21 22:59:05 +02:00
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//
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2003-10-20 22:19:47 +02:00
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//===----------------------------------------------------------------------===//
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2002-10-26 01:00:40 +02:00
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//
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// This file describes an abstract interface used to get information about a
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// target machines register file. This information is used for a variety of
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// purposed, especially register allocation.
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//
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//===----------------------------------------------------------------------===//
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2008-02-10 19:45:23 +01:00
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#ifndef LLVM_TARGET_TARGETREGISTERINFO_H
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#define LLVM_TARGET_TARGETREGISTERINFO_H
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2002-10-26 01:00:40 +02:00
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2011-06-16 19:42:25 +02:00
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#include "llvm/ADT/ArrayRef.h"
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2012-12-03 18:02:12 +01:00
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/ValueTypes.h"
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2013-01-02 12:36:10 +01:00
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#include "llvm/IR/CallingConv.h"
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2012-12-03 18:02:12 +01:00
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#include "llvm/MC/MCRegisterInfo.h"
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2004-02-25 22:55:45 +01:00
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#include <cassert>
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#include <functional>
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2002-10-26 01:00:40 +02:00
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2003-11-11 23:41:34 +01:00
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namespace llvm {
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2007-02-27 22:08:07 +01:00
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class BitVector;
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2002-12-15 21:06:35 +01:00
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class MachineFunction;
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2007-02-27 22:08:07 +01:00
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class RegScavenger;
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Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE
instructions.
e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12
After REG_SEQUENCE is eliminated, we are left with:
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible,
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.
llvm-svn: 103835
2010-05-15 01:21:14 +02:00
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template<class T> class SmallVectorImpl;
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2012-12-03 22:17:00 +01:00
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class VirtRegMap;
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2010-12-14 19:53:39 +01:00
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class raw_ostream;
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2002-11-20 19:54:53 +01:00
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2011-07-23 02:47:46 +02:00
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class TargetRegisterClass {
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2002-11-20 19:54:53 +01:00
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public:
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2012-11-29 03:39:28 +01:00
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typedef const MCPhysReg* iterator;
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typedef const MCPhysReg* const_iterator;
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2012-02-09 13:35:37 +01:00
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typedef const MVT::SimpleValueType* vt_iterator;
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2006-07-19 07:58:18 +02:00
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typedef const TargetRegisterClass* const * sc_iterator;
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2012-03-01 14:37:55 +01:00
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// Instance variables filled by tablegen, do not use!
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2011-07-23 02:47:46 +02:00
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const MCRegisterClass *MC;
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2006-02-22 00:51:58 +01:00
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const vt_iterator VTs;
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2012-05-03 20:17:32 +02:00
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const uint32_t *SubClassMask;
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2012-05-04 00:49:00 +02:00
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const uint16_t *SuperRegIndices;
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2006-05-11 09:31:44 +02:00
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const sc_iterator SuperClasses;
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2012-11-29 03:39:28 +01:00
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ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
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2010-07-08 21:46:25 +02:00
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2011-07-23 02:47:46 +02:00
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/// getID() - Return the register class ID number.
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///
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unsigned getID() const { return MC->getID(); }
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/// getName() - Return the register class name for debugging.
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///
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const char *getName() const { return MC->getName(); }
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/// begin/end - Return all of the registers in this class.
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///
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iterator begin() const { return MC->begin(); }
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iterator end() const { return MC->end(); }
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/// getNumRegs - Return the number of registers in this class.
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///
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unsigned getNumRegs() const { return MC->getNumRegs(); }
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/// getRegister - Return the specified register in the class.
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///
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unsigned getRegister(unsigned i) const {
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return MC->getRegister(i);
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}
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/// contains - Return true if the specified register is included in this
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/// register class. This does not include virtual registers.
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bool contains(unsigned Reg) const {
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return MC->contains(Reg);
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}
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/// contains - Return true if both registers are in this class.
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bool contains(unsigned Reg1, unsigned Reg2) const {
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return MC->contains(Reg1, Reg2);
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}
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/// getSize - Return the size of the register in bytes, which is also the size
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/// of a stack slot allocated to hold a spilled copy of this register.
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unsigned getSize() const { return MC->getSize(); }
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/// getAlignment - Return the minimum required alignment for a register of
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/// this class.
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unsigned getAlignment() const { return MC->getAlignment(); }
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/// getCopyCost - Return the cost of copying a value between two registers in
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/// this class. A negative number means the register class is very expensive
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/// to copy e.g. status flag register classes.
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int getCopyCost() const { return MC->getCopyCost(); }
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/// isAllocatable - Return true if this register class may be used to create
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/// virtual registers.
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bool isAllocatable() const { return MC->isAllocatable(); }
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2005-12-01 05:51:06 +01:00
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/// hasType - return true if this TargetRegisterClass has the ValueType vt.
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///
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2009-08-11 00:56:29 +02:00
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bool hasType(EVT vt) const {
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2010-11-03 13:17:33 +01:00
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for(int i = 0; VTs[i] != MVT::Other; ++i)
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2012-02-09 13:35:37 +01:00
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if (EVT(VTs[i]) == vt)
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2005-12-01 05:51:06 +01:00
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return true;
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return false;
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}
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2009-10-01 22:45:06 +02:00
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2006-05-09 08:35:30 +02:00
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/// vt_begin / vt_end - Loop over all of the value types that can be
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/// represented by values in this register class.
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2006-02-22 00:51:58 +01:00
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vt_iterator vt_begin() const {
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return VTs;
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}
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vt_iterator vt_end() const {
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vt_iterator I = VTs;
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2010-11-03 13:17:33 +01:00
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while (*I != MVT::Other) ++I;
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2006-02-22 00:51:58 +01:00
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return I;
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}
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2006-05-09 08:35:30 +02:00
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2010-02-10 17:03:48 +01:00
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/// hasSubClass - return true if the specified TargetRegisterClass
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2011-10-01 00:19:07 +02:00
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/// is a proper sub-class of this TargetRegisterClass.
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bool hasSubClass(const TargetRegisterClass *RC) const {
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return RC != this && hasSubClassEq(RC);
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2006-05-09 08:35:30 +02:00
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}
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2011-10-01 00:19:07 +02:00
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/// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
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2011-06-01 17:32:10 +02:00
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/// class.
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bool hasSubClassEq(const TargetRegisterClass *RC) const {
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2011-10-01 00:19:07 +02:00
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unsigned ID = RC->getID();
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return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
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2006-05-09 08:35:30 +02:00
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}
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2009-10-01 22:45:06 +02:00
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2007-07-26 10:01:58 +02:00
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/// hasSuperClass - return true if the specified TargetRegisterClass is a
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2011-10-01 00:19:07 +02:00
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/// proper super-class of this TargetRegisterClass.
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bool hasSuperClass(const TargetRegisterClass *RC) const {
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return RC->hasSubClass(this);
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2006-05-11 09:31:44 +02:00
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}
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2011-10-01 00:19:07 +02:00
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/// hasSuperClassEq - Returns true if RC is a super-class of or equal to this
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2011-06-01 17:32:10 +02:00
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/// class.
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bool hasSuperClassEq(const TargetRegisterClass *RC) const {
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2011-10-01 00:19:07 +02:00
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return RC->hasSubClassEq(this);
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2011-06-01 17:32:10 +02:00
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}
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2011-10-01 00:19:07 +02:00
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/// getSubClassMask - Returns a bit vector of subclasses, including this one.
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/// The vector is indexed by class IDs, see hasSubClassEq() above for how to
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/// use it.
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2012-03-05 06:37:41 +01:00
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const uint32_t *getSubClassMask() const {
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2011-10-01 00:19:07 +02:00
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return SubClassMask;
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2006-05-11 09:31:44 +02:00
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}
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2009-10-01 22:45:06 +02:00
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2012-05-04 00:49:00 +02:00
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/// getSuperRegIndices - Returns a 0-terminated list of sub-register indices
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2012-07-30 22:09:37 +02:00
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/// that project some super-register class into this register class. The list
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2012-05-04 00:49:00 +02:00
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/// has an entry for each Idx such that:
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///
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/// There exists SuperRC where:
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/// For all Reg in SuperRC:
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/// this->contains(Reg:Idx)
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///
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const uint16_t *getSuperRegIndices() const {
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return SuperRegIndices;
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}
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2011-10-01 00:19:07 +02:00
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/// getSuperClasses - Returns a NULL terminated list of super-classes. The
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/// classes are ordered by ID which is also a topological ordering from large
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/// to small classes. The list does NOT include the current class.
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sc_iterator getSuperClasses() const {
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return SuperClasses;
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2006-05-11 09:31:44 +02:00
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}
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2009-01-23 03:15:19 +01:00
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2009-04-13 17:38:05 +02:00
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/// isASubClass - return true if this TargetRegisterClass is a subset
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/// class of at least one other TargetRegisterClass.
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2009-01-23 03:15:19 +01:00
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bool isASubClass() const {
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return SuperClasses[0] != 0;
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}
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2009-10-01 22:45:06 +02:00
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2011-06-16 19:42:25 +02:00
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/// getRawAllocationOrder - Returns the preferred order for allocating
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/// registers from this register class in MF. The raw order comes directly
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/// from the .td file and may include reserved registers that are not
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/// allocatable. Register allocators should also make sure to allocate
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/// callee-saved registers only after all the volatiles are used. The
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/// RegisterClassInfo class provides filtered allocation orders with
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/// callee-saved registers moved to the end.
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///
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/// The MachineFunction argument can be used to tune the allocatable
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/// registers based on the characteristics of the function, subtarget, or
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/// other criteria.
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///
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/// By default, this method returns all registers in the class.
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///
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2012-11-29 03:39:28 +01:00
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ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
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2012-03-01 14:37:55 +01:00
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return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
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2011-06-16 19:42:25 +02:00
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}
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2002-11-20 19:54:53 +01:00
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};
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2011-06-24 03:44:41 +02:00
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/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
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/// registers. These are used by codegen, not by MC.
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struct TargetRegisterInfoDesc {
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unsigned CostPerUse; // Extra cost of instructions using register.
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bool inAllocatableClass; // Register belongs to an allocatable regclass.
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};
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2002-11-20 19:54:53 +01:00
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2012-04-11 20:16:28 +02:00
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/// Each TargetRegisterClass has a per register weight, and weight
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/// limit which must be less than the limits of its pressure sets.
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struct RegClassWeight {
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2012-04-17 03:22:58 +02:00
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unsigned RegWeight;
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2012-04-11 20:16:28 +02:00
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unsigned WeightLimit;
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};
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2008-02-10 19:45:23 +01:00
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/// TargetRegisterInfo base class - We assume that the target defines a static
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/// array of TargetRegisterDesc objects that represent all of the machine
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/// registers that the target has. As such, we simply have to track a pointer
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/// to this array so that we can turn register number into a register
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/// descriptor.
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2002-10-26 01:00:40 +02:00
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///
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2011-06-24 03:44:41 +02:00
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class TargetRegisterInfo : public MCRegisterInfo {
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2002-12-17 05:20:39 +01:00
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public:
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typedef const TargetRegisterClass * const * regclass_iterator;
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private:
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2011-06-24 03:44:41 +02:00
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const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
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2010-05-25 21:49:38 +02:00
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const char *const *SubRegIndexNames; // Names of subreg indexes.
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2012-09-11 18:34:08 +02:00
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// Pointer to array of lane masks, one per sub-reg index.
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const unsigned *SubRegIndexLaneMasks;
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2002-12-17 05:20:39 +01:00
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regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
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2009-11-12 22:00:03 +01:00
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2002-10-26 01:00:40 +02:00
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protected:
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2011-06-24 03:44:41 +02:00
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TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
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2008-02-10 19:45:23 +01:00
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regclass_iterator RegClassBegin,
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regclass_iterator RegClassEnd,
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2012-09-11 18:34:08 +02:00
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const char *const *SRINames,
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const unsigned *SRILaneMasks);
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2008-02-10 19:45:23 +01:00
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virtual ~TargetRegisterInfo();
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2002-10-26 01:00:40 +02:00
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public:
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2011-01-10 00:20:48 +01:00
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// Register numbers can represent physical registers, virtual registers, and
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// sometimes stack slots. The unsigned values are divided into these ranges:
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//
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// 0 Not a register, can be used as a sentinel.
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// [1;2^30) Physical registers assigned by TableGen.
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// [2^30;2^31) Stack slots. (Rarely used.)
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// [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
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//
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// Further sentinels can be allocated from the small negative integers.
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// DenseMapInfo<unsigned> uses -1u and -2u.
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2002-10-26 01:00:40 +02:00
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2011-01-09 22:17:37 +01:00
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/// isStackSlot - Sometimes it is useful the be able to store a non-negative
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/// frame index in a variable that normally holds a register. isStackSlot()
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/// returns true if Reg is in the range used for stack slots.
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///
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2011-01-09 23:42:48 +01:00
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/// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
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/// slots, so if a variable may contains a stack slot, always check
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/// isStackSlot() first.
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2011-01-09 22:17:37 +01:00
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///
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static bool isStackSlot(unsigned Reg) {
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2011-01-09 23:42:48 +01:00
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return int(Reg) >= (1 << 30);
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2011-01-09 22:17:37 +01:00
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}
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/// stackSlot2Index - Compute the frame index from a register value
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/// representing a stack slot.
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static int stackSlot2Index(unsigned Reg) {
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assert(isStackSlot(Reg) && "Not a stack slot");
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2011-01-09 23:42:48 +01:00
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return int(Reg - (1u << 30));
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2011-01-09 22:17:37 +01:00
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}
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/// index2StackSlot - Convert a non-negative frame index to a stack slot
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/// register value.
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static unsigned index2StackSlot(int FI) {
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assert(FI >= 0 && "Cannot hold a negative frame index.");
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2011-01-09 23:42:48 +01:00
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|
|
return FI + (1u << 30);
|
2011-01-09 22:17:37 +01:00
|
|
|
}
|
|
|
|
|
2004-01-31 20:57:11 +01:00
|
|
|
/// isPhysicalRegister - Return true if the specified register number is in
|
|
|
|
/// the physical register namespace.
|
|
|
|
static bool isPhysicalRegister(unsigned Reg) {
|
2011-01-09 23:42:48 +01:00
|
|
|
assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
|
|
|
|
return int(Reg) > 0;
|
2004-01-31 20:57:11 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/// isVirtualRegister - Return true if the specified register number is in
|
|
|
|
/// the virtual register namespace.
|
|
|
|
static bool isVirtualRegister(unsigned Reg) {
|
2011-01-09 23:42:48 +01:00
|
|
|
assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
|
|
|
|
return int(Reg) < 0;
|
2004-01-31 20:57:11 +01:00
|
|
|
}
|
|
|
|
|
2011-01-09 00:11:07 +01:00
|
|
|
/// virtReg2Index - Convert a virtual register number to a 0-based index.
|
|
|
|
/// The first virtual register in a function will get the index 0.
|
|
|
|
static unsigned virtReg2Index(unsigned Reg) {
|
2011-01-09 23:42:48 +01:00
|
|
|
assert(isVirtualRegister(Reg) && "Not a virtual register");
|
2011-05-24 05:20:56 +02:00
|
|
|
return Reg & ~(1u << 31);
|
2011-01-09 00:11:07 +01:00
|
|
|
}
|
|
|
|
|
2011-01-09 00:10:57 +01:00
|
|
|
/// index2VirtReg - Convert a 0-based index to a virtual register number.
|
|
|
|
/// This is the inverse operation of VirtReg2IndexFunctor below.
|
|
|
|
static unsigned index2VirtReg(unsigned Index) {
|
2011-05-24 05:20:56 +02:00
|
|
|
return Index | (1u << 31);
|
2011-01-09 00:10:57 +01:00
|
|
|
}
|
|
|
|
|
2010-06-02 14:39:06 +02:00
|
|
|
/// getMinimalPhysRegClass - Returns the Register Class of a physical
|
2010-07-06 17:31:55 +02:00
|
|
|
/// register of the given type, picking the most sub register class of
|
|
|
|
/// the right type that contains this physreg.
|
2010-06-29 16:02:34 +02:00
|
|
|
const TargetRegisterClass *
|
|
|
|
getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
|
2010-06-02 14:39:06 +02:00
|
|
|
|
2012-05-03 03:14:37 +02:00
|
|
|
/// getAllocatableClass - Return the maximal subclass of the given register
|
|
|
|
/// class that is alloctable, or NULL.
|
|
|
|
const TargetRegisterClass *
|
|
|
|
getAllocatableClass(const TargetRegisterClass *RC) const;
|
|
|
|
|
2004-08-27 00:21:04 +02:00
|
|
|
/// getAllocatableSet - Returns a bitset indexed by register number
|
2007-04-17 22:23:34 +02:00
|
|
|
/// indicating if a register is allocatable or not. If a register class is
|
|
|
|
/// specified, returns the subset for the class.
|
2009-10-10 00:09:05 +02:00
|
|
|
BitVector getAllocatableSet(const MachineFunction &MF,
|
2007-04-17 22:23:34 +02:00
|
|
|
const TargetRegisterClass *RC = NULL) const;
|
2004-08-27 00:21:04 +02:00
|
|
|
|
2011-04-20 20:19:48 +02:00
|
|
|
/// getCostPerUse - Return the additional cost of using this register instead
|
|
|
|
/// of other registers in its class.
|
|
|
|
unsigned getCostPerUse(unsigned RegNo) const {
|
2011-06-24 03:44:41 +02:00
|
|
|
return InfoDesc[RegNo].CostPerUse;
|
2011-04-20 20:19:48 +02:00
|
|
|
}
|
|
|
|
|
2011-06-24 03:44:41 +02:00
|
|
|
/// isInAllocatableClass - Return true if the register is in the allocation
|
|
|
|
/// of any register class.
|
|
|
|
bool isInAllocatableClass(unsigned RegNo) const {
|
|
|
|
return InfoDesc[RegNo].inAllocatableClass;
|
2004-02-01 18:14:20 +01:00
|
|
|
}
|
|
|
|
|
2010-05-25 21:49:38 +02:00
|
|
|
/// getSubRegIndexName - Return the human-readable symbolic target-specific
|
|
|
|
/// name for the specified SubRegIndex.
|
|
|
|
const char *getSubRegIndexName(unsigned SubIdx) const {
|
2012-09-11 18:34:02 +02:00
|
|
|
assert(SubIdx && SubIdx < getNumSubRegIndices() &&
|
|
|
|
"This is not a subregister index");
|
2010-05-25 21:49:38 +02:00
|
|
|
return SubRegIndexNames[SubIdx-1];
|
|
|
|
}
|
|
|
|
|
2012-09-11 18:34:08 +02:00
|
|
|
/// getSubRegIndexLaneMask - Return a bitmask representing the parts of a
|
|
|
|
/// register that are covered by SubIdx.
|
|
|
|
///
|
|
|
|
/// Lane masks for sub-register indices are similar to register units for
|
|
|
|
/// physical registers. The individual bits in a lane mask can't be assigned
|
|
|
|
/// any specific meaning. They can be used to check if two sub-register
|
|
|
|
/// indices overlap.
|
|
|
|
///
|
|
|
|
/// If the target has a register such that:
|
|
|
|
///
|
|
|
|
/// getSubReg(Reg, A) overlaps getSubReg(Reg, B)
|
|
|
|
///
|
|
|
|
/// then:
|
|
|
|
///
|
|
|
|
/// getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B) != 0
|
|
|
|
///
|
|
|
|
/// The converse is not necessarily true. If two lane masks have a common
|
|
|
|
/// bit, the corresponding sub-registers may not overlap, but it can be
|
|
|
|
/// assumed that they usually will.
|
|
|
|
unsigned getSubRegIndexLaneMask(unsigned SubIdx) const {
|
|
|
|
// SubIdx == 0 is allowed, it has the lane mask ~0u.
|
|
|
|
assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
|
|
|
|
return SubRegIndexLaneMasks[SubIdx];
|
|
|
|
}
|
|
|
|
|
2009-09-03 04:52:02 +02:00
|
|
|
/// regsOverlap - Returns true if the two registers are equal or alias each
|
|
|
|
/// other. The registers may be virtual register.
|
|
|
|
bool regsOverlap(unsigned regA, unsigned regB) const {
|
2011-06-15 08:53:50 +02:00
|
|
|
if (regA == regB) return true;
|
2009-09-03 04:52:02 +02:00
|
|
|
if (isVirtualRegister(regA) || isVirtualRegister(regB))
|
|
|
|
return false;
|
2012-05-30 01:40:02 +02:00
|
|
|
|
|
|
|
// Regunits are numerically ordered. Find a common unit.
|
|
|
|
MCRegUnitIterator RUA(regA, this);
|
|
|
|
MCRegUnitIterator RUB(regB, this);
|
|
|
|
do {
|
|
|
|
if (*RUA == *RUB) return true;
|
|
|
|
if (*RUA < *RUB) ++RUA;
|
|
|
|
else ++RUB;
|
|
|
|
} while (RUA.isValid() && RUB.isValid());
|
2004-02-19 02:10:55 +01:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-08-02 16:45:53 +02:00
|
|
|
/// hasRegUnit - Returns true if Reg contains RegUnit.
|
|
|
|
bool hasRegUnit(unsigned Reg, unsigned RegUnit) const {
|
|
|
|
for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units)
|
|
|
|
if (*Units == RegUnit)
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2007-01-02 22:30:17 +01:00
|
|
|
/// getCalleeSavedRegs - Return a null-terminated list of all of the
|
|
|
|
/// callee saved registers on this target. The register should be in the
|
2006-09-28 02:07:19 +02:00
|
|
|
/// order of desired callee-save stack frame offset. The first register is
|
2012-01-14 02:45:25 +01:00
|
|
|
/// closest to the incoming stack pointer if stack grows down, and vice versa.
|
|
|
|
///
|
2012-11-29 03:39:28 +01:00
|
|
|
virtual const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF = 0)
|
2007-07-14 16:06:15 +02:00
|
|
|
const = 0;
|
2002-12-17 05:20:39 +01:00
|
|
|
|
2012-01-14 02:45:25 +01:00
|
|
|
/// getCallPreservedMask - Return a mask of call-preserved registers for the
|
|
|
|
/// given calling convention on the current sub-target. The mask should
|
|
|
|
/// include all call-preserved aliases. This is used by the register
|
|
|
|
/// allocator to determine which registers can be live across a call.
|
|
|
|
///
|
|
|
|
/// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
|
|
|
|
/// A set bit indicates that all bits of the corresponding register are
|
|
|
|
/// preserved across the function call. The bit mask is expected to be
|
|
|
|
/// sub-register complete, i.e. if A is preserved, so are all its
|
|
|
|
/// sub-registers.
|
|
|
|
///
|
|
|
|
/// Bits are numbered from the LSB, so the bit for physical register Reg can
|
|
|
|
/// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
|
2012-02-03 00:52:57 +01:00
|
|
|
///
|
|
|
|
/// A NULL pointer means that no register mask will be used, and call
|
|
|
|
/// instructions should use implicit-def operands to indicate call clobbered
|
|
|
|
/// registers.
|
2012-01-14 02:45:25 +01:00
|
|
|
///
|
|
|
|
virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const {
|
|
|
|
// The default mask clobbers everything. All targets should override.
|
|
|
|
return 0;
|
|
|
|
}
|
2002-12-17 05:20:39 +01:00
|
|
|
|
2007-02-19 22:49:54 +01:00
|
|
|
/// getReservedRegs - Returns a bitset indexed by physical register number
|
2007-10-10 07:45:59 +02:00
|
|
|
/// indicating if a register is a special register that has particular uses
|
|
|
|
/// and should be considered unavailable at all times, e.g. SP, RA. This is
|
|
|
|
/// used by register scavenger to determine what registers are free.
|
2007-02-19 22:49:54 +01:00
|
|
|
virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
|
|
|
|
|
2009-04-28 20:29:27 +02:00
|
|
|
/// getMatchingSuperReg - Return a super-register of the specified register
|
|
|
|
/// Reg so its sub-register of index SubIdx is Reg.
|
2009-10-01 22:45:06 +02:00
|
|
|
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
|
2009-04-28 20:29:27 +02:00
|
|
|
const TargetRegisterClass *RC) const {
|
2012-03-05 20:33:24 +01:00
|
|
|
return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
|
2009-04-28 20:29:27 +02:00
|
|
|
}
|
|
|
|
|
2009-07-18 04:10:10 +02:00
|
|
|
/// getMatchingSuperRegClass - Return a subclass of the specified register
|
|
|
|
/// class A so that each register in it has a sub-register of the
|
|
|
|
/// specified sub-register index which is in the specified register class B.
|
2011-12-19 17:53:34 +01:00
|
|
|
///
|
|
|
|
/// TableGen will synthesize missing A sub-classes.
|
2009-07-18 04:10:10 +02:00
|
|
|
virtual const TargetRegisterClass *
|
|
|
|
getMatchingSuperRegClass(const TargetRegisterClass *A,
|
2012-05-04 00:49:04 +02:00
|
|
|
const TargetRegisterClass *B, unsigned Idx) const;
|
2009-07-18 04:10:10 +02:00
|
|
|
|
2011-10-05 02:35:49 +02:00
|
|
|
/// getSubClassWithSubReg - Returns the largest legal sub-class of RC that
|
|
|
|
/// supports the sub-register index Idx.
|
|
|
|
/// If no such sub-class exists, return NULL.
|
|
|
|
/// If all registers in RC already have an Idx sub-register, return RC.
|
|
|
|
///
|
|
|
|
/// TableGen generates a version of this function that is good enough in most
|
|
|
|
/// cases. Targets can override if they have constraints that TableGen
|
|
|
|
/// doesn't understand. For example, the x86 sub_8bit sub-register index is
|
|
|
|
/// supported by the full GR32 register class in 64-bit mode, but only by the
|
|
|
|
/// GR32_ABCD regiister class in 32-bit mode.
|
|
|
|
///
|
2011-12-19 17:53:34 +01:00
|
|
|
/// TableGen will synthesize missing RC sub-classes.
|
2011-10-05 02:35:49 +02:00
|
|
|
virtual const TargetRegisterClass *
|
2012-05-03 18:26:20 +02:00
|
|
|
getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
|
|
|
|
assert(Idx == 0 && "Target has no sub-registers");
|
|
|
|
return RC;
|
|
|
|
}
|
2011-10-05 02:35:49 +02:00
|
|
|
|
2010-05-28 20:18:53 +02:00
|
|
|
/// composeSubRegIndices - Return the subregister index you get from composing
|
|
|
|
/// two subregister indices.
|
|
|
|
///
|
2012-11-01 01:32:10 +01:00
|
|
|
/// The special null sub-register index composes as the identity.
|
|
|
|
///
|
2010-05-28 20:18:53 +02:00
|
|
|
/// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
|
|
|
|
/// returns c. Note that composeSubRegIndices does not tell you about illegal
|
|
|
|
/// compositions. If R does not have a subreg a, or R:a does not have a subreg
|
|
|
|
/// b, composeSubRegIndices doesn't tell you.
|
|
|
|
///
|
|
|
|
/// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
|
|
|
|
/// ssub_0:S0 - ssub_3:S3 subregs.
|
|
|
|
/// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
|
|
|
|
///
|
2012-11-01 01:32:10 +01:00
|
|
|
unsigned composeSubRegIndices(unsigned a, unsigned b) const {
|
|
|
|
if (!a) return b;
|
|
|
|
if (!b) return a;
|
|
|
|
return composeSubRegIndicesImpl(a, b);
|
2010-05-28 20:18:53 +02:00
|
|
|
}
|
|
|
|
|
2012-11-01 01:32:10 +01:00
|
|
|
protected:
|
|
|
|
/// Overridden by TableGen in targets that have sub-registers.
|
|
|
|
virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
|
|
|
|
llvm_unreachable("Target has no sub-registers");
|
|
|
|
}
|
|
|
|
|
|
|
|
public:
|
2012-05-07 21:14:58 +02:00
|
|
|
/// getCommonSuperRegClass - Find a common super-register class if it exists.
|
|
|
|
///
|
|
|
|
/// Find a register class, SuperRC and two sub-register indices, PreA and
|
|
|
|
/// PreB, such that:
|
|
|
|
///
|
|
|
|
/// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
|
|
|
|
///
|
|
|
|
/// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
|
|
|
|
///
|
|
|
|
/// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
|
|
|
|
///
|
|
|
|
/// SuperRC will be chosen such that no super-class of SuperRC satisfies the
|
|
|
|
/// requirements, and there is no register class with a smaller spill size
|
|
|
|
/// that satisfies the requirements.
|
|
|
|
///
|
|
|
|
/// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
|
|
|
|
///
|
|
|
|
/// Either of the PreA and PreB sub-register indices may be returned as 0. In
|
|
|
|
/// that case, the returned register class will be a sub-class of the
|
|
|
|
/// corresponding argument register class.
|
|
|
|
///
|
|
|
|
/// The function returns NULL if no register class can be found.
|
|
|
|
///
|
|
|
|
const TargetRegisterClass*
|
|
|
|
getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
|
|
|
|
const TargetRegisterClass *RCB, unsigned SubB,
|
|
|
|
unsigned &PreA, unsigned &PreB) const;
|
|
|
|
|
2002-12-17 05:20:39 +01:00
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
// Register Class Information
|
|
|
|
//
|
|
|
|
|
|
|
|
/// Register class iterators
|
2003-07-30 07:29:45 +02:00
|
|
|
///
|
2002-12-17 05:20:39 +01:00
|
|
|
regclass_iterator regclass_begin() const { return RegClassBegin; }
|
|
|
|
regclass_iterator regclass_end() const { return RegClassEnd; }
|
|
|
|
|
|
|
|
unsigned getNumRegClasses() const {
|
2008-05-05 20:30:58 +02:00
|
|
|
return (unsigned)(regclass_end()-regclass_begin());
|
2002-12-17 05:20:39 +01:00
|
|
|
}
|
2009-10-01 22:45:06 +02:00
|
|
|
|
2006-07-21 22:57:35 +02:00
|
|
|
/// getRegClass - Returns the register class associated with the enumeration
|
2011-06-28 21:10:37 +02:00
|
|
|
/// value. See class MCOperandInfo.
|
2006-07-21 22:57:35 +02:00
|
|
|
const TargetRegisterClass *getRegClass(unsigned i) const {
|
2010-06-18 20:13:55 +02:00
|
|
|
assert(i < getNumRegClasses() && "Register Class ID out of range");
|
|
|
|
return RegClassBegin[i];
|
2006-07-21 22:57:35 +02:00
|
|
|
}
|
2002-12-17 05:20:39 +01:00
|
|
|
|
2011-10-01 00:18:51 +02:00
|
|
|
/// getCommonSubClass - find the largest common subclass of A and B. Return
|
|
|
|
/// NULL if there is no common subclass.
|
|
|
|
const TargetRegisterClass *
|
|
|
|
getCommonSubClass(const TargetRegisterClass *A,
|
|
|
|
const TargetRegisterClass *B) const;
|
|
|
|
|
2009-02-06 18:43:24 +01:00
|
|
|
/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
|
2009-07-29 22:31:52 +02:00
|
|
|
/// values. If a target supports multiple different pointer register classes,
|
|
|
|
/// kind specifies which one is indicated.
|
2012-05-08 00:10:26 +02:00
|
|
|
virtual const TargetRegisterClass *
|
|
|
|
getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
|
2012-02-05 23:14:15 +01:00
|
|
|
llvm_unreachable("Target didn't implement getPointerRegClass!");
|
2009-02-06 18:43:24 +01:00
|
|
|
}
|
2002-12-17 05:20:39 +01:00
|
|
|
|
2007-09-26 23:31:07 +02:00
|
|
|
/// getCrossCopyRegClass - Returns a legal register class to copy a register
|
2011-03-10 01:16:32 +01:00
|
|
|
/// in the specified class to or from. If it is possible to copy the register
|
|
|
|
/// directly without using a cross register class copy, return the specified
|
|
|
|
/// RC. Returns NULL if it is not possible to copy between a two registers of
|
|
|
|
/// the specified class.
|
2007-09-26 23:31:07 +02:00
|
|
|
virtual const TargetRegisterClass *
|
|
|
|
getCrossCopyRegClass(const TargetRegisterClass *RC) const {
|
2011-03-10 01:16:32 +01:00
|
|
|
return RC;
|
2007-09-26 23:31:07 +02:00
|
|
|
}
|
|
|
|
|
2011-04-26 20:52:33 +02:00
|
|
|
/// getLargestLegalSuperClass - Returns the largest super class of RC that is
|
|
|
|
/// legal to use in the current sub-target and has the same spill size.
|
|
|
|
/// The returned register class can be used to create virtual registers which
|
|
|
|
/// means that all its registers can be copied and spilled.
|
|
|
|
virtual const TargetRegisterClass*
|
|
|
|
getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
|
|
|
|
/// The default implementation is very conservative and doesn't allow the
|
|
|
|
/// register allocator to inflate register classes.
|
|
|
|
return RC;
|
|
|
|
}
|
|
|
|
|
2011-03-07 22:56:36 +01:00
|
|
|
/// getRegPressureLimit - Return the register pressure "high water mark" for
|
|
|
|
/// the specific register class. The scheduler is in high register pressure
|
|
|
|
/// mode (for the specific register class) if it goes over the limit.
|
2012-04-10 04:25:26 +02:00
|
|
|
///
|
|
|
|
/// Note: this is the old register pressure model that relies on a manually
|
|
|
|
/// specified representative register class per value type.
|
2011-03-07 22:56:36 +01:00
|
|
|
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
|
|
|
|
MachineFunction &MF) const {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-12-05 07:47:06 +01:00
|
|
|
/// Get the weight in units of pressure for this register class.
|
2012-04-11 20:16:28 +02:00
|
|
|
virtual const RegClassWeight &getRegClassWeight(
|
|
|
|
const TargetRegisterClass *RC) const = 0;
|
2012-04-10 04:25:26 +02:00
|
|
|
|
2012-12-05 07:47:12 +01:00
|
|
|
/// Get the weight in units of pressure for this register unit.
|
|
|
|
virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
|
|
|
|
|
2012-04-10 04:25:26 +02:00
|
|
|
/// Get the number of dimensions of register pressure.
|
|
|
|
virtual unsigned getNumRegPressureSets() const = 0;
|
|
|
|
|
2012-04-20 22:45:00 +02:00
|
|
|
/// Get the name of this register unit pressure set.
|
|
|
|
virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
|
|
|
|
|
2012-04-10 04:25:26 +02:00
|
|
|
/// Get the register unit pressure limit for this dimension.
|
|
|
|
/// This limit must be adjusted dynamically for reserved registers.
|
|
|
|
virtual unsigned getRegPressureSetLimit(unsigned Idx) const = 0;
|
|
|
|
|
|
|
|
/// Get the dimensions of register pressure impacted by this register class.
|
|
|
|
/// Returns a -1 terminated array of pressure set IDs.
|
|
|
|
virtual const int *getRegClassPressureSets(
|
|
|
|
const TargetRegisterClass *RC) const = 0;
|
|
|
|
|
2012-12-05 07:47:12 +01:00
|
|
|
/// Get the dimensions of register pressure impacted by this register unit.
|
|
|
|
/// Returns a -1 terminated array of pressure set IDs.
|
|
|
|
virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
|
|
|
|
|
2012-12-03 22:17:00 +01:00
|
|
|
/// Get a list of 'hint' registers that the register allocator should try
|
|
|
|
/// first when allocating a physical register for the virtual register
|
|
|
|
/// VirtReg. These registers are effectively moved to the front of the
|
|
|
|
/// allocation order.
|
|
|
|
///
|
|
|
|
/// The Order argument is the allocation order for VirtReg's register class
|
|
|
|
/// as returned from RegisterClassInfo::getOrder(). The hint registers must
|
|
|
|
/// come from Order, and they must not be reserved.
|
|
|
|
///
|
|
|
|
/// The default implementation of this function can resolve
|
|
|
|
/// target-independent hints provided to MRI::setRegAllocationHint with
|
|
|
|
/// HintType == 0. Targets that override this function should defer to the
|
|
|
|
/// default implementation if they have no reason to change the allocation
|
|
|
|
/// order for VirtReg. There may be target-independent hints.
|
|
|
|
virtual void getRegAllocationHints(unsigned VirtReg,
|
|
|
|
ArrayRef<MCPhysReg> Order,
|
|
|
|
SmallVectorImpl<MCPhysReg> &Hints,
|
|
|
|
const MachineFunction &MF,
|
|
|
|
const VirtRegMap *VRM = 0) const;
|
|
|
|
|
2011-04-19 20:11:45 +02:00
|
|
|
/// avoidWriteAfterWrite - Return true if the register allocator should avoid
|
|
|
|
/// writing a register from RC in two consecutive instructions.
|
|
|
|
/// This can avoid pipeline stalls on certain architectures.
|
|
|
|
/// It does cause increased register pressure, though.
|
|
|
|
virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2009-06-18 04:04:01 +02:00
|
|
|
/// UpdateRegAllocHint - A callback to allow target a chance to update
|
|
|
|
/// register allocation hints when a register is "changed" (e.g. coalesced)
|
|
|
|
/// to another register. e.g. On ARM, some virtual registers should target
|
|
|
|
/// register pairs, if one of pair is coalesced to another register, the
|
|
|
|
/// allocation hint of the other half of the pair should be changed to point
|
|
|
|
/// to the new register.
|
|
|
|
virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
|
|
|
|
MachineFunction &MF) const {
|
|
|
|
// Do nothing.
|
|
|
|
}
|
|
|
|
|
2007-10-10 07:45:59 +02:00
|
|
|
/// requiresRegisterScavenging - returns true if the target requires (and can
|
|
|
|
/// make use of) the register scavenger.
|
2007-02-28 01:59:19 +01:00
|
|
|
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
|
2007-02-28 01:17:36 +01:00
|
|
|
return false;
|
|
|
|
}
|
2009-10-01 22:45:06 +02:00
|
|
|
|
2011-03-03 21:01:52 +01:00
|
|
|
/// useFPForScavengingIndex - returns true if the target wants to use
|
|
|
|
/// frame pointer based accesses to spill to the scavenger emergency spill
|
|
|
|
/// slot.
|
|
|
|
virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2009-10-08 03:46:59 +02:00
|
|
|
/// requiresFrameIndexScavenging - returns true if the target requires post
|
|
|
|
/// PEI scavenging of registers for materializing frame index constants.
|
|
|
|
virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2010-08-24 21:05:43 +02:00
|
|
|
/// requiresVirtualBaseRegisters - Returns true if the target wants the
|
|
|
|
/// LocalStackAllocation pass to be run and virtual base registers
|
|
|
|
/// used for more efficient stack access.
|
|
|
|
virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2009-07-09 08:53:48 +02:00
|
|
|
/// hasReservedSpillSlot - Return true if target has reserved a spill slot in
|
|
|
|
/// the stack frame of the given function for the specified register. e.g. On
|
|
|
|
/// x86, if the frame register is required, the first fixed stack object is
|
|
|
|
/// reserved as its spill slot. This tells PEI not to create a new stack frame
|
|
|
|
/// object for the given register. It should be called only after
|
|
|
|
/// processFunctionBeforeCalleeSavedScan().
|
2010-07-20 08:52:21 +02:00
|
|
|
virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
|
2009-07-09 08:53:48 +02:00
|
|
|
int &FrameIdx) const {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-04-23 23:39:35 +02:00
|
|
|
/// trackLivenessAfterRegAlloc - returns true if the live-ins should be tracked
|
|
|
|
/// after register allocation.
|
|
|
|
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2009-07-09 08:53:48 +02:00
|
|
|
/// needsStackRealignment - true if storage within the function requires the
|
|
|
|
/// stack pointer to be aligned more than the normal calling convention calls
|
|
|
|
/// for.
|
2008-06-26 03:51:13 +02:00
|
|
|
virtual bool needsStackRealignment(const MachineFunction &MF) const {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2010-08-20 01:52:25 +02:00
|
|
|
/// getFrameIndexInstrOffset - Get the offset from the referenced frame
|
2011-02-02 01:46:09 +01:00
|
|
|
/// index in the instruction, if there is one.
|
2010-08-26 23:56:30 +02:00
|
|
|
virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
|
|
|
|
int Idx) const {
|
2010-08-20 01:52:25 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-08-17 20:13:53 +02:00
|
|
|
/// needsFrameBaseReg - Returns true if the instruction's frame index
|
|
|
|
/// reference would be better served by a base register other than FP
|
|
|
|
/// or SP. Used by LocalStackFrameAllocation to determine which frame index
|
|
|
|
/// references it should create new base registers for.
|
2010-08-24 23:19:33 +02:00
|
|
|
virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
|
2010-08-17 20:13:53 +02:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2010-08-18 00:41:55 +02:00
|
|
|
/// materializeFrameBaseRegister - Insert defining instruction(s) for
|
|
|
|
/// BaseReg to be a pointer to FrameIdx before insertion point I.
|
2010-12-18 00:09:14 +01:00
|
|
|
virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
|
2010-08-20 01:52:25 +02:00
|
|
|
unsigned BaseReg, int FrameIdx,
|
|
|
|
int64_t Offset) const {
|
2012-02-05 23:14:15 +01:00
|
|
|
llvm_unreachable("materializeFrameBaseRegister does not exist on this "
|
|
|
|
"target");
|
2010-08-18 00:41:55 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/// resolveFrameIndex - Resolve a frame index operand of an instruction
|
|
|
|
/// to reference the indicated base register plus offset instead.
|
|
|
|
virtual void resolveFrameIndex(MachineBasicBlock::iterator I,
|
|
|
|
unsigned BaseReg, int64_t Offset) const {
|
2012-02-05 23:14:15 +01:00
|
|
|
llvm_unreachable("resolveFrameIndex does not exist on this target");
|
2010-08-18 00:41:55 +02:00
|
|
|
}
|
|
|
|
|
2010-08-20 01:52:25 +02:00
|
|
|
/// isFrameOffsetLegal - Determine whether a given offset immediate is
|
|
|
|
/// encodable to resolve a frame index.
|
|
|
|
virtual bool isFrameOffsetLegal(const MachineInstr *MI,
|
|
|
|
int64_t Offset) const {
|
2012-02-05 23:14:15 +01:00
|
|
|
llvm_unreachable("isFrameOffsetLegal does not exist on this target");
|
2010-08-18 19:57:37 +02:00
|
|
|
}
|
2010-08-18 00:41:55 +02:00
|
|
|
|
2002-12-28 21:10:23 +01:00
|
|
|
|
2009-10-20 00:27:30 +02:00
|
|
|
/// saveScavengerRegister - Spill the register so it can be used by the
|
|
|
|
/// register scavenger. Return true if the register was spilled, false
|
|
|
|
/// otherwise. If this function does not spill the register, the scavenger
|
2009-10-06 00:30:23 +02:00
|
|
|
/// will instead spill it to the emergency spill slot.
|
|
|
|
///
|
|
|
|
virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator I,
|
2009-10-20 00:27:30 +02:00
|
|
|
MachineBasicBlock::iterator &UseMI,
|
2009-10-06 00:30:23 +02:00
|
|
|
const TargetRegisterClass *RC,
|
2009-11-21 03:32:35 +01:00
|
|
|
unsigned Reg) const {
|
|
|
|
return false;
|
|
|
|
}
|
2009-10-06 00:30:23 +02:00
|
|
|
|
2002-12-28 21:10:23 +01:00
|
|
|
/// eliminateFrameIndex - This method must be overriden to eliminate abstract
|
|
|
|
/// frame indices from instructions which may use them. The instruction
|
|
|
|
/// referenced by the iterator contains an MO_FrameIndex operand which must be
|
|
|
|
/// eliminated by this method. This method may modify or replace the
|
2010-01-13 02:39:38 +01:00
|
|
|
/// specified instruction, as long as it keeps the iterator pointing at the
|
2013-01-31 21:02:54 +01:00
|
|
|
/// finished product. SPAdj is the SP adjustment due to call frame setup
|
|
|
|
/// instruction. FIOperandNum is the FI operand number.
|
2010-08-27 01:32:16 +02:00
|
|
|
virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
|
2013-01-31 21:02:54 +01:00
|
|
|
int SPAdj, unsigned FIOperandNum,
|
|
|
|
RegScavenger *RS = NULL) const = 0;
|
2002-12-28 21:10:23 +01:00
|
|
|
|
2006-03-28 15:48:33 +02:00
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
/// Debug information queries.
|
2009-10-01 22:45:06 +02:00
|
|
|
|
2006-03-28 15:48:33 +02:00
|
|
|
/// getFrameRegister - This method should return the register used as a base
|
2006-04-07 18:34:46 +02:00
|
|
|
/// for values allocated in the current stack frame.
|
2009-11-12 22:00:03 +01:00
|
|
|
virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
|
2008-01-31 04:37:28 +01:00
|
|
|
|
2011-07-01 01:20:32 +02:00
|
|
|
/// getCompactUnwindRegNum - This function maps the register to the number for
|
|
|
|
/// compact unwind encoding. Return -1 if the register isn't valid.
|
2011-07-06 22:33:48 +02:00
|
|
|
virtual int getCompactUnwindRegNum(unsigned, bool) const {
|
2011-07-01 01:20:32 +02:00
|
|
|
return -1;
|
|
|
|
}
|
2002-10-26 01:00:40 +02:00
|
|
|
};
|
|
|
|
|
2009-05-03 20:32:42 +02:00
|
|
|
|
2012-05-04 03:48:29 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SuperRegClassIterator
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// Iterate over the possible super-registers for a given register class. The
|
|
|
|
// iterator will visit a list of pairs (Idx, Mask) corresponding to the
|
|
|
|
// possible classes of super-registers.
|
|
|
|
//
|
|
|
|
// Each bit mask will have at least one set bit, and each set bit in Mask
|
|
|
|
// corresponds to a SuperRC such that:
|
|
|
|
//
|
|
|
|
// For all Reg in SuperRC: Reg:Idx is in RC.
|
|
|
|
//
|
|
|
|
// The iterator can include (O, RC->getSubClassMask()) as the first entry which
|
|
|
|
// also satisfies the above requirement, assuming Reg:0 == Reg.
|
|
|
|
//
|
|
|
|
class SuperRegClassIterator {
|
|
|
|
const unsigned RCMaskWords;
|
|
|
|
unsigned SubReg;
|
|
|
|
const uint16_t *Idx;
|
|
|
|
const uint32_t *Mask;
|
|
|
|
|
|
|
|
public:
|
|
|
|
/// Create a SuperRegClassIterator that visits all the super-register classes
|
|
|
|
/// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
|
|
|
|
SuperRegClassIterator(const TargetRegisterClass *RC,
|
|
|
|
const TargetRegisterInfo *TRI,
|
|
|
|
bool IncludeSelf = false)
|
|
|
|
: RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
|
|
|
|
SubReg(0),
|
|
|
|
Idx(RC->getSuperRegIndices()),
|
|
|
|
Mask(RC->getSubClassMask()) {
|
|
|
|
if (!IncludeSelf)
|
|
|
|
++*this;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Returns true if this iterator is still pointing at a valid entry.
|
|
|
|
bool isValid() const { return Idx; }
|
|
|
|
|
|
|
|
/// Returns the current sub-register index.
|
|
|
|
unsigned getSubReg() const { return SubReg; }
|
|
|
|
|
|
|
|
/// Returns the bit mask if register classes that getSubReg() projects into
|
|
|
|
/// RC.
|
|
|
|
const uint32_t *getMask() const { return Mask; }
|
|
|
|
|
|
|
|
/// Advance iterator to the next entry.
|
|
|
|
void operator++() {
|
|
|
|
assert(isValid() && "Cannot move iterator past end.");
|
|
|
|
Mask += RCMaskWords;
|
|
|
|
SubReg = *Idx++;
|
|
|
|
if (!SubReg)
|
|
|
|
Idx = 0;
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2007-02-01 06:32:05 +01:00
|
|
|
// This is useful when building IndexedMaps keyed on virtual registers
|
2009-09-06 10:55:57 +02:00
|
|
|
struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
|
2004-02-25 22:55:45 +01:00
|
|
|
unsigned operator()(unsigned Reg) const {
|
2011-01-09 00:11:07 +01:00
|
|
|
return TargetRegisterInfo::virtReg2Index(Reg);
|
2004-02-25 22:55:45 +01:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2011-01-09 04:05:53 +01:00
|
|
|
/// PrintReg - Helper class for printing registers on a raw_ostream.
|
|
|
|
/// Prints virtual and physical registers with or without a TRI instance.
|
|
|
|
///
|
|
|
|
/// The format is:
|
2011-01-09 20:45:45 +01:00
|
|
|
/// %noreg - NoRegister
|
|
|
|
/// %vreg5 - a virtual register.
|
|
|
|
/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
|
|
|
|
/// %EAX - a physical register
|
|
|
|
/// %physreg17 - a physical register when no TRI instance given.
|
2011-01-09 04:05:53 +01:00
|
|
|
///
|
|
|
|
/// Usage: OS << PrintReg(Reg, TRI) << '\n';
|
|
|
|
///
|
|
|
|
class PrintReg {
|
|
|
|
const TargetRegisterInfo *TRI;
|
|
|
|
unsigned Reg;
|
|
|
|
unsigned SubIdx;
|
|
|
|
public:
|
2012-11-27 09:14:24 +01:00
|
|
|
explicit PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0,
|
|
|
|
unsigned subidx = 0)
|
2011-01-09 04:05:53 +01:00
|
|
|
: TRI(tri), Reg(reg), SubIdx(subidx) {}
|
|
|
|
void print(raw_ostream&) const;
|
|
|
|
};
|
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static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
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PR.print(OS);
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|
return OS;
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|
}
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|
2012-05-31 19:18:29 +02:00
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/// PrintRegUnit - Helper class for printing register units on a raw_ostream.
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|
///
|
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|
|
/// Register units are named after their root registers:
|
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|
///
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|
/// AL - Single root.
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|
|
|
/// FP0~ST7 - Dual roots.
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|
|
|
///
|
|
|
|
/// Usage: OS << PrintRegUnit(Unit, TRI) << '\n';
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|
///
|
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|
|
class PrintRegUnit {
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|
|
const TargetRegisterInfo *TRI;
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|
|
|
unsigned Unit;
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|
|
public:
|
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|
|
PrintRegUnit(unsigned unit, const TargetRegisterInfo *tri)
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|
|
|
: TRI(tri), Unit(unit) {}
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|
|
void print(raw_ostream&) const;
|
|
|
|
};
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|
|
|
|
|
|
|
static inline raw_ostream &operator<<(raw_ostream &OS, const PrintRegUnit &PR) {
|
|
|
|
PR.print(OS);
|
|
|
|
return OS;
|
|
|
|
}
|
|
|
|
|
2003-11-11 23:41:34 +01:00
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|
|
} // End llvm namespace
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|
2002-10-26 01:00:40 +02:00
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|
|
#endif
|