Owen Anderson
b59504a1a1
Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding.
...
llvm-svn: 128965
2011-04-05 23:55:28 +00:00
Johnny Chen
48b39632aa
Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register
...
encodings for DisassembleArithMiscFrm().
rdar://problem/9238659
llvm-svn: 128958
2011-04-05 23:28:00 +00:00
Bob Wilson
89dce9ab06
Clean up some code for clarity.
...
llvm-svn: 128953
2011-04-05 23:03:25 +00:00
Owen Anderson
c8ceb7246f
Revert r128946 while I figure out why it broke the buildbots.
...
llvm-svn: 128951
2011-04-05 23:03:06 +00:00
Johnny Chen
359b9a2331
A7.3 register encoding
...
Qd -> bit[12] == 0
Qn -> bit[16] == 0
Qm -> bit[0] == 0
If one of these bits is 1, the instruction is UNDEFINED.
rdar://problem/9238399
rdar://problem/9238445
llvm-svn: 128949
2011-04-05 22:57:07 +00:00
Owen Anderson
809f1a74d1
Give RSBS and RSCS the pseudo treatment.
...
llvm-svn: 128946
2011-04-05 22:42:54 +00:00
Johnny Chen
cf11408b65
ARM disassembler was erroneously accepting an invalid RSC instruction.
...
Added checks for regs which should not be 15.
rdar://problem/9237734
llvm-svn: 128945
2011-04-05 22:18:07 +00:00
Johnny Chen
6e1367d5dd
ARM disassembler was erroneously accepting an invalid LSL instruction.
...
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.
rdar://problem/9237693
llvm-svn: 128941
2011-04-05 21:49:44 +00:00
Owen Anderson
b73d1741c6
Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions.
...
llvm-svn: 128940
2011-04-05 21:48:57 +00:00
Johnny Chen
b50ab34083
The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.
...
Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.
rdar://problem/9236873
llvm-svn: 128922
2011-04-05 20:32:23 +00:00
Johnny Chen
4a15bdc1aa
ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.
...
llvm-svn: 128913
2011-04-05 19:42:11 +00:00
Jim Grosbach
7bdaed671d
Make second source operand of LDRD pre/post explicit.
...
Finish what r128736 started.
llvm-svn: 128903
2011-04-05 18:40:13 +00:00
Johnny Chen
d37098ae32
Constants with multiple encodings (ARM):
...
An alternative syntax is available for a modified immediate constant that permits the programmer to specify
the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:
<byte> is the numeric value of abcdefgh, in the range 0-255
<rot> is twice the numeric value of rotation, an even number in the range 0-30.
llvm-svn: 128897
2011-04-05 18:02:46 +00:00
Johnny Chen
626c0a35f6
Check for invalid register encodings for UMAAL and friends where:
...
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
if dHi == dLo then UNPREDICTABLE;
rdar://problem/9230202
llvm-svn: 128895
2011-04-05 17:43:10 +00:00
Owen Anderson
b314020ff7
Convert ADCS and SBCS instructions into pseudos that are expanded to the ADC/ABC with the appropriate S-bit input value.
...
llvm-svn: 128892
2011-04-05 17:24:25 +00:00
Bill Wendling
a8db395dc1
Revamp the SjLj "dispatch setup" intrinsic.
...
It needed to be moved closer to the setjmp statement, because the code directly
after the setjmp needs to know about values that are on the stack. Also, the
'bitcast' of the function context was causing a dead load. This wouldn't be too
horrible, except that at -O0 it wasn't optimized out, and because it wasn't
using the correct base pointer (if there is a VLA), it would try to access a
value from a garbage address.
<rdar://problem/9130540>
llvm-svn: 128873
2011-04-05 01:37:43 +00:00
Eric Christopher
b04934036a
Just use BL all the time. It's safer that way.
...
Fixes rdar://9184526
llvm-svn: 128869
2011-04-05 00:39:26 +00:00
Johnny Chen
785ab1531b
Fix SRS/SRSW encoding bits.
...
rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS
Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with
http://llvm.org/viewvc/llvm-project?view=rev&revision=128859 .
llvm-svn: 128864
2011-04-05 00:16:18 +00:00
Johnny Chen
92c33bafac
A8.6.105 MUL
...
Inst{15-12} should be specified as 0b0000.
rdar://problem/9231168 ARM disassembler discrepancy: erroneously accepting MUL
llvm-svn: 128862
2011-04-04 23:57:05 +00:00
Johnny Chen
eb8e7684b9
RFE encoding should also specify the "should be" encoding bits.
...
rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE
Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while
doing regression testings.
llvm-svn: 128859
2011-04-04 23:39:08 +00:00
Joerg Sonnenberger
4033708a54
Make OpcodeMask an unsigned long long literal to deal with overflow.
...
llvm-svn: 128847
2011-04-04 21:38:17 +00:00
Johnny Chen
7fb247299a
Fix incorrect alignment for NEON VST2b32_UPD.
...
rdar://problem/9225433
llvm-svn: 128841
2011-04-04 20:35:31 +00:00
Jakob Stoklund Olesen
c4092e120d
Insert code in the right location when lowering PowerPC atomics.
...
This causes defs to dominate uses, no instructions after terminators, and other
goodness.
llvm-svn: 128836
2011-04-04 17:57:29 +00:00
Bruno Cardoso Lopes
74363376e4
- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT
...
also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
index mode to print.
- Testcases.
llvm-svn: 128832
2011-04-04 17:18:19 +00:00
Akira Hatanaka
54ae678397
Move transformation of JmpLink and related nodes done during instruction selection to Legalize phase.
...
llvm-svn: 128830
2011-04-04 17:11:07 +00:00
Jakob Stoklund Olesen
8eef3feba8
PowerPC atomic pseudos clobber CR0, they don't read it.
...
llvm-svn: 128829
2011-04-04 17:07:09 +00:00
Jakob Stoklund Olesen
de8d7a7432
Use X0 instead of R0 for the zero register on ppc64.
...
The 32-bit R0 cannot be used where a 64-bit register is expected.
llvm-svn: 128828
2011-04-04 17:07:06 +00:00
Joerg Sonnenberger
1cbd300346
Add support for the VIA PadLock instructions.
...
llvm-svn: 128826
2011-04-04 16:58:13 +00:00
Joerg Sonnenberger
2bfb3e48e7
Expand Op0Mask by one bit in preparation for the PadLock prefixes.
...
Define most shift masks incrementally to reduce the redundant
hard-coding. Introduce new shift for the VEX flags to replace the
magic constant 32 in various places.
llvm-svn: 128822
2011-04-04 15:58:30 +00:00
Jay Foad
fc232f270b
Remove some support for ReturnInsts with multiple operands, and for
...
returning a scalar value in a function whose return type is a single-
element structure or array.
llvm-svn: 128810
2011-04-04 07:44:02 +00:00
Che-Liang Chiou
c4a22b7cd5
ptx: support setp's 4-operand format
...
llvm-svn: 128767
2011-04-02 08:51:39 +00:00
Cameron Zwarich
9573b6277e
Do some peephole optimizations to remove pointless VMOVs from Neon to integer
...
registers that arise from argument shuffling with the soft float ABI. These
instructions are particularly slow on Cortex A8. This fixes one half of
<rdar://problem/8674845>.
llvm-svn: 128759
2011-04-02 02:40:43 +00:00
Johnny Chen
dcd29e054c
Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset;
...
instead of the second operand in addrmode_imm12.
rdar://problem/9225289
llvm-svn: 128757
2011-04-02 02:24:54 +00:00
Akira Hatanaka
9a001f303e
Undo changes mistakenly made in revision 128750.
...
llvm-svn: 128751
2011-04-02 00:26:12 +00:00
Akira Hatanaka
6b700f35aa
Insert space before ';' to prevent warnings.
...
llvm-svn: 128750
2011-04-02 00:15:58 +00:00
Johnny Chen
6f10cfdf01
Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.
...
rdar://problem/9224276
llvm-svn: 128749
2011-04-01 23:30:25 +00:00
Johnny Chen
b308662930
MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE.
...
rdar://problem/9224120
llvm-svn: 128748
2011-04-01 23:15:50 +00:00
Johnny Chen
845caa871c
Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that
...
all the instruction have:
let Inst{31-27} = 0b1110; // non-predicated
Before, the ARM decoder was confusing:
> 0x40 0xf3 0xb8 0x80
as:
Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcs pc, r8, r0, asr #6
since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.
Now, the AR decoder behaves correctly:
> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt
Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcshi pc, r8, r0, asr #6
>
rdar://problem/9223094
llvm-svn: 128746
2011-04-01 22:32:51 +00:00
Evan Cheng
4531994839
Avoid de-referencing pass beginning of a basic block. No small test case possible. rdar://9216009
...
llvm-svn: 128743
2011-04-01 22:09:28 +00:00
Akira Hatanaka
9f4b4d2dc1
Remove redundant code. There are assignments to variables Base and Offset right after the code that is removed.
...
llvm-svn: 128742
2011-04-01 21:56:02 +00:00
Akira Hatanaka
9257b524eb
Simplifies logic for printing target flags.
...
llvm-svn: 128741
2011-04-01 21:41:06 +00:00
Owen Anderson
48048d179c
When the architecture is explicitly armv6 or thumbv6, we need to mark the object file appropriately.
...
llvm-svn: 128739
2011-04-01 21:07:39 +00:00
Jim Grosbach
039844acc5
LDRD/STRD instructions should print both Rt and Rt2 in the asm string.
...
llvm-svn: 128736
2011-04-01 20:26:57 +00:00
Johnny Chen
65fe34ae00
Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction
...
as invalid.
llvm-svn: 128734
2011-04-01 20:21:38 +00:00
Akira Hatanaka
0b476a8e81
Modifies MipsAsmPrinter::isBlockOnlyReachableByFallthrough so that it handles delay slots correctly.
...
llvm-svn: 128724
2011-04-01 18:57:38 +00:00
Johnny Chen
17f1f7c322
Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm).
...
rdar://problem/9219356
llvm-svn: 128722
2011-04-01 18:26:38 +00:00
Akira Hatanaka
c2d74b05ca
Add code for analyzing FP branches. Clean up branch Analysis functions.
...
llvm-svn: 128718
2011-04-01 17:39:08 +00:00
Benjamin Kramer
aff6a9e50a
Initialize HasVMLxForwarding.
...
llvm-svn: 128709
2011-04-01 09:20:31 +00:00
Evan Cheng
39574b2766
Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.
...
rdar://8911343
llvm-svn: 128696
2011-04-01 00:42:02 +00:00
Matt Beaumont-Gay
2520bb8022
Remove unused variables
...
llvm-svn: 128692
2011-04-01 00:06:01 +00:00
Bruno Cardoso Lopes
d285a7f27e
Apply again changes to support ARM memory asm parsing. I removed
...
all LDR/STR changes and left them to a future patch. Passing all
checks now.
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
llvm-svn: 128689
2011-03-31 23:26:08 +00:00
Jakob Stoklund Olesen
5421130bfc
Provide a legal pointer register class when targeting thumb1.
...
The LocalStackSlotAllocation pass was creating illegal registers.
llvm-svn: 128687
2011-03-31 23:02:15 +00:00
Evan Cheng
64850406cf
Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier
...
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2
llvm-svn: 128665
2011-03-31 19:38:48 +00:00
Johnny Chen
2c5149791a
Fix single word and unsigned byte data transfer instruction encodings so that
...
Inst{4} = 0.
rdar://problem/9213022
llvm-svn: 128662
2011-03-31 19:28:35 +00:00
Akira Hatanaka
b26c89ee68
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons.
...
llvm-svn: 128650
2011-03-31 18:26:17 +00:00
Johnny Chen
0bb797b2f3
Add BLXi to the instruction table for disassembly purpose.
...
A8.6.23 BLX (immediate)
rdar://problem/9212921
llvm-svn: 128644
2011-03-31 17:53:50 +00:00
Bruno Cardoso Lopes
392dbfd384
Revert r128632 again, until I figure out what break the tests
...
llvm-svn: 128635
2011-03-31 15:54:36 +00:00
Richard Osborne
5b9df0d075
Add XCore intrinsics for initializing / starting / synchronizing threads.
...
llvm-svn: 128633
2011-03-31 15:13:13 +00:00
Bruno Cardoso Lopes
3b2f5421ac
Reapply r128585 without generating a lib depedency cycle. An updated log:
...
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
{STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
addrmode2.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
llvm-svn: 128632
2011-03-31 14:52:28 +00:00
Matt Beaumont-Gay
325e16f668
Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"
...
This revision introduced a dependency cycle, as nlewycky mentioned by email.
llvm-svn: 128597
2011-03-31 00:39:16 +00:00
Owen Anderson
d4e1a2f2b6
Somehow we managed to forget to encode the lane index for a large swathe of NEON instructions. With this fix, the entire test-suite passes with the Thumb integrated assembler.
...
llvm-svn: 128587
2011-03-30 23:45:29 +00:00
Evan Cheng
fa37c7d815
Don't try to create zero-sized stack objects.
...
llvm-svn: 128586
2011-03-30 23:44:13 +00:00
Bruno Cardoso Lopes
cebbf7fe68
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
...
{STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser
llvm-svn: 128585
2011-03-30 23:32:32 +00:00
Cameron Zwarich
1b8f91d2c8
Add a ARM-specific SD node for VBSL so that forms with a constant first operand
...
can be recognized. This fixes <rdar://problem/9183078>.
llvm-svn: 128584
2011-03-30 23:01:21 +00:00
Akira Hatanaka
c7724b4167
fixed typo
...
llvm-svn: 128574
2011-03-30 21:15:35 +00:00
Jay Foad
53632b7c03
Remove PHINode::reserveOperandSpace(). Instead, add a parameter to
...
PHINode::Create() giving the (known or expected) number of operands.
llvm-svn: 128537
2011-03-30 11:28:46 +00:00
Evan Cheng
ed09135349
Add intrinsics @llvm.arm.neon.vmulls and @llvm.arm.neon.vmullu.* back. Frontends
...
was lowering them to sext / uxt + mul instructions. Unfortunately the
optimization passes may hoist the extensions out of the loop and separate them.
When that happens, the long multiplication instructions can be broken into
several scalar instructions, causing significant performance issue.
Note the vmla and vmls intrinsics are not added back. Frontend will codegen them
as intrinsics vmull* + add / sub. Also note the isel optimizations for catching
mul + sext / zext are not changed either.
First part of rdar://8832507, rdar://9203134
llvm-svn: 128502
2011-03-29 23:06:19 +00:00
Cameron Zwarich
95260e5ebb
Add Neon SINT_TO_FP and UINT_TO_FP lowering from v4i16 to v4f32. Fixes
...
<rdar://problem/8875309> and <rdar://problem/9057191>.
llvm-svn: 128492
2011-03-29 21:41:55 +00:00
Owen Anderson
c2b8d6ac65
Check early if this is an unsupported opcode, so that we can avoid needlessly instantiating the base register in some cases.
...
llvm-svn: 128481
2011-03-29 20:27:38 +00:00
Johnny Chen
ab342ac374
A8.6.188 STC, STC2
...
The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}.
rdar://problem/9200661
llvm-svn: 128478
2011-03-29 19:49:38 +00:00
Owen Anderson
3310282e25
Add safety check that didn't show up in testing.
...
llvm-svn: 128467
2011-03-29 17:42:25 +00:00
Owen Anderson
d73041e884
Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist.
...
llvm-svn: 128461
2011-03-29 16:45:53 +00:00
Evan Cheng
5bcaef9cc9
Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
...
isel lowering to fold the zero-extend's and take advantage of no-stall
back to back vmul + vmla:
vmull q0, d4, d6
vmlal q0, d5, d6
is faster than
vaddl q0, d4, d5
vmovl q1, d6
vmul q0, q0, q1
This allows us to vmull + vmlal for:
f = vmull_u8( vget_high_u8(s), c);
f = vmlal_u8(f, vget_low_u8(s), c);
rdar://9197392
llvm-svn: 128444
2011-03-29 01:56:09 +00:00
Daniel Dunbar
cec6959c23
Integrated-As: Add support for setting the AllowTemporaryLabels flag via
...
integrated-as.
llvm-svn: 128431
2011-03-28 22:49:19 +00:00
Johnny Chen
8b921cebc6
Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add some test cases.
...
Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly.
llvm-svn: 128417
2011-03-28 18:41:58 +00:00
Che-Liang Chiou
a4ae414c30
ptx: clean up branch code a bit
...
llvm-svn: 128405
2011-03-28 10:23:13 +00:00
Benjamin Kramer
00b5430931
Make helper static.
...
llvm-svn: 128338
2011-03-26 12:38:19 +00:00
Johnny Chen
61713b9c16
Fixed the t2PLD and friends disassembly and add two test cases.
...
llvm-svn: 128322
2011-03-26 01:32:48 +00:00
Eric Christopher
b51c27cd9a
Fix the bfi handling for or (and a mask) (and b mask). We need the two
...
masks to match inversely for the code as is to work. For the example given
we actually want:
bfi r0, r2, #1 , #1
not #0 , however, given the way the pattern is written it's not possible
at the moment.
Fixes rdar://9177502
llvm-svn: 128320
2011-03-26 01:21:03 +00:00
Johnny Chen
75c4627aea
Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID.
...
Also add some test cases.
rdar://problem/9189829
llvm-svn: 128304
2011-03-25 22:19:07 +00:00
Johnny Chen
5b840e19ef
DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases.
...
rdar://problem/9182892
llvm-svn: 128299
2011-03-25 19:35:37 +00:00
Johnny Chen
c69c7b19ae
Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to
...
t2LDREX/t2STREX instructions. Add two test cases.
llvm-svn: 128293
2011-03-25 18:29:49 +00:00
Benjamin Kramer
12ea727553
Add a note.
...
llvm-svn: 128286
2011-03-25 17:32:40 +00:00
Johnny Chen
f19366e37b
Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the disassembler to handle that.
...
rdar://problem/9184053
llvm-svn: 128285
2011-03-25 17:31:16 +00:00
Johnny Chen
583b7cb25e
Also need to handle invalid imod values for CPS2p.
...
rdar://problem/9186136
llvm-svn: 128283
2011-03-25 17:03:12 +00:00
Jakob Stoklund Olesen
e20f22be07
Ignore special ARM allocation hints for unexpected register classes.
...
Add an assertion to linear scan to prevent it from allocating registers outside
the register class.
<rdar://problem/9183021>
llvm-svn: 128254
2011-03-25 01:48:18 +00:00
Johnny Chen
1f29c2775d
Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed),
...
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.
llvm-svn: 128252
2011-03-25 01:09:48 +00:00
Matt Beaumont-Gay
7e9b4f0934
Suppress an unused variable warning in -asserts builds
...
llvm-svn: 128244
2011-03-24 22:05:48 +00:00
Johnny Chen
9672fe0126
Handle the added VBICiv*i* NEON instructions, too.
...
llvm-svn: 128243
2011-03-24 22:04:39 +00:00
Johnny Chen
69bc7c288b
Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer!
...
llvm-svn: 128241
2011-03-24 21:42:55 +00:00
Johnny Chen
1fc160fa19
T2 Load/Store Multiple:
...
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add a test case.
llvm-svn: 128240
2011-03-24 21:36:56 +00:00
Benjamin Kramer
a9c4afdeec
Plug a leak in the arm disassembler and put the tests back.
...
llvm-svn: 128238
2011-03-24 21:14:28 +00:00
Bruno Cardoso Lopes
a5de5df6d8
Add asm parsing support w/ testcases for strex/ldrex family of instructions
...
llvm-svn: 128236
2011-03-24 21:04:58 +00:00
Johnny Chen
ae5d27987a
ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled.
...
Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.
llvm-svn: 128234
2011-03-24 20:42:48 +00:00
Jim Grosbach
213800d44b
Clean up assembly statement separator support.
...
The MC asm lexer wasn't honoring a non-default (anything but ';') statement
separator. Fix that, and generalize a bit to support multi-character
statement separators.
llvm-svn: 128227
2011-03-24 18:46:34 +00:00
Johnny Chen
f6655e82b3
The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the
...
VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case.
llvm-svn: 128226
2011-03-24 18:40:38 +00:00
Johnny Chen
154393018f
Add comments to the handling of opcode CPS3p to reject invalid instruction encoding,
...
a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.
llvm-svn: 128220
2011-03-24 17:04:22 +00:00
NAKAMURA Takumi
cabdaca3c7
Target/X86: [PR8777][PR8778] Tweak alloca/chkstk for Windows targets.
...
FIXME: Some cleanups would be needed.
llvm-svn: 128206
2011-03-24 07:07:00 +00:00
Evan Cheng
1502266aba
Nasty bug in ARMBaseInstrInfo::produceSameValue(). The MachineConstantPoolEntry
...
entries being compared may not be ARMConstantPoolValue. Without checking
whether they are ARMConstantPoolValue first, and if the stars and moons
are aligned properly, the equality test may return true (when the first few
words of two Constants' values happen to be identical) and very bad things can
happen.
rdar://9125354
llvm-svn: 128203
2011-03-24 06:20:03 +00:00
Johnny Chen
e61d22bde8
CPS3p: Let's reject impossible imod values by returning false from the DisassembleMiscFrm() function.
...
Fixed rdar://problem/9179416 ARM disassembler crash: "Unknown imod operand" (fuzz testing)
Opcode=98 Name=CPS3p Format=ARM_FORMAT_MISCFRM(26)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
Before:
cpsUnknown imod operand
UNREACHABLE executed at /Volumes/data/lldb/llvm/lib/Target/ARM/InstPrinter/../ARMBaseInfo.h:123!
After:
/Volumes/data/Radar/9179416/mc-input-arm.txt:1:1: warning: invalid instruction encoding
0x93 0x1c 0x2 0xf1
^
llvm-svn: 128192
2011-03-24 02:24:36 +00:00
Johnny Chen
404fb6c07f
Load/Store Multiple:
...
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add two test cases.
llvm-svn: 128191
2011-03-24 01:40:42 +00:00
Johnny Chen
0d55ce3734
STRT and STRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
...
We now tag them as IndexModePost.
llvm-svn: 128189
2011-03-24 01:07:26 +00:00
Johnny Chen
f8507c96f1
The r128103 fix to cope with the removal of addressing modes from the MC instructions
...
were incomplete. The assert stmt needs to be updated and the operand index incrment is wrong.
Fix the bad logic and add some sanity checking to detect bad instruction encoding;
and add a test case.
llvm-svn: 128186
2011-03-24 00:28:38 +00:00
Devang Patel
2cea16e9bb
Enable GlobalMerge on darwin.
...
llvm-svn: 128183
2011-03-23 23:34:19 +00:00
Andrew Trick
80893981d6
Revert r128175.
...
I'm backing this out for the second time. It was supposed to be fixed by r128164, but the mingw self-host must be defeating the fix.
llvm-svn: 128181
2011-03-23 23:11:02 +00:00
Evan Cheng
6e799c3c58
Cmp peephole optimization isn't always safe for signed arithmetics.
...
int tries = INT_MAX;
while (tries > 0) {
tries--;
}
The check should be:
subs r4, #1
cmp r4, #0
bgt LBB0_1
The subs can set the overflow V bit when r4 is INT_MAX+1 (which loop
canonicalization apparently does in this case). cmp #0 would have cleared
it while not changing the N and Z bits. Since BGT is dependent on the V
bit, i.e. (N == V) && !Z, it is not safe to eliminate the cmp #0 .
rdar://9172742
llvm-svn: 128179
2011-03-23 22:52:04 +00:00
Andrew Trick
a7b48f34b1
Reapply Eli's r127852 now that the pre-RA scheduler can spill EFLAGS.
...
(target-specific branchless method for double-width relational comparisons on x86)
llvm-svn: 128175
2011-03-23 22:16:02 +00:00
Owen Anderson
f473d3cff9
The high bit of a Thumb2 ADR's offset is stored in bit 26, not bit 25.
...
This fixes 464.h264ref with the integrated assembler.
llvm-svn: 128172
2011-03-23 22:03:44 +00:00
Justin Holewinski
8861d34661
PTX: Improve support for 64-bit addressing
...
- Fix bug in ADDRrr/ADDRri/ADDRii selection for 64-bit addresses
- Add comparison selection for i64
- Add zext selection for i32 -> i64
- Add shl/shr/sha support for i64
llvm-svn: 128153
2011-03-23 16:58:51 +00:00
Johnny Chen
b4284e3f90
For ARM Disassembler, start a newline to dump the opcode and friends for an instruction.
...
Change inspired by llvm-bug 9530 submitted by Jyun-Yan You.
llvm-svn: 128122
2011-03-22 23:49:46 +00:00
Johnny Chen
beb7e880a2
LDRT and LDRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
...
We now tag them as IndexModePost.
This fixed http://llvm.org/bugs/show_bug.cgi?id=9530 .
llvm-svn: 128113
2011-03-22 22:28:49 +00:00
Eli Friedman
f9d5010081
A bit more analysis of a memset-related README entry.
...
llvm-svn: 128107
2011-03-22 20:49:53 +00:00
Johnny Chen
90908a8eeb
A8.6.399 VSTM:
...
VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the
MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD
are two instructions. Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm()
to reflect the change.
Also add a test case.
llvm-svn: 128103
2011-03-22 20:00:10 +00:00
Eric Christopher
448c6a5632
Migrate the fix in r128041 to ARM's fastisel support as well.
...
Fixes rdar://9169640
llvm-svn: 128100
2011-03-22 19:39:17 +00:00
Bruno Cardoso Lopes
c8d8dc9869
Change MRC and MRC2 instructions to model the output register properly
...
llvm-svn: 128085
2011-03-22 15:06:24 +00:00
Che-Liang Chiou
7c5fc3a68f
ptx: add analyze/insert/remove branch
...
llvm-svn: 128084
2011-03-22 14:12:00 +00:00
Matt Beaumont-Gay
7aa8a7d216
Avoid -Wunused-variable in -asserts builds
...
llvm-svn: 128048
2011-03-22 00:37:28 +00:00
Dan Gohman
a83323bca5
Fix fast-isel address mode folding to avoid folding instructions
...
outside of the current basic block. This fixes PR9500, rdar://9156159.
llvm-svn: 128041
2011-03-22 00:04:35 +00:00
Bill Wendling
a2eec46242
We need to pass the TargetMachine object to the InstPrinter if we are printing
...
the alias of an InstAlias instead of the thing being aliased. Because we need to
know the features that are valid for an InstAlias.
This is part of a work-in-progress.
llvm-svn: 127986
2011-03-21 04:13:46 +00:00
Eli Friedman
0da0b4aed0
This README entry was fixed recently.
...
llvm-svn: 127982
2011-03-21 01:33:03 +00:00
Evan Cheng
dd99a0a548
Re-apply r127953 with fixes: eliminate empty return block if it has no predecessors; update dominator tree if cfg is modified.
...
llvm-svn: 127981
2011-03-21 01:19:09 +00:00
Daniel Dunbar
34c65737c3
Revert r127953, "SimplifyCFG has stopped duplicating returns into predecessors
...
to canonicalize IR", it broke a lot of things.
llvm-svn: 127954
2011-03-19 21:47:14 +00:00
Evan Cheng
c5f50f7322
SimplifyCFG has stopped duplicating returns into predecessors to canonicalize IR
...
to have single return block (at least getting there) for optimizations. This
is general goodness but it would prevent some tailcall optimizations.
One specific case is code like this:
int f1(void);
int f2(void);
int f3(void);
int f4(void);
int f5(void);
int f6(void);
int foo(int x) {
switch(x) {
case 1: return f1();
case 2: return f2();
case 3: return f3();
case 4: return f4();
case 5: return f5();
case 6: return f6();
}
}
=>
LBB0_2: ## %sw.bb
callq _f1
popq %rbp
ret
LBB0_3: ## %sw.bb1
callq _f2
popq %rbp
ret
LBB0_4: ## %sw.bb3
callq _f3
popq %rbp
ret
This patch teaches codegenprep to duplicate returns when the return value
is a phi and where the phi operands are produced by tail calls followed by
an unconditional branch:
sw.bb7: ; preds = %entry
%call8 = tail call i32 @f5() nounwind
br label %return
sw.bb9: ; preds = %entry
%call10 = tail call i32 @f6() nounwind
br label %return
return:
%retval.0 = phi i32 [ %call10, %sw.bb9 ], [ %call8, %sw.bb7 ], ... [ 0, %entry ]
ret i32 %retval.0
This allows codegen to generate better code like this:
LBB0_2: ## %sw.bb
jmp _f1 ## TAILCALL
LBB0_3: ## %sw.bb1
jmp _f2 ## TAILCALL
LBB0_4: ## %sw.bb3
jmp _f3 ## TAILCALL
rdar://9147433
llvm-svn: 127953
2011-03-19 17:17:39 +00:00
Nadav Rotem
92561196b7
Add support for legalizing UINT_TO_FP of vectors on platforms which do
...
not have native support for this operation (such as X86).
The legalized code uses two vector INT_TO_FP operations and is faster
than scalarizing.
llvm-svn: 127951
2011-03-19 13:09:10 +00:00
Johnny Chen
3520263009
Fixed an assert by the ARM disassembler for LDRD_PRE/POST.
...
The relevant instruction table entries were changed sometime ago to no longer take
<Rt2> as an operand. Modify ARMDisassemblerCore.cpp to accomodate the change and
add a test case.
llvm-svn: 127935
2011-03-19 01:16:20 +00:00
Owen Anderson
16fce7d4af
Add support to the ARM asm parser for the register-shifted-register forms of basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA.
...
llvm-svn: 127917
2011-03-18 22:50:18 +00:00
Evan Cheng
93d04c1c00
Match a few more obvious patterns to revsh. rdar://9147637.
...
llvm-svn: 127913
2011-03-18 21:52:42 +00:00
Eli Friedman
8d903449c3
Revert r127852; it's apparently causing an ICE on mingw.
...
llvm-svn: 127909
2011-03-18 21:12:29 +00:00
Owen Anderson
25ab3f714f
Clean whitespace.
...
llvm-svn: 127900
2011-03-18 19:47:14 +00:00
Owen Anderson
acda6f77a8
Reduce code duplication.
...
llvm-svn: 127899
2011-03-18 19:46:58 +00:00
Justin Holewinski
d9c382441b
PTX: Fix various codegen issues
...
- Emit mad instead of mad.rn for shader model 1.0
- Emit explicit mov.u32 instructions for reading global variables
- (most PTX instructions cannot take global variable immediates)
llvm-svn: 127895
2011-03-18 19:24:28 +00:00
Owen Anderson
c23c6e0c1a
Thumb2 PC-relative loads require a fixup rather than just an immediate.
...
llvm-svn: 127888
2011-03-18 17:42:55 +00:00
Joerg Sonnenberger
aa8ac259e9
Support explicit argument forms for the X86 string instructions.
...
For now, only the default segments are supported.
llvm-svn: 127875
2011-03-18 11:59:40 +00:00
Che-Liang Chiou
2b173c0443
ptx: fix parameter order that is reversed
...
llvm-svn: 127874
2011-03-18 11:23:56 +00:00
Che-Liang Chiou
f4a2c17cf5
ptx: add unconditional and conditional branch
...
llvm-svn: 127873
2011-03-18 11:08:52 +00:00
Eli Friedman
64a2b7e4f2
Add a target-specific branchless method for double-width relational
...
comparisons on x86. Essentially, the way this works is that SUB+SBB sets
the relevant flags the same way a double-width CMP would.
This is a substantial improvement over the generic lowering in LLVM. The output
is also shorter than the gcc-generated output; I haven't done any detailed
benchmarking, though.
llvm-svn: 127852
2011-03-18 02:34:11 +00:00
Johnny Chen
14f091b6ab
The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset.
...
Remove the offending logic and update the test cases.
llvm-svn: 127843
2011-03-18 00:38:03 +00:00
Owen Anderson
0753b79795
There are two pseudos in this case that are Thumb mode, not one.
...
llvm-svn: 127840
2011-03-17 23:52:05 +00:00
Johnny Chen
41abb5b0f7
It used to be that t_addrmode_s4 was used for both:
...
o A8.6.195 STR (register) -- Encoding T1
o A8.6.193 STR (immediate, Thumb) -- Encoding T1
It has been changed so that now they use different addressing modes
and thus different MC representation (Operand Infos). Modify the
disassembler to reflect the change, and add relevant tests.
llvm-svn: 127833
2011-03-17 22:04:05 +00:00
Richard Osborne
6bad79b514
Add XCore intrinsic for setpsc.
...
llvm-svn: 127821
2011-03-17 18:42:05 +00:00
Cameron Zwarich
cea63dc052
Move more logic into getTypeForExtArgOrReturn.
...
llvm-svn: 127809
2011-03-17 14:53:37 +00:00
Cameron Zwarich
a5746339cc
Rename getTypeForExtendedInteger() to getTypeForExtArgOrReturn().
...
llvm-svn: 127807
2011-03-17 14:21:56 +00:00
Nick Lewycky
9dac4ea71f
Add "swi" which is an obsolete mnemonic for "svc".
...
llvm-svn: 127788
2011-03-17 01:46:14 +00:00
Eli Friedman
dcc256df41
A couple new README entries.
...
llvm-svn: 127786
2011-03-17 01:22:09 +00:00
Cameron Zwarich
2bb1e45ea3
The x86-64 ABI says that a bool is only guaranteed to be sign-extended to a byte
...
rather than an int. Thankfully, this only causes LLVM to miss optimizations, not
generate incorrect code.
This just fixes the zext at the return. We still insert an i32 ZextAssert when
reading a function's arguments, but it is followed by a truncate and another i8
ZextAssert so it is not optimized.
llvm-svn: 127766
2011-03-16 22:20:18 +00:00
Richard Osborne
8b90369d96
Add XCore intrinsics for setclk, setrdy.
...
llvm-svn: 127761
2011-03-16 21:56:00 +00:00
Richard Osborne
318e25c620
Add checkevent intrinsic to check if any resources owned by the current thread
...
can event.
llvm-svn: 127741
2011-03-16 18:34:00 +00:00
Johnny Chen
e88573849d
There were two issues fixed:
...
1. The ARM Darwin *r9 call instructions were pseudo-ized recently.
Modify the ARMDisassemblerCore.cpp file to accomodate the change.
2. The disassembler was unnecessarily adding 8 to the sign-extended imm24:
imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate)
// Encoding A1
It has no business doing such. Removed the offending logic.
Add test cases to arm-tests.txt.
llvm-svn: 127707
2011-03-15 22:27:33 +00:00
Bill Wendling
c12aadb9b6
The VTBL (and VTBX) instructions are rather permissive concerning the masks they
...
accept. If a value in the mask is out of range, it uses the value 0, for VTBL,
or leaves the value unchanged, for VTBX.
llvm-svn: 127700
2011-03-15 21:15:20 +00:00
Bill Wendling
388dad6d62
Some minor cleanups based on feedback.
...
llvm-svn: 127694
2011-03-15 20:47:26 +00:00
Evan Cheng
59ba6777c3
Do not form thumb2 ldrd / strd if the offset is by multiple of 4. rdar://9133587
...
llvm-svn: 127683
2011-03-15 18:41:52 +00:00
Richard Osborne
601c8a703b
Don't indent cases in a switch, no functionality change.
...
llvm-svn: 127681
2011-03-15 15:55:30 +00:00
Richard Osborne
af1b66c427
On the XCore the scavenging slot should be closest to the SP.
...
llvm-svn: 127680
2011-03-15 15:10:11 +00:00
Richard Osborne
70204c1c29
Add XCore intrinsics for getps, setps, setsr and clrsr.
...
llvm-svn: 127678
2011-03-15 13:45:47 +00:00
Justin Holewinski
8948485aa7
PTX: Set PTX 2.0 as the minimum supported version
...
- Remove PTX 1.4 code generation
- Change type of intrinsics to .v4.i32 instead of .v4.i16
- Add and/or/xor integer instructions
llvm-svn: 127677
2011-03-15 13:24:15 +00:00
Duncan Sands
fc3e4d63e1
Avoid a compiler warning about reg possibly being used uninitialized
...
when building with assertions disabled.
llvm-svn: 127675
2011-03-15 08:41:24 +00:00
Sean Callanan
a38db2eeda
Enabled disassembler support for AVX instructions
...
in the instruction tables and fixed a few bugs that
were causing decode conflicts. Rudimentary tests
are coming up in the next patch.
llvm-svn: 127646
2011-03-15 01:28:15 +00:00
Sean Callanan
5a51ccdc0f
X86 table-generator and disassembler support for the AVX
...
instruction set. This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures. Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.
llvm-svn: 127644
2011-03-15 01:23:15 +00:00
Johnny Chen
a86399b8e6
Fixed an ARM disassembler bug where it does not handle STRi12 correctly because an extra
...
register operand was erroneously added. Remove an incorrect assert which triggers the bug.
rdar://problem/9131529
llvm-svn: 127642
2011-03-15 01:13:17 +00:00
Jim Grosbach
3de97c6e32
Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches.
...
Also more cleanly separate the ARM vs. Thumb functionality. Previously, the
encoding would be incorrect for some Thumb instructions (the indirect calls).
llvm-svn: 127637
2011-03-15 00:30:40 +00:00
Bill Wendling
da1364d669
Generate a VTBL instruction instead of a series of loads and stores when we
...
can. As Nate pointed out, VTBL isn't super performant, but it *has* to be better
than this:
_shuf:
@ BB#0: @ %entry
push {r4, r7, lr}
add r7, sp, #4
sub sp, #12
mov r4, sp
bic r4, r4, #7
mov sp, r4
mov r2, sp
vmov d16, r0, r1
orr r0, r2, #6
orr r3, r2, #7
vst1.8 {d16[0]}, [r3]
vst1.8 {d16[5]}, [r0]
subs r4, r7, #4
orr r0, r2, #5
vst1.8 {d16[4]}, [r0]
orr r0, r2, #4
vst1.8 {d16[4]}, [r0]
orr r0, r2, #3
vst1.8 {d16[0]}, [r0]
orr r0, r2, #2
vst1.8 {d16[2]}, [r0]
orr r0, r2, #1
vst1.8 {d16[1]}, [r0]
vst1.8 {d16[3]}, [r2]
vldr.64 d16, [sp]
vmov r0, r1, d16
mov sp, r4
pop {r4, r7, pc}
The "illegal" testcase in vext.ll is no longer illegal.
<rdar://problem/9078775>
llvm-svn: 127630
2011-03-14 23:02:38 +00:00
Jim Grosbach
6ee5aef028
Remove some dead patterns.
...
llvm-svn: 127601
2011-03-14 18:34:35 +00:00
Evan Cheng
fbb846289a
Indentation.
...
llvm-svn: 127595
2011-03-14 18:02:30 +00:00
Justin Holewinski
a2f7c8557c
PTX: Emit global arrays with proper sizes
...
- Emit all arrays as type .b8 and proper sizes in bytes to conform
to the output of nvcc
llvm-svn: 127584
2011-03-14 15:40:11 +00:00
Justin Holewinski
995d10cfea
PTX: Add support for sqrt/sin/cos intrinsics
...
llvm-svn: 127578
2011-03-14 14:09:33 +00:00
Che-Liang Chiou
6ff0aa8ab3
ptx: add set.p instruction and related changes to predicate execution
...
llvm-svn: 127577
2011-03-14 11:26:01 +00:00
Che-Liang Chiou
962612fc5c
ptx: add basic support of predicate execution
...
llvm-svn: 127569
2011-03-13 17:26:00 +00:00
Eric Christopher
80a45901e0
Sometimes isPredicable lies to us and tells us we don't need the operands.
...
Go ahead and add them on when we might want to use them and let
later passes remove them.
Fixes rdar://9118569
llvm-svn: 127518
2011-03-12 01:09:29 +00:00
Jim Grosbach
f7531e7697
Add FIXME.
...
llvm-svn: 127516
2011-03-12 00:51:00 +00:00
Jim Grosbach
555d910477
Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the same
...
actual instruction as the non-Darwin defs, but have different call-clobber
semantics and so need separate patterns. They don't need to duplicate the
encoding information, however.
llvm-svn: 127515
2011-03-12 00:45:26 +00:00
Jim Grosbach
923c731f15
Add a FIXME.
...
llvm-svn: 127511
2011-03-11 23:25:21 +00:00
Jim Grosbach
daffeb06fb
Pseudo-ize the ARM 'B' instruction.
...
llvm-svn: 127510
2011-03-11 23:24:15 +00:00
Jim Grosbach
2226dfbea2
Remove dead code. These ARM instruction definitions no longer exist.
...
llvm-svn: 127509
2011-03-11 23:15:02 +00:00
Jim Grosbach
009af69d6d
Pseudo-ize VMOVDcc and VMOVScc.
...
llvm-svn: 127506
2011-03-11 23:09:50 +00:00
Jim Grosbach
61ff87cd2d
80 columns
...
llvm-svn: 127505
2011-03-11 23:00:16 +00:00
Jim Grosbach
27eaca3e0d
Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-
...
effect that we get proper instruction printing using the "pop" mnemonic for it.
llvm-svn: 127502
2011-03-11 22:51:41 +00:00
Jim Grosbach
ee6075cda5
ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same
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as for VDUP32d and VDUP32q, respectively.
llvm-svn: 127489
2011-03-11 20:44:08 +00:00
Jim Grosbach
3329263352
ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q
...
and VDUPLN32d, respectively.
llvm-svn: 127486
2011-03-11 20:31:17 +00:00
Jim Grosbach
431682981d
ARM VREV64df and VREV64qf can just be patterns. The instruction is the same
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as for VREV64d32 and VREV64q32, respectively.
llvm-svn: 127485
2011-03-11 20:18:05 +00:00
Jim Grosbach
fff6ff502b
This FIXME has been fixed.
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llvm-svn: 127483
2011-03-11 20:07:37 +00:00
Jim Grosbach
2ecded3a94
Properly pseudo-ize ARM MVNCCi.
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llvm-svn: 127482
2011-03-11 19:55:55 +00:00
Jim Grosbach
39804c0b44
Fix MOVCCi32imm to be have ARM-mode Requires and a proper size (8 bytes, was 4).
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llvm-svn: 127469
2011-03-11 18:00:42 +00:00
Chris Lattner
2cd24b852f
silence a conditional assignment -Wuninitialized warning.
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llvm-svn: 127453
2011-03-11 02:12:51 +00:00
Jim Grosbach
ed45ac390c
Properly pseudo-ize ARM MOVCCi and MOVCCi16.
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llvm-svn: 127442
2011-03-11 01:09:28 +00:00
Eric Christopher
46f43c9cce
Change the x86 32-bit scheduler to register pressure and fix up the
...
corresponding testcases back to the previous versions.
Fixes some performance regressions only seen on 32-bit.
llvm-svn: 127441
2011-03-11 01:05:58 +00:00
Jim Grosbach
1986d9ac8f
Properly pseudo-ize MOVCCr and MOVCCs.
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llvm-svn: 127434
2011-03-10 23:56:09 +00:00
Jim Grosbach
5891b1323a
DMB can just be a pat referencing MCR.
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llvm-svn: 127423
2011-03-10 19:27:17 +00:00
Jim Grosbach
4b74ef6ca9
Reorganize a bit. No functional change, just moving patterns up.
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llvm-svn: 127422
2011-03-10 19:21:08 +00:00
Jim Grosbach
db549a7f6c
Pseudo-instructions are codegenonly by definition.
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llvm-svn: 127420
2011-03-10 19:06:39 +00:00
Justin Holewinski
a26d2f782e
PTX: Add preliminary support for floating-point divide and multiply-and-add
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llvm-svn: 127410
2011-03-10 16:57:18 +00:00
Che-Liang Chiou
fc6c7ba9d5
ptx: add the rest of special registers of ISA version 2.0
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llvm-svn: 127397
2011-03-10 04:05:57 +00:00
Stuart Hastings
fd42046d56
Revert 127359; it broke lencod.
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llvm-svn: 127382
2011-03-10 00:25:53 +00:00
Evan Cheng
a3a7a7e364
Re-commit 127368 and 127371. They are exonerated.
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llvm-svn: 127380
2011-03-10 00:16:32 +00:00
Evan Cheng
d7a2008a55
Revert 127368 and 127371 for now.
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llvm-svn: 127376
2011-03-09 23:53:17 +00:00
Evan Cheng
b717770dfe
Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be more
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flexible.
If it returns a register class that's different from the input, then that's the
register class used for cross-register class copies.
If it returns a register class that's the same as the input, then no cross-
register class copies are needed (normal copies would do).
If it returns null, then it's not at all possible to copy registers of the
specified register class.
llvm-svn: 127368
2011-03-09 22:47:38 +00:00
Benjamin Kramer
f1c1220d8f
Fix a pasto that broke all x86_64-elf targets.
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llvm-svn: 127365
2011-03-09 22:07:13 +00:00
Stuart Hastings
61f9a3dab2
X86 byval copies no longer always_inline. <rdar://problem/8706628>
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llvm-svn: 127359
2011-03-09 21:10:30 +00:00
Johnny Chen
6bf5d7a170
LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.
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The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16. Add extra logic to recover from that.
Fixed an assert reported by Sean Callanan
llvm-svn: 127354
2011-03-09 20:01:14 +00:00
Bruno Cardoso Lopes
88bef593d8
Improve varags handling, with testcases. Patch by Sasa Stankovic
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llvm-svn: 127349
2011-03-09 19:22:22 +00:00
Jan Sjödin
c7c66d9f88
Add createELFObjectTargetWriter method to TargetAsmBackend, which enables construction of non-standard ELFObjectWriters that can be used in MCJIT.
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llvm-svn: 127346
2011-03-09 18:44:41 +00:00
NAKAMURA Takumi
fe84f8672a
Target/X86: Tweak va_arg for Win64 not to miss taking va_start when number of fixed args > 4.
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llvm-svn: 127328
2011-03-09 11:33:15 +00:00
Bill Wendling
68934338ab
* Correct encoding for VSRI.
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* Add tests for VSRI and VSLI.
llvm-svn: 127297
2011-03-09 00:33:17 +00:00
Bill Wendling
b790c462c0
Correct the encoding for VRSRA and VSRA instructions.
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llvm-svn: 127294
2011-03-09 00:00:35 +00:00
Bill Wendling
ab9f04b6d8
* Fix VRSHR and VSHR to have the correct encoding for the immediate.
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* Update the NEON shift instruction test to expect what 'as' produces.
llvm-svn: 127293
2011-03-08 23:48:09 +00:00
Benjamin Kramer
d5782492c8
X86: Fix the (saddo/ssub x, 1) -> incl/decl selection to check the right operand for 1.
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Found by inspection.
llvm-svn: 127247
2011-03-08 15:20:20 +00:00
Justin Holewinski
d7426856e9
PTX: Add intrinsic support for ntid, ctaid, and nctaid registers
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llvm-svn: 127246
2011-03-08 14:10:18 +00:00
Eric Christopher
72d7cc25f3
Turn on list-ilp scheduling by default on x86 and x86-64, fix up
...
testcases accordingly. Some are currently xfailed and will be filed
as bugs to be fixed or understood.
Performance results:
roughly neutral on SPEC
some micro benchmarks in the llvm suite are up between 100 and 150%, only
a pair of regressions that are due to be investigated
john-the-ripper saw:
10% improvement in traditional DES
8% improvement in BSDI DES
59% improvement in FreeBSD MD5
67% improvement in OpenBSD Blowfish
14% improvement in LM DES
Small compile time impact.
llvm-svn: 127208
2011-03-08 02:42:25 +00:00
Bob Wilson
f8c4d1ded9
Fix a compiler crash where a Glue value had multiple uses. Radar 9049552.
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llvm-svn: 127198
2011-03-08 01:17:20 +00:00
Bob Wilson
94403e6221
Fix comment typos.
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llvm-svn: 127197
2011-03-08 01:17:16 +00:00
Bill Wendling
958e854f40
Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
...
expand the testing of the narrowing shift right instructions.
No functionality change.
llvm-svn: 127193
2011-03-07 23:38:41 +00:00
Cameron Zwarich
a1920d7f51
Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.
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llvm-svn: 127175
2011-03-07 21:56:36 +00:00
Anton Korobeynikov
8c7010e832
ARM assembler stuff is crazy: for .setfp positive values of offset corresponds to "add" instruction, not to "sub" as in .pad case
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llvm-svn: 127106
2011-03-05 18:44:00 +00:00
Anton Korobeynikov
f15e269356
In Thumb1 mode the constant might be materialized via the load from constpool. Emit unwinding information in case when this load from constpool is used to change the stack pointer in the prologue.
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llvm-svn: 127105
2011-03-05 18:43:55 +00:00
Anton Korobeynikov
d8873d31a8
Implement frame unwinding information emission for Thumb1. Not finished yet because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed.
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llvm-svn: 127104
2011-03-05 18:43:50 +00:00
Anton Korobeynikov
d4828b54ec
Add unwind information emission for thumb stuff
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llvm-svn: 127103
2011-03-05 18:43:43 +00:00
Anton Korobeynikov
7ba97c2831
Handle MI flags inside Thumb2SizeReduction pass.
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llvm-svn: 127102
2011-03-05 18:43:38 +00:00
Anton Korobeynikov
917ca94111
Preliminary support for ARM frame save directives emission via MI flags.
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This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.
llvm-svn: 127101
2011-03-05 18:43:32 +00:00
Anton Korobeynikov
62e48532b9
Some first rudimentary support for ARM EHABI: print exception table in "text mode".
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llvm-svn: 127099
2011-03-05 18:43:15 +00:00
Bob Wilson
1497601a7b
Remove unused conditional negate operations.
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llvm-svn: 127090
2011-03-05 16:54:31 +00:00
Che-Liang Chiou
15aba09539
ptx: add basic intrinsic support
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llvm-svn: 127084
2011-03-05 14:17:37 +00:00
Andrew Trick
7db197d209
Increased the register pressure limit on x86_64 from 8 to 12
...
regs. This is the only change in this checkin that may affects the
default scheduler. With better register tracking and heuristics, it
doesn't make sense to artificially lower the register limit so much.
Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to
give the scheduler a way to account for div and sqrt on targets that
don't have an itinerary. It is currently defaults to 10 (the actual
number doesn't matter much), but only takes effect on non-default
schedulers: list-hybrid and list-ilp.
Added several heuristics that can be individually disabled for the
non-default sched=list-ilp mode. This helps us determine how much
better we can do on a given benchmark than the default
scheduler. Certain compute intensive loops run much faster in this
mode with the right set of heuristics, and it doesn't seem to have
much negative impact elsewhere. Not all of the heuristics are needed,
but we still need to experiment to decide which should be disabled by
default for sched=list-ilp.
llvm-svn: 127067
2011-03-05 08:00:22 +00:00
Andrew Trick
5023de34d3
whitespace
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llvm-svn: 127065
2011-03-05 06:31:54 +00:00
Bill Wendling
73b20a325f
Initialize variable.
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llvm-svn: 127038
2011-03-04 21:38:47 +00:00
Bruno Cardoso Lopes
52c64a2eb3
Improve div/rem node handling on mips. Patch by Akira Hatanaka
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llvm-svn: 127034
2011-03-04 21:03:24 +00:00
Bruno Cardoso Lopes
e697a8bcb0
Expands register/immediate pairs when the immediate is too large to fit in 16-bit field. Patch by Akira Hatanaka
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llvm-svn: 127032
2011-03-04 20:48:08 +00:00
Bruno Cardoso Lopes
0545e7fe48
Rewrite and simplify o32 vaarg passing, no functional changes. Patch by Sasa Stankovic
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llvm-svn: 127029
2011-03-04 20:27:44 +00:00
Bruno Cardoso Lopes
99619e5bef
Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka
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llvm-svn: 127027
2011-03-04 20:01:52 +00:00
Bruno Cardoso Lopes
5347fd6512
Fix an old copy-n-paste
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llvm-svn: 127020
2011-03-04 19:20:24 +00:00
Devang Patel
23ee9fdba3
Disable ARMGlobalMerge on darwin. The debugger is not yet able to extract individual variable's info from merged global.
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llvm-svn: 127019
2011-03-04 19:11:05 +00:00
Bruno Cardoso Lopes
9390dc6271
Expands FCOS and FSIN nodes when type is f64.
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llvm-svn: 127017
2011-03-04 18:54:14 +00:00
Bruno Cardoso Lopes
a49a596acf
Fixes addc pattern when immediate cannot be represented with 16-bit. Patch by Akira Hatanaka
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llvm-svn: 127005
2011-03-04 17:59:18 +00:00
Bruno Cardoso Lopes
5400401372
Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira
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llvm-svn: 127003
2011-03-04 17:51:39 +00:00
Kalle Raiskila
6e33c92ffb
Allow vector shifts (shl,lshr,ashr) on SPU.
...
There was a previous implementation with patterns that would
have matched e.g.
shl <v4i32> <i32>,
but this is not valid LLVM IR so they never were selected.
llvm-svn: 126998
2011-03-04 13:19:18 +00:00
Kalle Raiskila
72cfda1a29
Allow load from constant on SPU.
...
A 'load <4 x i32>* null' crashes llc before this fix.
llvm-svn: 126995
2011-03-04 12:00:11 +00:00
Eli Friedman
be07c34368
PR9377: Handle x86 str with register operand in a way consistent with gas.
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llvm-svn: 126970
2011-03-04 00:10:17 +00:00
Bob Wilson
c48ba54186
PR8053: Fix encoding of S bit in some ARM instructions.
...
Patch by Zonr Chang!
llvm-svn: 126967
2011-03-03 23:07:15 +00:00
Richard Osborne
88d0d840f2
Optimize fprintf -> iprintf if there are no floating point arguments
...
and siprintf is available on the target.
llvm-svn: 126940
2011-03-03 14:20:22 +00:00
Justin Holewinski
396fdaee6d
PTX: Fix Emacs renaming a symbol
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llvm-svn: 126938
2011-03-03 14:09:40 +00:00
Richard Osborne
021b589253
Optimize sprintf -> siprintf if there are no floating point arguments
...
and siprintf is available on the target.
llvm-svn: 126937
2011-03-03 14:09:28 +00:00
Justin Holewinski
86e749c620
PTX: Fix a couple of lint violations
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llvm-svn: 126936
2011-03-03 13:34:29 +00:00
Richard Osborne
df829ddcb7
Optimize printf -> iprintf if there are no floating point arguments
...
and iprintf is available on the target. Currently iprintf is only
marked as being available on the XCore.
llvm-svn: 126935
2011-03-03 13:17:51 +00:00
Tilmann Scheller
ab6450ec63
Use X86_thiscall calling convention for Win64 as well.
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llvm-svn: 126934
2011-03-03 07:49:07 +00:00
Bob Wilson
72ccdfe148
Add a readme entry for the redundant movw issue for pr9370.
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llvm-svn: 126930
2011-03-03 06:39:09 +00:00
Bob Wilson
42f80596ca
pr9367: Add missing predicated BLX instructions.
...
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.
llvm-svn: 126915
2011-03-03 01:41:01 +00:00
Kevin Enderby
58cc960338
Fixes an assertion failure while disassembling ARM rsbs reg/reg form.
...
Patch by Ted Kremenek!
llvm-svn: 126895
2011-03-02 23:08:33 +00:00
Renato Golin
967b93c6e3
Fixing a bug when printing fpu text to object file. Patch by Mans Rullgard.
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llvm-svn: 126882
2011-03-02 21:20:09 +00:00
Tilmann Scheller
c557d1eeb4
Add Win64 thiscall calling convention.
...
llvm-svn: 126862
2011-03-02 19:29:22 +00:00
David Greene
2fd6d03bc9
[AVX] Fix mask predicates for 256-bit UNPCKLPS/D and implement
...
missing patterns for them.
Add a SIMD test subdirectory to hold tests for SIMD instruction
selection correctness and quality.
'
llvm-svn: 126845
2011-03-02 17:23:43 +00:00
Che-Liang Chiou
8ab0f86f1b
ptx: fix lint and compiler warnings
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llvm-svn: 126838
2011-03-02 07:58:46 +00:00
Che-Liang Chiou
3529b49230
Add 64-bit addressing to PTX backend
...
- Add '64bit' sub-target option.
- Select 32-bit/64-bit loads/stores based on '64bit' option.
- Fix function parameter order.
Patch by Justin Holewinski
llvm-svn: 126837
2011-03-02 07:36:48 +00:00