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803 Commits

Author SHA1 Message Date
Akira Hatanaka
90fcf55a54 Lower MachineInstr to MC Inst and print to .s files. 
llvm-svn: 134661
 2011-07-07 23:56:50 +00:00
Akira Hatanaka
e3bcd9ec0a Remove unnecessary newline. 
llvm-svn: 134645
 2011-07-07 22:06:18 +00:00
Akira Hatanaka
ccdaa7946c Rather than having printMemOperand change the way memory operands are printed 
based on a modifier, split it into two functions.

llvm-svn: 134637
 2011-07-07 20:54:20 +00:00
Akira Hatanaka
9cddf51671 Define class MipsMCInstLower. 
llvm-svn: 134633
 2011-07-07 20:24:54 +00:00
Akira Hatanaka
382742199f Change visibility of MipsAsmPrinter. 
llvm-svn: 134630
 2011-07-07 20:10:52 +00:00
Akira Hatanaka
b5f9a0486c Define class MipsMCSymbolRefExpr. 
llvm-svn: 134629
 2011-07-07 19:27:22 +00:00
Akira Hatanaka
0de1fce485 Simplify MipsRegisterInfo::eliminateFrameIndex. 
llvm-svn: 134628
 2011-07-07 19:13:09 +00:00
Akira Hatanaka
d3c031eb00 Reverse order of operands of address operand mem so that the base operand comes 
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.

llvm-svn: 134625
 2011-07-07 18:57:00 +00:00
Akira Hatanaka
31119a50bc Add missing return statement. 
llvm-svn: 134622
 2011-07-07 18:27:36 +00:00
Evan Cheng
18acf2200c Compute feature bits at time of MCSubtargetInfo initialization. 
llvm-svn: 134606
 2011-07-07 07:07:08 +00:00
Evan Cheng
018b2055fc Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency. 
llvm-svn: 134281
 2011-07-01 22:36:09 +00:00
Evan Cheng
e7e74a3250 Rename TargetSubtarget to TargetSubtargetInfo for consistency. 
llvm-svn: 134259
 2011-07-01 21:01:15 +00:00
Evan Cheng
771cdf9b5d - Added MCSubtargetInfo to capture subtarget features and scheduling 
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
  and hide more details from targets.

llvm-svn: 134257
 2011-07-01 20:45:01 +00:00
Evan Cheng
157d40fba1 Hide the call to InitMCInstrInfo into tblgen generated ctor. 
llvm-svn: 134244
 2011-07-01 17:57:27 +00:00
Akira Hatanaka
960f6898a6 Improve Mips back-end's handling of DBG_VALUE. 
llvm-svn: 134224
 2011-07-01 01:04:43 +00:00
Evan Cheng
034261674b Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to 
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.

The fix is to just have the clients explictly pass the CPU name!

llvm-svn: 134127
 2011-06-30 01:53:36 +00:00
Eric Christopher
f04ac137f3 Update comment for getRegForInlineAsmConstraint for Mips. 
llvm-svn: 134087
 2011-06-29 19:33:04 +00:00
Eric Christopher
82c3bcfb14 Remove getRegClassForInlineAsmConstraint for Mips. 
Part of rdar://9643582

llvm-svn: 134084
 2011-06-29 19:04:31 +00:00
Evan Cheng
b4dc8bdd22 Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC. 
llvm-svn: 134049
 2011-06-29 01:14:12 +00:00
Evan Cheng
65e7766262 Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo. 
llvm-svn: 134030
 2011-06-28 21:14:33 +00:00
Evan Cheng
b83b307ae8 Hide more details in tablegen generated MCRegisterInfo ctor function. 
llvm-svn: 134027
 2011-06-28 20:44:22 +00:00
Evan Cheng
a115f77785 Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc 
llvm-svn: 134024
 2011-06-28 20:07:07 +00:00
Evan Cheng
4a169be530 - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and 
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
 2011-06-28 19:10:37 +00:00
Evan Cheng
6fea701360 Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc 
into XXXGenRegisterInfo.inc.

llvm-svn: 133922
 2011-06-27 18:32:37 +00:00
Akira Hatanaka
539ba34c25 Change the chain input of nodes that load the address of a function. This change 
enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.

llvm-svn: 133811
 2011-06-24 19:01:25 +00:00
Akira Hatanaka
3a3e7dfd84 Prevent generation of redundant addiu instructions that compute address of 
static variables or functions. 

llvm-svn: 133803
 2011-06-24 17:55:19 +00:00
Evan Cheng
e0801b07e0 Starting to refactor Target to separate out code that's needed to fully describe 
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.

llvm-svn: 133782
 2011-06-24 01:44:41 +00:00
Akira Hatanaka
288c049012 Add A0 and A1 to the list of registers used for returning a value in order to 
handle functions with return type Complex long long.

llvm-svn: 133497
 2011-06-21 01:28:11 +00:00
Akira Hatanaka
1197db1f9b Coding style fixes. 
llvm-svn: 133496
 2011-06-21 01:02:03 +00:00
Akira Hatanaka
1e08980a21 Re-apply 132758 and 132768 which were speculatively reverted in 132777. 
llvm-svn: 133494
 2011-06-21 00:40:49 +00:00
Bruno Cardoso Lopes
762b3d1f0f Silence warnings in non assert builds. Patch by David Blaikie 
llvm-svn: 133118
 2011-06-16 00:40:02 +00:00
Jakob Stoklund Olesen
d89900e14c Use set operations instead of plain lists to enumerate register classes. 
This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.

I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.

llvm-svn: 133105
 2011-06-15 23:28:14 +00:00
Jakob Stoklund Olesen
164dc685e5 Remove custom allocation order boilerplate that is no longer needed. 
The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.

Some targets still use custom allocation orders:

ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.

X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.

SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.

llvm-svn: 132781
 2011-06-09 16:56:59 +00:00
Eric Christopher
24dafa3dbc Speculatively revert 132758 and 132768 to try to fix the Windows buildbots. 
llvm-svn: 132777
 2011-06-09 16:03:19 +00:00
Akira Hatanaka
33ec063f3b Initial support for inline asm memory operand constraints. 
llvm-svn: 132768
 2011-06-09 03:31:05 +00:00
Eric Christopher
1ae9ec6124 Add a parameter to CCState so that it can access the MachineFunction. 
No functional change.

Part of PR6965

llvm-svn: 132763
 2011-06-08 23:55:35 +00:00
Akira Hatanaka
38115eb019 Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the 
dynamically allocated stack area was not set.

llvm-svn: 132758
 2011-06-08 21:28:09 +00:00
Akira Hatanaka
ea8ce56dbb Reorganize code in MipsTargetLowering::LowerCall to improve readability. 
llvm-svn: 132756
 2011-06-08 17:39:33 +00:00
Akira Hatanaka
101d50423a Refactor MipsTargetLowering::EmitInstrWithCustomInserter. 
llvm-svn: 132726
 2011-06-07 19:28:39 +00:00
Akira Hatanaka
e56d1fa083 Put back removed line. 
llvm-svn: 132725
 2011-06-07 19:03:14 +00:00
Akira Hatanaka
3b7982650c Coding style fixes. 
- Fix indentation.
- Move comments.
- Fit lines in 80 columns.
- Remove dead code.

llvm-svn: 132724
 2011-06-07 18:58:42 +00:00
Akira Hatanaka
f56f544d80 Use tabs to separate opcode and operand strings. 
llvm-svn: 132718
 2011-06-07 18:16:51 +00:00
Akira Hatanaka
fe54bb9de1 Add comments for wrapper node patterns in MipsInstrInfo.td. 
llvm-svn: 132717
 2011-06-07 18:00:14 +00:00
Akira Hatanaka
fbeb14925f Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue: 
- cfi directives are not inserted at the right location or in the right order.
- The source MachineLocation for the cfi directive that changes the cfa register
  to $fp should be MachineLocation::VirtualFP.
- A PROLOG_LABEL that marks the beginning of cfi_offset directives for
  callee-saved register is emitted even when no callee-saved registers are
  saved.
- When a callee-saved double precision register is saved, two cfi_offset
  directives, one for each of the paired single precision registers, should be
  emitted.
 
 

llvm-svn: 132703
 2011-06-07 02:17:21 +00:00
Akira Hatanaka
1f91013bcb Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic. 
llvm-svn: 132448
 2011-06-02 01:03:14 +00:00
Akira Hatanaka
69ae562f33 Custom-lower FRAMEADDR. Patch by Sasa Stankovic. 
llvm-svn: 132444
 2011-06-02 00:24:44 +00:00
Bruno Cardoso Lopes
9231127d37 Fix uninitialized variables and silence warnings 
llvm-svn: 132355
 2011-05-31 20:25:26 +00:00
Bruno Cardoso Lopes
728ea362c3 This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, 
nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.

Patch by Sasa Stankovic.

llvm-svn: 132323
 2011-05-31 02:54:07 +00:00
Bruno Cardoso Lopes
f6fa29e7a1 This patch implements the thread local storage. Implemented are General 
Dynamic, Initial Exec and Local Exec TLS models.

Patch by Sasa Stankovic

llvm-svn: 132322
 2011-05-31 02:53:58 +00:00
Rafael Espindola
33f7d7f9fa Use the dwarf->llvm mapping to print register names in the cfi 
directives.

Fixes PR9826.

llvm-svn: 132317
 2011-05-30 20:20:15 +00:00
Rafael Espindola
51a8fe13bc Remove the dwarf numbers from the D registers. They don't have dwarf numbers 
and should probably be encoded as

DW_OP_reg 32 DW_OP_piece 4 DW_OP_reg 33

llvm-svn: 132274
 2011-05-29 02:21:01 +00:00
Akira Hatanaka
45b3f52c41 Change the set of callee-saved registers for non-MIPS32 architectures specified 
in MipsRegisterInfo::getCalleeSavedRegs so that both registers paired for a
double precision register get saved.

 

llvm-svn: 132243
 2011-05-28 01:41:05 +00:00
Akira Hatanaka
1590e4eab1 Define a wrapper node for target constant nodes (tglobaladdr, etc.). 
Need this to prevent emitting illegal conditional move instructions. 

llvm-svn: 132240
 2011-05-28 01:07:07 +00:00
Akira Hatanaka
71839b355d Use MachineFrameInfo::hasCalls instead of MipsFunctionInfo::hasCall to check if 
a function has any function calls.

llvm-svn: 132140
 2011-05-26 20:30:31 +00:00
Rafael Espindola
a77d692299 Fix some dwarf register numbers. 
llvm-svn: 132136
 2011-05-26 19:25:47 +00:00
Akira Hatanaka
5bfbea9ef2 Add support for C++ exception handling. 
llvm-svn: 132131
 2011-05-26 18:59:03 +00:00
Akira Hatanaka
5a8bd76f99 Set HasSetDirective to true. 
llvm-svn: 132127
 2011-05-26 18:16:18 +00:00
Akira Hatanaka
3f49cbeb37 Define WeakRefDirective. 
llvm-svn: 132098
 2011-05-25 23:30:30 +00:00
Akira Hatanaka
4806508364 Remove MipsTargetLowering::LowerFP_TO_SINT. Patterns for fp_to_sint have already 
been defined in MipsInstrFPU.td.

llvm-svn: 132076
 2011-05-25 20:08:05 +00:00
Akira Hatanaka
32b5043265 Custom-lower FCOPYSIGN nodes. 
llvm-svn: 132074
 2011-05-25 19:32:07 +00:00
Akira Hatanaka
ae2e2d557a Update MaxCallFrameSize regardless of the relocation model selected. 
llvm-svn: 132070
 2011-05-25 18:08:32 +00:00
Akira Hatanaka
953e0a3c45 Change initial value of MaxCallFrameSize. MipsFI::getMaxCallFrameSize() should 
return 0 if there are no function calls made. 

llvm-svn: 132065
 2011-05-25 17:52:48 +00:00
Akira Hatanaka
33415b8179 Coding style fixes. Added comments. 
llvm-svn: 132063
 2011-05-25 17:32:06 +00:00
Akira Hatanaka
a5b11ee449 Fix lowering of DYNAMIC_STACKALLOC nodes. 
llvm-svn: 132030
 2011-05-25 02:20:00 +00:00
Akira Hatanaka
161f211628 Enable printing of immediates that do not fit in 16-bit. .cprestore can have 
offsets that are larger than 0x10000.

llvm-svn: 132003
 2011-05-24 21:22:21 +00:00
Akira Hatanaka
f4c853e3e4 Implement byval structure argument passing. The following limitations or 
deficiencies exist:

- Works only if ABI is o32.
- Zero-sized structures cannot be passed.
- There is a lot of redundancy in generated code.

llvm-svn: 131986
 2011-05-24 19:18:33 +00:00
Akira Hatanaka
d0694fb652 Simplify offset calculation of stack frame objects for $gp restore location and 
variable arguments in LowerCall and LowerFormalArguments. This should also fix
the bug in which handling of variable arguments is incorrect when the front-end
optimizes away unused fixed arguments.

llvm-svn: 131942
 2011-05-24 00:23:52 +00:00
Akira Hatanaka
e2e584df0e Expand f64 FPOW. 
llvm-svn: 131928
 2011-05-23 22:23:58 +00:00
Akira Hatanaka
5b696387f7 Add pattern for double-to-integer conversion. Patch by Sasa Stankovic. 
llvm-svn: 131927
 2011-05-23 22:16:43 +00:00
Akira Hatanaka
daa4afec69 Fixes related to coding style. 
llvm-svn: 131922
 2011-05-23 21:13:59 +00:00
Akira Hatanaka
123ee4388c Fix MipsAsmPrinter::printSavedRegsBitmaskChange. Remove functions and variables 
in MipsFunctionInfo that are no longer used.

llvm-svn: 131917
 2011-05-23 20:34:30 +00:00
Akira Hatanaka
6ddbe02441 Change StackDirection from StackGrowsUp to StackGrowsDown. 
The following improvements are accomplished as a result of applying this patch:
- Fixed frame objects' offsets (relative to either the virtual frame pointer or
  the stack pointer) are set before instruction selection is completed. There is
  no need to wait until Prologue/Epilogue Insertion is run to set them.
- Calculation of final offsets of fixed frame objects is straightforward. It is
  no longer necessary to assign negative offsets to fixed objects for incoming
  arguments in order to distinguish them from the others.
- Since a fixed object has its relative offset set during instruction
  selection, there is no need to conservatively set its alignment to 4.
- It is no longer necessary to reorder non-fixed frame objects in 
  MipsFrameLowering::adjustMipsStackFrame.

llvm-svn: 131915
 2011-05-23 20:16:59 +00:00
Akira Hatanaka
af8143cdde Use the correct register to access stack frame objects. 
llvm-svn: 131785
 2011-05-21 03:01:03 +00:00
Akira Hatanaka
6605a1e1a6 Insert instructions that copy $sp to or from $fp at the right locations. 
llvm-svn: 131784
 2011-05-21 02:29:26 +00:00
Akira Hatanaka
66b7b0949f Change the order fixed objects are created in MipsTargetLowering::LowerCall in 
preparation for reversing StackDirection.

Fixed objects are created in the following order:  
 1. Incoming arguments passed on stack.
 2. va_arg objects (include both arguments that are passed in registers and
    pointer to the location of the first va_arg argument).
 3. $gp restore slot.
 4. Outgoing arguments passed on stack.
 5. Pointer to alloca'd space.

llvm-svn: 131767
 2011-05-20 23:22:14 +00:00
Akira Hatanaka
84f0431846 In CC_MipsO32, allocate a stack space regardless of whether the argument is 
passed in register or on the stack.

llvm-svn: 131758
 2011-05-20 21:39:54 +00:00
Akira Hatanaka
cc6174d5a5 Define functions that get/set maximum call frame size. 
llvm-svn: 131752
 2011-05-20 20:11:17 +00:00
Akira Hatanaka
89801a318c Make $fp and $ra callee-saved registers and let PrologEpilogInserter handle 
saving and restoring them.

llvm-svn: 131745
 2011-05-20 18:39:33 +00:00
Benjamin Kramer
63248bc95b Remove noisy semicolons. 
llvm-svn: 131724
 2011-05-20 09:20:25 +00:00
Akira Hatanaka
9736ffe863 Fix bug in which nodes that write to argument registers do not get glued with the JALR node. Patch by Sasa Stankovic 
llvm-svn: 131714
 2011-05-20 02:30:51 +00:00
Akira Hatanaka
bbb0805af2 Remove code that creates unnecessary frame objects. 
llvm-svn: 131711
 2011-05-20 01:45:06 +00:00
Akira Hatanaka
e96ba812ae Define variables and functions in MipsFunctionInfo. 
This is the first of a series of patches that attempt to simplify handling of 
stack frame objects. 

llvm-svn: 131710
 2011-05-20 01:17:58 +00:00
Akira Hatanaka
669a518bab Align i64 arguments to 64 bit boundaries. 
llvm-svn: 131668
 2011-05-19 20:29:48 +00:00
Akira Hatanaka
0ed99ae9e9 Increase number of available registers when target is MIPS32. 
llvm-svn: 131660
 2011-05-19 18:25:03 +00:00
Akira Hatanaka
adf693ba31 Simplify CC_MipsO32 and merge it with CC_MipsO32_VarArgs. Patch by Sasa Stankovic. 
llvm-svn: 131657
 2011-05-19 18:06:05 +00:00
Akira Hatanaka
fb42792a55 Fix data layout string. i64 is aligned to 64 bit boundaries. 
llvm-svn: 131642
 2011-05-19 17:21:09 +00:00
Akira Hatanaka
a57b77b65f Fix setting of isCommutable flag. 
llvm-svn: 131233
 2011-05-12 17:42:08 +00:00
Eric Christopher
49409b8534 Fix td file comments for Mips. 
Patch by Liu <proljc@gmail.com>!

llvm-svn: 131086
 2011-05-09 18:16:46 +00:00
Akira Hatanaka
fe1f642eb1 1. Keep lines in 80 columns. 
2. Remove unused function.
3. Correct indentation.

llvm-svn: 131028
 2011-05-06 22:11:29 +00:00
Eli Friedman
12e590e760 Make the logic for determining function alignment more explicit. No functionality change. 
llvm-svn: 131012
 2011-05-06 20:34:06 +00:00
Rafael Espindola
9e59931156 Fix cmake build. 
llvm-svn: 130850
 2011-05-04 18:46:56 +00:00
Akira Hatanaka
e9a2d2a78f Prevent instructions using $gp from being placed between a jalr and the instruction that restores the clobbered $gp. 
llvm-svn: 130847
 2011-05-04 17:54:27 +00:00
Akira Hatanaka
5a2b3f0120 Fix function MipsRegisterInfo::getRegisterNumbering. 
llvm-svn: 130774
 2011-05-03 18:41:54 +00:00
Akira Hatanaka
59b356bcc3 Lower BlockAddress node when relocation-model is static. 
llvm-svn: 130131
 2011-04-25 17:10:45 +00:00
Duncan Sands
e4e802432c Fix comment typo. Noticed by Liu. 
llvm-svn: 130120
 2011-04-25 06:21:43 +00:00
Akira Hatanaka
74d45b54f1 Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. 
llvm-svn: 129612
 2011-04-15 21:51:11 +00:00
Akira Hatanaka
d4fd6b478e Fix lines that exceed 80 columns. There is no change in functionality. 
llvm-svn: 129608
 2011-04-15 21:06:38 +00:00
Akira Hatanaka
6f900185ed Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality. 
llvm-svn: 129606
 2011-04-15 21:00:26 +00:00
Rafael Espindola
4daf38357c Fix cmake build. 
llvm-svn: 129601
 2011-04-15 20:34:45 +00:00
Akira Hatanaka
025720d06f Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions. 
llvm-svn: 129594
 2011-04-15 19:52:08 +00:00
Chris Lattner
0304b82f80 Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!

llvm-svn: 129558
 2011-04-15 05:18:47 +00:00
Akira Hatanaka
dcc8678bd5 Fix indentation. 
llvm-svn: 129105
 2011-04-07 20:25:10 +00:00
Akira Hatanaka
b8304b2c15 Update ATUsed every time after expandRegLargeImmPair is called. 
llvm-svn: 129104
 2011-04-07 20:23:26 +00:00
Akira Hatanaka
24e15bbe94 Fix handling of functions with internal linkage. 
llvm-svn: 129099
 2011-04-07 19:51:44 +00:00
Akira Hatanaka
54ae678397 Move transformation of JmpLink and related nodes done during instruction selection to Legalize phase. 
llvm-svn: 128830
 2011-04-04 17:11:07 +00:00
Akira Hatanaka
9a001f303e Undo changes mistakenly made in revision 128750. 
llvm-svn: 128751
 2011-04-02 00:26:12 +00:00
Akira Hatanaka
6b700f35aa Insert space before ';' to prevent warnings. 
llvm-svn: 128750
 2011-04-02 00:15:58 +00:00
Akira Hatanaka
9f4b4d2dc1 Remove redundant code. There are assignments to variables Base and Offset right after the code that is removed. 
llvm-svn: 128742
 2011-04-01 21:56:02 +00:00
Akira Hatanaka
9257b524eb Simplifies logic for printing target flags. 
llvm-svn: 128741
 2011-04-01 21:41:06 +00:00
Akira Hatanaka
0b476a8e81 Modifies MipsAsmPrinter::isBlockOnlyReachableByFallthrough so that it handles delay slots correctly. 
llvm-svn: 128724
 2011-04-01 18:57:38 +00:00
Akira Hatanaka
c2d74b05ca Add code for analyzing FP branches. Clean up branch Analysis functions. 
llvm-svn: 128718
 2011-04-01 17:39:08 +00:00
Akira Hatanaka
b26c89ee68 Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. 
llvm-svn: 128650
 2011-03-31 18:26:17 +00:00
Akira Hatanaka
c7724b4167 fixed typo 
llvm-svn: 128574
 2011-03-30 21:15:35 +00:00
Chris Lattner
2cd24b852f silence a conditional assignment -Wuninitialized warning. 
llvm-svn: 127453
 2011-03-11 02:12:51 +00:00
Bruno Cardoso Lopes
88bef593d8 Improve varags handling, with testcases. Patch by Sasa Stankovic 
llvm-svn: 127349
 2011-03-09 19:22:22 +00:00
Bill Wendling
73b20a325f Initialize variable. 
llvm-svn: 127038
 2011-03-04 21:38:47 +00:00
Bruno Cardoso Lopes
52c64a2eb3 Improve div/rem node handling on mips. Patch by Akira Hatanaka 
llvm-svn: 127034
 2011-03-04 21:03:24 +00:00
Bruno Cardoso Lopes
e697a8bcb0 Expands register/immediate pairs when the immediate is too large to fit in 16-bit field. Patch by Akira Hatanaka 
llvm-svn: 127032
 2011-03-04 20:48:08 +00:00
Bruno Cardoso Lopes
0545e7fe48 Rewrite and simplify o32 vaarg passing, no functional changes. Patch by Sasa Stankovic 
llvm-svn: 127029
 2011-03-04 20:27:44 +00:00
Bruno Cardoso Lopes
99619e5bef Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka 
llvm-svn: 127027
 2011-03-04 20:01:52 +00:00
Bruno Cardoso Lopes
5347fd6512 Fix an old copy-n-paste 
llvm-svn: 127020
 2011-03-04 19:20:24 +00:00
Bruno Cardoso Lopes
9390dc6271 Expands FCOS and FSIN nodes when type is f64. 
llvm-svn: 127017
 2011-03-04 18:54:14 +00:00
Bruno Cardoso Lopes
a49a596acf Fixes addc pattern when immediate cannot be represented with 16-bit. Patch by Akira Hatanaka 
llvm-svn: 127005
 2011-03-04 17:59:18 +00:00
Bruno Cardoso Lopes
5400401372 Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira 
llvm-svn: 127003
 2011-03-04 17:51:39 +00:00
Oscar Fuentes
59c8ae34f7 Use explicit add_subdirectory's for LLVM target sublibraries instead 
of testing for its presence at cmake time.

This way the build automatically regenerates the makefiles when a svn
update brings in a new sublibrary.

llvm-svn: 126068
 2011-02-20 02:55:27 +00:00
Bruno Cardoso Lopes
7cc40009a8 Fix a lot of o32 CC issues and add a bunch of tests. Patch by Akira Hatanaka with some small modifications by me. 
llvm-svn: 125292
 2011-02-10 18:05:10 +00:00
Rafael Espindola
492ad6ca06 Remove more duplicated code. 
llvm-svn: 124056
 2011-01-23 04:43:11 +00:00
Rafael Espindola
59c1246cee Remove duplicated code. 
llvm-svn: 124054
 2011-01-23 04:28:49 +00:00
Bruno Cardoso Lopes
13cefe452d Ensure Mips::GP is properly reloaded after a function call. Patch by Sasa Stankovic 
llvm-svn: 123768
 2011-01-18 19:50:18 +00:00
Bruno Cardoso Lopes
2d509b8b40 Negative zero is not legal on mips. Patch by Sasa Stankovic 
llvm-svn: 123766
 2011-01-18 19:41:41 +00:00
Bruno Cardoso Lopes
542853bcd7 Handle (i32,i32) => f64 in a cleaner way. Patch by Sasa Stankovic 
llvm-svn: 123763
 2011-01-18 19:38:25 +00:00
Bruno Cardoso Lopes
6c5db0236a Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka 
llvm-svn: 123760
 2011-01-18 19:29:17 +00:00
Jakob Stoklund Olesen
0f2b9d9dc4 Teach frame lowering to ignore debug values after the terminators. 
llvm-svn: 123399
 2011-01-13 21:28:52 +00:00
Anton Korobeynikov
abd9a868df Update CMake stuff 
llvm-svn: 123171
 2011-01-10 12:39:23 +00:00
Anton Korobeynikov
cf5967630b Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. 
llvm-svn: 123170
 2011-01-10 12:39:04 +00:00
Chris Lattner
01e8c46349 Flag -> Glue, the ongoing saga 
llvm-svn: 122513
 2010-12-23 18:28:41 +00:00
Jeffrey Yasskin
a199652a3e Change all self assignments X=X to (void)X, so that we can turn on a 
new gcc warning that complains on self-assignments and
self-initializations.

llvm-svn: 122458
 2010-12-23 00:58:24 +00:00
Chris Lattner
65c5243bd6 rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for 
something that just glues two nodes together, even if it is
sometimes used for flags.

llvm-svn: 122310
 2010-12-21 02:38:05 +00:00
Bruno Cardoso Lopes
93e5c2fb64 Add ROTR and ROTRV mips32 instructions. Patch by Akira Hatanaka 
llvm-svn: 121377
 2010-12-09 17:32:30 +00:00
Bruno Cardoso Lopes
0f5478218e Fix delay slot filler for non mips1 targets. Patch by Akira Hatanaka 
llvm-svn: 121376
 2010-12-09 17:31:11 +00:00
Bruno Cardoso Lopes
e11d870459 Remove target specific node MipsISD::CMov, which is not used because all conditional moves are directly matched using tablegen patterns. If there's a need in the future, we can introduce it again 
llvm-svn: 121164
 2010-12-07 19:04:14 +00:00
Bruno Cardoso Lopes
0e14644599 Match a pattern generated by a dag combiner opt where: 
(select (load (load tga0)) (load tga1)) => (load (select (load tga0) tga1))

Thanks to Akira for pointing that.

llvm-svn: 121163
 2010-12-07 19:00:20 +00:00
Wesley Peck
d589353ad0 Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. 
llvm-svn: 119990
 2010-11-23 03:31:01 +00:00
Anton Korobeynikov
269e7d3be1 Move hasFP() and few related hooks to TargetFrameInfo. 
llvm-svn: 119740
 2010-11-18 21:19:35 +00:00
Anton Korobeynikov
794259aec0 Attempt to unbreak cmake-based builds 
llvm-svn: 119098
 2010-11-15 00:48:12 +00:00
Anton Korobeynikov
76c52dcf44 First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place 
llvm-svn: 119097
 2010-11-15 00:06:54 +00:00
Chris Lattner
cec3b226a4 move all the target's asmprinters into the main target. The piece 
that should be split out is the InstPrinter (if a target is mc'ized).
This change makes all the targets be consistent.

llvm-svn: 119056
 2010-11-14 18:43:56 +00:00
Bruno Cardoso Lopes
37f2439cbd Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com> 
llvm-svn: 118864
 2010-11-12 00:38:32 +00:00
Bruno Cardoso Lopes
2266e58196 Add clo instruction. Patch by Akira Hatanaka (ahatanaka@mips.com) with some minor tweaks 
llvm-svn: 118667
 2010-11-10 02:13:22 +00:00
Bruno Cardoso Lopes
81f7b26109 Fix trailing whitespace and style, no functionality change 
llvm-svn: 118515
 2010-11-09 17:25:34 +00:00
Bruno Cardoso Lopes
64dd957550 Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka (ahatanaka@mips.com) 
llvm-svn: 118447
 2010-11-08 21:42:32 +00:00
Duncan Sands
3bf2a701a5 In the calling convention logic, ValVT is always a legal type, 
and as such can be represented by an MVT - the more complicated
EVT is not needed.  Use MVT for ValVT everywhere.

llvm-svn: 118245
 2010-11-04 10:49:57 +00:00
Duncan Sands
f6e5e02c9b Inside the calling convention logic LocVT is always a simple 
value type, so there is no point in passing it around using
an EVT.  Use the simpler MVT everywhere.  Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.

llvm-svn: 118167
 2010-11-03 11:35:31 +00:00
John Thompson
6115a7f1d4 Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. 
llvm-svn: 117667
 2010-10-29 17:29:13 +00:00
Evan Cheng
39c462b4f1 Add support to model pipeline bypass / forwarding. 
llvm-svn: 115005
 2010-09-28 23:50:49 +00:00
Oscar Fuentes
eb27a44982 Removed a bunch of unnecessary target_link_libraries. 
llvm-svn: 114999
 2010-09-28 22:39:14 +00:00
Che-Liang Chiou
cf3ce50cc0 Remove trailing spaces of MipsMachineFunction.h 
llvm-svn: 114948
 2010-09-28 10:06:53 +00:00
Che-Liang Chiou
6a72cc8a38 Remove trailing spaces of MipsTargetObjectFile.cpp 
llvm-svn: 114947
 2010-09-28 09:55:24 +00:00
Chris Lattner
55043ef46a fix a long standing wart: all the ComplexPattern's were being 
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel 
like detangling).   Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.

llvm-svn: 114471
 2010-09-21 20:31:19 +00:00
Chris Lattner
5f584efd31 eliminate some uses of the getStore overload. 
llvm-svn: 114453
 2010-09-21 17:50:43 +00:00
Chris Lattner
4320dda4fb convert the targets off the non-MachinePointerInfo of getLoad. 
llvm-svn: 114410
 2010-09-21 06:44:06 +00:00
Jakob Stoklund Olesen
44d7693fdc Remove Predicate_* calls from Mips 
llvm-svn: 112919
 2010-09-03 00:35:13 +00:00
Jim Grosbach
2b81a07dc7 Simplify eliminateFrameIndex() interface back down now that PEI doesn't need 
to try to re-use scavenged frame index reference registers. rdar://8277890

llvm-svn: 112241
 2010-08-26 23:32:16 +00:00
Jakob Stoklund Olesen
f2b0bcb397 Don't call Predicate_* in Mips. 
llvm-svn: 111468
 2010-08-18 23:56:46 +00:00
Chris Lattner
a556264e06 fix emacs language spec's, patch by Edmund Grimley-Evans! 
llvm-svn: 111241
 2010-08-17 16:20:04 +00:00
Owen Anderson
f2fea95f2f Reapply r110396, with fixes to appease the Linux buildbot gods. 
llvm-svn: 110460
 2010-08-06 18:33:48 +00:00
Owen Anderson
aadd8a89ca Revert r110396 to fix buildbots. 
llvm-svn: 110410
 2010-08-06 00:23:35 +00:00
Owen Anderson
b9762c07cb Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static 
ID member as the sole unique type identifier.  Clean up APIs related to this change.

llvm-svn: 110396
 2010-08-05 23:42:04 +00:00
Bruno Cardoso Lopes
0fa595f073 Fix PR7174, a couple o Mips fixes: 
- Fix a typo for PIC check during jmp table lowering
- Also fix the "first jump table basic block is not
considered only reachable by fall through" problem, use this
ad-hoc solution until I come up with something better.

Patch by stetorvs@gmail.com

llvm-svn: 108820
 2010-07-20 08:37:04 +00:00
Bruno Cardoso Lopes
b127fa9a01 Fix Mips PR7473. Patch by stetorvs@gmail.com 
llvm-svn: 108816
 2010-07-20 07:58:51 +00:00
Jakob Stoklund Olesen
44949b2e1b Remove the isMoveInstr() hook. 
llvm-svn: 108567
 2010-07-16 22:35:46 +00:00
Benjamin Kramer
da3e6cdb26 Don't pass StringRef by reference. 
llvm-svn: 108366
 2010-07-14 22:38:02 +00:00
Jakob Stoklund Olesen
7af3eff94d RISC architectures get their memory operand folding for free. 
The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.

llvm-svn: 108099
 2010-07-11 19:19:13 +00:00
Jakob Stoklund Olesen
c1aca7464d Replace copyRegToReg with copyPhysReg for Mips. 
llvm-svn: 108066
 2010-07-11 01:08:31 +00:00
Jakob Stoklund Olesen
b1c6191d3b Use COPY in targets 
llvm-svn: 108063
 2010-07-10 22:43:03 +00:00
Dan Gohman
c768525273 Split the SDValue out of OutputArg so that SelectionDAG-independent 
code can do calling-convention queries. This obviates OutputArgReg.

llvm-svn: 107786
 2010-07-07 15:54:55 +00:00
Devang Patel
7ab104353b Propagate debug loc. 
llvm-svn: 107710
 2010-07-06 22:08:15 +00:00
Dan Gohman
808f334f79 Reapply r107655 with fixes; insert the pseudo instruction into 
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.

llvm-svn: 107691
 2010-07-06 20:24:04 +00:00
Dan Gohman
4d264f7e51 Revert r107655. 
llvm-svn: 107668
 2010-07-06 15:49:48 +00:00
Dan Gohman
6a73079aba Fix a bunch of custom-inserter functions to handle the case where 
the pseudo instruction is not at the end of the block.

llvm-svn: 107655
 2010-07-06 15:18:19 +00:00
Evan Cheng
47f3a2db40 Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false. 
llvm-svn: 107550
 2010-07-03 00:40:23 +00:00
Eric Christopher
caf8285bff Remove isTwoAddress from Mips. 
llvm-svn: 106465
 2010-06-21 20:19:21 +00:00
Stuart Hastings
bd7194d21c Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This 
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.

llvm-svn: 106243
 2010-06-17 22:43:56 +00:00
Rafael Espindola
f7170870cf Remove the TargetRegisterClass member from CalleeSavedInfo 
llvm-svn: 105344
 2010-06-02 20:02:30 +00:00
Rafael Espindola
9113809536 cleanup 
llvm-svn: 105322
 2010-06-02 13:53:17 +00:00
Jakob Stoklund Olesen
83d2cfd6cd Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104704
 2010-05-26 17:27:12 +00:00
Jakob Stoklund Olesen
0fefdf4d2a Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism." 
This reverts commit 104654.

llvm-svn: 104660
 2010-05-26 01:21:14 +00:00
Jakob Stoklund Olesen
a2f0c34e41 Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104654
 2010-05-26 00:28:19 +00:00
Jakob Stoklund Olesen
696fbed514 Remove NumberHack entirely. 
SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.

llvm-svn: 104627
 2010-05-25 19:49:33 +00:00
Jakob Stoklund Olesen
d1f4d14609 Switch SubRegSet to using symbolic SubRegIndices 
llvm-svn: 104571
 2010-05-24 23:03:18 +00:00
Jakob Stoklund Olesen
3a19b732d8 Replace the tablegen RegisterClass field SubRegClassList with an alist-like data 
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

llvm-svn: 104563
 2010-05-24 21:46:58 +00:00
Jakob Stoklund Olesen
7c5127a0c6 SubRegIndex'ize Mips 
llvm-svn: 104514
 2010-05-24 17:42:58 +00:00
Bill Wendling
e346a38ed4 Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what 
the variable actually tracks.

N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.

llvm-svn: 103802
 2010-05-14 21:14:32 +00:00
Dan Gohman
fb6f4da0e0 Implement a bunch more TargetSelectionDAGInfo infrastructure. 
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.

llvm-svn: 103481
 2010-05-11 17:31:57 +00:00
Dan Gohman
497e752655 Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 
doesn't have to guess.

llvm-svn: 103194
 2010-05-06 20:33:48 +00:00
Evan Cheng
80f3051bb7 Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. 
llvm-svn: 103193
 2010-05-06 19:06:44 +00:00
Dan Gohman
87a1315fce No-ops emitted for scheduling don't correspond with anything in the 
user's source, so don't arbitrarily assign them a debug location.

llvm-svn: 103121
 2010-05-05 20:58:01 +00:00
Chris Lattner
1452a149f0 fix some inconsistent line endings, patch by Jakub Staszak! 
llvm-svn: 102852
 2010-05-01 17:36:49 +00:00
Dan Gohman
68f04d06c8 Get rid of the EdgeMapping map. Instead, just check for BasicBlock 
changes before doing phi lowering for switches.

llvm-svn: 102809
 2010-05-01 00:01:06 +00:00
Devang Patel
00f63442db Use MachineOperand::is* predicates. 
llvm-svn: 102472
 2010-04-27 22:24:37 +00:00