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1376 Commits

Author SHA1 Message Date
Dan Gohman
5a693288f6 Fix this test so it actually runs the grep lines. 
llvm-svn: 57653
 2008-10-16 23:57:54 +00:00
Duncan Sands
10e931facf Testcase for PR2762. 
llvm-svn: 57633
 2008-10-16 08:56:46 +00:00
Bill Wendling
8d26b9c07a Testcase for PR1638. 
llvm-svn: 57590
 2008-10-15 18:27:15 +00:00
Evan Cheng
cb8b4e9dd4 - Add target lowering hooks that specify which setcc conditions are illegal, 
i.e. conditions that cannot be checked with a single instruction. For example,
SETONE and SETUEQ on x86.
- Teach legalizer to implement *illegal* setcc as a and / or of a number of
legal setcc nodes. For now, only implement FP conditions. e.g. SETONE is
implemented as SETO & SETNE, SETUEQ is SETUO | SETEQ.
- Move x86 target over.

llvm-svn: 57542
 2008-10-15 02:05:31 +00:00
Dan Gohman
e08e0dcfcc When doing the very-late shift-and address-mode optimization, 
create a new DAG node to represent the new shift to keep the
DAG consistent, even though it'll almost always be folded into
the address.

If a user of the resulting address has multiple uses, the
nodes may get revisited by a later MatchAddress call, in which
case DAG inconsistencies do matter.

This fixes PR2849.

llvm-svn: 57465
 2008-10-13 20:52:04 +00:00
Evan Cheng
de99d94c58 FIX PR2794. Make sure SIGN_EXTEND_INREG nodes introduced by LegalizeSetCCOperands are leglized. Patch by Richard Pennington. 
llvm-svn: 57460
 2008-10-13 18:46:18 +00:00
Evan Cheng
731f400eac Also update sub-register intervals after a trivial computation is rematt'ed for a copy instruction. PR2775. 
llvm-svn: 57458
 2008-10-13 18:35:52 +00:00
Evan Cheng
023b124109 Add a test case for _Complex passed as a FCA. 
llvm-svn: 57456
 2008-10-13 18:13:07 +00:00
Chris Lattner
7910d59d44 Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as 
parameters instead of raw Constants.  This prevents the constants from
being selected by the isel pass, fixing PR2735.

llvm-svn: 57385
 2008-10-11 22:08:30 +00:00
Anton Korobeynikov
72e9aa27f0 Add testcase for 'r' inline asm operand 
llvm-svn: 57361
 2008-10-10 20:28:59 +00:00
Anton Korobeynikov
3f74df506c This does not fail anymore 
llvm-svn: 57360
 2008-10-10 20:28:32 +00:00
Anton Korobeynikov
40b8d5fc4d Add sparc test for memory operand used in inline asm 
llvm-svn: 57348
 2008-10-10 10:15:33 +00:00
Anton Korobeynikov
1134867d55 This is not failing anymore 
llvm-svn: 57347
 2008-10-10 10:15:18 +00:00
Chris Lattner
284ae75537 get CodeGen/Alpha/mul128.ll to work. 
llvm-svn: 57318
 2008-10-09 04:50:56 +00:00
Dan Gohman
08e60cee90 Remove -disable-fast-isel. Use cl::boolOrDefault with -fast-isel 
instead.

So now: -fast-isel or -fast-isel=true enable fast-isel, and
-fast-isel=false disables it. Fast-isel is also on by default
with -fast, and off by default otherwise.

llvm-svn: 57270
 2008-10-07 23:00:56 +00:00
Dan Gohman
bc47391399 Add a testcase for i256 add. i256 isn't fully supported in 
codegen right now, but add and subtract work.

llvm-svn: 57260
 2008-10-07 20:39:12 +00:00
Andrew Lenharth
dccb47de69 128 mul test, xfailed 
llvm-svn: 57250
 2008-10-07 17:13:32 +00:00
Anders Carlsson
a9c42526f8 Certain patterns involving the "movss" instruction were marked as requiring SSE2, when in reality movss is an SSE1 instruction. 
llvm-svn: 57246
 2008-10-07 16:14:11 +00:00
Andrew Lenharth
c00c2a0058 Expand arith on machines without carry flags 
llvm-svn: 57243
 2008-10-07 14:15:42 +00:00
Chris Lattner
75c684100c no need to write the output to the disk 
llvm-svn: 57232
 2008-10-07 04:06:55 +00:00
Andrew Lenharth
99c106c2a2 Add test case for ADDC ADDE expansion 
llvm-svn: 57228
 2008-10-07 02:30:13 +00:00
Dale Johannesen
40d00c0979 Be more precise about which conversions of NaNs 
are Inexact.  (These are not Inexact as defined
by IEEE754, but that seems like a reasonable way
to abstract what happens:  information is lost.)

llvm-svn: 57218
 2008-10-06 22:59:10 +00:00
Evan Cheng
88d76ffe8a Fix PR2850 and PR2863. Only generate movddup for 128-bit SSE vector shuffles. 
llvm-svn: 57210
 2008-10-06 21:13:08 +00:00
Anton Korobeynikov
4cc9051fbb Revert r56675 - it breaks unwinding runtime everywhere. 
llvm-svn: 57048
 2008-10-04 11:09:36 +00:00
Dan Gohman
638a8001c8 Fix a bug in the local allocator's liveness computation where it 
was setting kill flags on tied uses in two-address instructions.
The kill flags were causing the allocator to think it could
allocate the use and its tied def in different registers.

llvm-svn: 57039
 2008-10-04 00:31:14 +00:00
Dale Johannesen
dbd7b1bd33 Handle some 64-bit atomics on x86-32, some of the time. 
llvm-svn: 56963
 2008-10-02 18:53:47 +00:00
Dan Gohman
c48242640d Fix a think-o in isSafeToMove. This fixes it from thinking that 
volatile memory references are safe to move.

llvm-svn: 56948
 2008-10-02 15:04:30 +00:00
Dan Gohman
595edc380a Disable fast-isel for this test, as it doesn't emit the same 
number of instructions.

llvm-svn: 56940
 2008-10-01 23:48:35 +00:00
Devang Patel
a5cda569d3 Remove OptimizeForSize global. Use function attribute optsize. 
llvm-svn: 56937
 2008-10-01 23:18:38 +00:00
Dan Gohman
be88cf29b6 Split this test and move it into target-specific directories. 
This fixes failures on configurations that don't have one or the
other targets enabled.

llvm-svn: 56926
 2008-10-01 19:46:30 +00:00
Dan Gohman
5508abb3bf nounwind-ify this test. 
llvm-svn: 56918
 2008-10-01 15:07:14 +00:00
Bill Wendling
c807050f44 Moved this option to the front-end. 
llvm-svn: 56901
 2008-10-01 01:02:18 +00:00
Dan Gohman
d456cc01eb Use explicit target-triples to unbreak this test on non-darwin systems. 
llvm-svn: 56896
 2008-10-01 00:25:38 +00:00
Bill Wendling
618d422cdd Just don't transform this memset into "bzero" if no-builtin is specified. 
llvm-svn: 56888
 2008-09-30 22:05:33 +00:00
Bill Wendling
86f6fdc7e3 - Initialize "--no-builtin" to "false". 
- Testcase for r56885.

llvm-svn: 56886
 2008-09-30 21:40:30 +00:00
Evan Cheng
1c8ff02eeb Re-apply 56835 along with header file changes. 
llvm-svn: 56848
 2008-09-30 15:44:16 +00:00
Duncan Sands
a2c8482495 Revert commit 56835 since it breaks the build. 
"If a re-materializable instruction has a register
operand, the spiller will change the register operand's
spill weight to HUGE_VAL to avoid it being spilled.
However, if the operand is already in the queue ready
to be spilled, avoid re-materializing it".

llvm-svn: 56837
 2008-09-30 10:00:30 +00:00
Evan Cheng
4eee17f4fb If a re-materializable instruction has a register operand, the spiller will change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it. 
llvm-svn: 56835
 2008-09-30 06:36:58 +00:00
Evan Cheng
b749199c34 Fix PR2835. Do not change the width of a volatile load. 
llvm-svn: 56792
 2008-09-29 17:26:18 +00:00
Evan Cheng
28d9b3a8ad Re-apply 56683 with fixes. 
llvm-svn: 56748
 2008-09-27 01:56:22 +00:00
Devang Patel
47a504c87c Implement function notes as function attributes. 
llvm-svn: 56716
 2008-09-26 23:51:19 +00:00
Evan Cheng
d63fc80c1e Implement "punpckldq %xmm0, $xmm0" as "pshufd $0x50, %xmm0, %xmm" unless optimizing for code size. 
llvm-svn: 56711
 2008-09-26 23:41:32 +00:00
Bill Wendling
7273078850 Temporarily reverting r56683. This is causing a failure during the build of llvm-gcc: 
/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2  -O2 -g -O2  -DIN_GCC    -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition  -isystem ./include  -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED  -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include  -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311.
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
{standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
{standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression
{standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
...

llvm-svn: 56703
 2008-09-26 22:10:44 +00:00
Evan Cheng
9946443460 Fix @llvm.frameaddress codegen. FP elimination optimization should be disabled when frame address is desired. Also add support for depth > 0. 
llvm-svn: 56683
 2008-09-26 19:48:35 +00:00
Evan Cheng
b4d6625c85 Avoid spilling EBP / RBP twice in the prologue. 
llvm-svn: 56675
 2008-09-26 19:14:21 +00:00
Evan Cheng
c8674dcfd0 Prefer movlhps over punpcklqdq, etc. in more cases. 
llvm-svn: 56627
 2008-09-25 23:35:16 +00:00
Evan Cheng
d190aeb62d With sse3 and when the source is a load or has multiple uses, favors movddup over shuffp*, pshufd, etc. Without sse3 or when the source is from a register, make use of movlhps 
llvm-svn: 56620
 2008-09-25 20:50:48 +00:00
Dale Johannesen
62f64ab4c8 Accept 'inreg' attribute on x86 functions as 
meaning sse_regparm (i.e. float/double values go
in XMM0 instead of ST0).  Update documentation
to reflect reality.

llvm-svn: 56619
 2008-09-25 20:47:45 +00:00
Evan Cheng
efd1f614ff Fix patterns for SSE4.1 move and sign extend instructions. Also add instructions which fold VZEXT_MOVL and VZEXT_LOAD. 
llvm-svn: 56594
 2008-09-24 23:27:55 +00:00
Dale Johannesen
4184c23365 Remove SelectionDag early allocation of registers 
for earlyclobbers.  Teach Local RA about earlyclobber,
and add some tests for it.

llvm-svn: 56592
 2008-09-24 23:13:09 +00:00
Evan Cheng
f942615847 Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc. 
llvm-svn: 56526
 2008-09-24 00:05:32 +00:00
Evan Cheng
5bf702d20a Support x86 specific inline asm modifier 'J'. 
llvm-svn: 56483
 2008-09-22 23:57:37 +00:00
Arnold Schwaighofer
49f49e2086 Change the calling convention used when tail call optimization is enabled from CC_X86_32_TailCall to CC_X86_32_FastCC. 
llvm-svn: 56436
 2008-09-22 14:50:07 +00:00
Evan Cheng
270178bdda Fix PR2808. When regalloc runs out of register, it spill a physical register around the live interval being allocated. Do not continue to try to spill another register, just grab the physical register and move on. 
llvm-svn: 56381
 2008-09-20 01:28:05 +00:00
Evan Cheng
c01e6c2f59 Clean up the test. 
llvm-svn: 56380
 2008-09-20 01:26:27 +00:00
Evan Cheng
6a86ec1ef0 No need to print function stubs for Mac OS X 10.5 and up. Linker will handle it. 
llvm-svn: 56378
 2008-09-20 00:13:45 +00:00
Dan Gohman
f66b3277d3 Refactor X86SelectConstAddr, folding it into X86SelectAddress. This 
results in better code for globals. Also, unbreak the local CSE for
GlobalValue stub loads.

llvm-svn: 56371
 2008-09-19 22:16:54 +00:00
Evan Cheng
14493ffe78 Re-materalized definition instructions may be dead. Whack them. 
llvm-svn: 56352
 2008-09-19 17:38:47 +00:00
Dale Johannesen
99091ed94f Add a bit to mark operands of asm's that conflict 
with an earlyclobber operand elsewhere.  Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way 
that conflicts with an earlyclobber.  See also comments.

llvm-svn: 56290
 2008-09-17 21:13:11 +00:00
Evan Cheng
d3225118a6 Unallocatable registers do not have live intervals. 
llvm-svn: 56287
 2008-09-17 18:36:25 +00:00
Bill Wendling
b2701e541c Add trampoline support to PPC. GCC simply calls the "__trampoline_setup" 
function with appropriate parameters. This allows us to support blocks on PPC.

llvm-svn: 56267
 2008-09-17 00:30:57 +00:00
Dan Gohman
faa15214e0 Teach LSR to optimize away SMAX operations for tripcounts in common 
cases.  See the comment above OptimizeSMax for the full story, and
the testcase for an example. This cancels out a pessimization
commonly attributed to indvars, and will allow us to lift some of
the artificial throttles in indvars, rather than add new ones.

llvm-svn: 56230
 2008-09-15 21:22:06 +00:00
Dan Gohman
f38d63884f Re-enable SelectionDAG CSE for calls. It matters in the case of 
libcalls, as in this testcase on ARM.

llvm-svn: 56226
 2008-09-15 19:46:03 +00:00
Bruno Cardoso Lopes
5463c59693 Added testcase for bswap allegrexel intrinsic 
llvm-svn: 56225
 2008-09-15 19:38:11 +00:00
Evan Cheng
db1693cb14 Correctly update kill infos after extending a live range and merge 2 val#'s; fix 56165 - do not mark val# copy field if the copy does not define the val#. 
llvm-svn: 56199
 2008-09-15 06:28:41 +00:00
Evan Cheng
07046dae41 On some targets, non-move instructions can become move instructions because of coalescing. e.g. 
vr2 = OR vr0, vr1
=>
vr2 = OR vr1, vr1   // after coalescing vr0 with vr1

Update the value# of the destination register with the copy instruction if that happens.

llvm-svn: 56165
 2008-09-12 18:13:14 +00:00
Arnold Schwaighofer
9cfcc68e04 Add indirect tail call (function pointer) examples. 
llvm-svn: 56127
 2008-09-11 22:24:28 +00:00
Arnold Schwaighofer
adfb111f10 When tailcallopt is enabled all fastcc calls must have an aligned argument stack size. Add a test case. 
llvm-svn: 56119
 2008-09-11 20:28:43 +00:00
Evan Cheng
5c7e3783ef Fix PR2748. Avoid coalescing physical register with virtual register which would create illegal extract_subreg. e.g. 
vr1024 = extract_subreg vr1025, 1
...
vr1024 = mov8rr AH
If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH.

llvm-svn: 56118
 2008-09-11 20:07:10 +00:00
Evan Cheng
99be914c9a Fix PR2783 - coalescer bug. Missing a TargetRegisterInfo::isVirtualRegister check. 
llvm-svn: 56112
 2008-09-11 18:40:32 +00:00
Evan Cheng
b879f93ba5 Propagate subreg index when promoting a load to a copy. 
llvm-svn: 56085
 2008-09-11 01:02:12 +00:00
Evan Cheng
83c694fbe7 Fix a fastcc + sret bug. If fastcc and sret, callee doesn't need to pop the hidden struct ptr; Re-enable fastcc. 
llvm-svn: 56061
 2008-09-10 18:25:29 +00:00
Evan Cheng
ba11945234 Legalizer was missing code that expand fpow to a libcall. 
llvm-svn: 56028
 2008-09-09 23:02:14 +00:00
Evan Cheng
304fba81c9 Fix PR2757. Ignore liveinterval register allocation preference if the preference register is not in the right register class. This can happen due to sub-register coalescing. 
llvm-svn: 56006
 2008-09-09 20:22:01 +00:00
Evan Cheng
dc011a1b10 Fix a constant lowering bug. Now we can do load and store instructions with funky getelementptr embedded in the address operand. 
llvm-svn: 55975
 2008-09-09 01:26:59 +00:00
Anton Korobeynikov
afd49daa42 Reapply 55902: Add test for checking proper lowering of eh_return & unwind init intrinsics on 32bit x86 targets 
llvm-svn: 55960
 2008-09-08 21:14:36 +00:00
Anton Korobeynikov
ddf0f04445 Reapply 55903: Testcase for 64-bit lowering of eh_return & unwind_init 
llvm-svn: 55959
 2008-09-08 21:14:19 +00:00
Dan Gohman
6f360fc081 Add a target triple; apparently LLVM doesn't use 64-bit 
data directives on darwin.

llvm-svn: 55941
 2008-09-08 20:16:18 +00:00
Bill Wendling
122df59fda Remove these testcases associated with changes between r 55898 and r 55909. 
llvm-svn: 55931
 2008-09-08 18:00:39 +00:00
Bill Wendling
4cc4caab72 Reverting r55898 to r55909. One of these patches was causing an ICE during the full bootstrap on Darwin: 
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2  -O2 -g -O2  -DIN_GCC    -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include  -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED  -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_negdi2 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_negdi2_s.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) &&
TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical
register live information"), function runOnMachineFunction, file
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp,
line 311.
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2  -O2 -g -O2  -DIN_GCC    -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include  -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED  -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_lshrdi3 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_lshrdi3_s.o
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
{standard input}:unknown:Undefined local symbol LBB21_11
{standard input}:unknown:Undefined local symbol LBB21_12
{standard input}:unknown:Undefined local symbol LBB21_13
{standard input}:unknown:Undefined local symbol LBB21_8

llvm-svn: 55928
 2008-09-08 17:59:12 +00:00
Evan Cheng
fc78ac5bbe Handle calls which produce i1 results: promote to i8 but and it with 1 to get the low bit. 
llvm-svn: 55925
 2008-09-08 17:15:42 +00:00
Dan Gohman
f2a912c2a7 Add AsmPrinter support for i128 and larger static initializer data. 
llvm-svn: 55919
 2008-09-08 16:40:13 +00:00
Anton Korobeynikov
0da56882db Testcase for 64-bit lowering of eh_return & unwind_init 
llvm-svn: 55903
 2008-09-08 14:23:16 +00:00
Anton Korobeynikov
7dc16250e7 Add test for checking proper lowering of eh_return & unwind init intrinsics on 32bit x86 targets 
llvm-svn: 55902
 2008-09-08 14:22:57 +00:00
Rafael Espindola
ce4f075afd Add testcase from bug 2770. 
llvm-svn: 55897
 2008-09-08 11:17:54 +00:00
Evan Cheng
f8d8287454 Correctly handle physical register inputs. They are not explicit input operands in the resulting machine instrs. 
llvm-svn: 55893
 2008-09-08 08:39:33 +00:00
Evan Cheng
6690ccd573 Handle x86 truncate to i8 with target hook for now. 
llvm-svn: 55877
 2008-09-07 08:47:42 +00:00
Eli Friedman
fecea4b498 Fix for PR2687: Add patterns to match sint_to_fp and fp_to_sint for <2 x 
i32>.  This is a little messy, but it works.

We should really get rid of the intrinsics, though, since they map
perfectly well to standard LLVM instructions.

llvm-svn: 55864
 2008-09-05 23:07:03 +00:00
Evan Cheng
1f4b84cad0 Fix test. 
llvm-svn: 55849
 2008-09-05 20:04:37 +00:00
Evan Cheng
10a350fa89 If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls. 
llvm-svn: 55840
 2008-09-05 17:24:07 +00:00
Evan Cheng
bd15e330d0 For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries. 
llvm-svn: 55807
 2008-09-04 22:59:58 +00:00
Owen Anderson
cd3ee9198d Fix the ordering of operands to the store (inverted relative to LLVM IR), and fix the testcase. 
llvm-svn: 55777
 2008-09-04 16:48:33 +00:00
Owen Anderson
35485dbae3 Add a first attempt at implementing stores for X86 fast isel using target hooks. 
Dan or Evan, please review.

llvm-svn: 55764
 2008-09-04 07:08:58 +00:00
Evan Cheng
9c728a557d Load from GV stub should be locally CSE'd. 
llvm-svn: 55763
 2008-09-04 06:18:33 +00:00
Evan Cheng
53ce5fa5ce Remove code that pad number of bytes to pop for X86_FastCall CC. The code doesn't do the "aligning" for Cygwin, Mingw, and Windows. But aligning it on Darwin and Linux breaks gcc compatibility. That ruled out all the platforms we support! 
llvm-svn: 55756
 2008-09-04 01:04:15 +00:00
Evan Cheng
942d55dd92 Add X86 target hook to implement load (even from GlobalAddress). 
llvm-svn: 55693
 2008-09-03 06:44:39 +00:00
Duncan Sands
044fcaf6b4 Turn this legalize types test on. 
llvm-svn: 55605
 2008-09-01 12:00:55 +00:00
Bill Wendling
297eb080b6 Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR 
instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.

llvm-svn: 55582
 2008-08-31 02:59:23 +00:00
Bill Wendling
5c442aafb6 CellSPU doesn't appear to support fully the "ISD::ROTR" operation. The DAG 
combiner can now generate ROTR if the backend says that it can handle it. Cell
SPU says this, but gets an error from code gen saying that it can't select
ROTR. I'm xfailing this test until this can be fixed.

llvm-svn: 55579
 2008-08-31 02:32:12 +00:00
Evan Cheng
b40b710766 Re-apply 55467 with fix. If copy is being replaced by remat'ed def, transfer the implicit defs onto the remat'ed instruction. 
llvm-svn: 55564
 2008-08-30 09:09:33 +00:00
Evan Cheng
4bc8c9652e Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). 
llvm-svn: 55558
 2008-08-30 02:03:58 +00:00
Dale Johannesen
0124a7db51 Testcases for ppc atomics. 
llvm-svn: 55556
 2008-08-30 00:54:31 +00:00
Evan Cheng
c1c53221c5 Swap fp comparison operands and change predicate to allow load folding (safely this time). 
llvm-svn: 55553
 2008-08-29 23:22:12 +00:00
Evan Cheng
79d2a8f97d xfail this. 
llvm-svn: 55550
 2008-08-29 22:59:13 +00:00
Chris Lattner
f24550c9d2 allow this to pass. 
llvm-svn: 55540
 2008-08-29 17:18:26 +00:00
Evan Cheng
cdd06ba3f4 Swap fp comparison operands and change predicate to allow load folding. 
llvm-svn: 55521
 2008-08-28 23:48:31 +00:00
Mon P Wang
7566974359 In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN 
llvm-svn: 55499
 2008-08-28 21:04:05 +00:00
Dan Gohman
35a69c106a Optimize DAGCombiner's worklist processing. Previously it started 
its work by putting all nodes in the worklist, requiring a big
dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
list and maintains a worklist for nodes that are newly created or
need to be revisited. This allows the worklist to stay small in most
cases, so it can be a SmallVector.

This has the side effect of making DAGCombine not miss a folding
opportunity in alloca-align-rounding.ll.

llvm-svn: 55498
 2008-08-28 21:01:56 +00:00
Dan Gohman
8f4d612996 Revert r55467; it causes regressions in UnitTests/Vector/divides, 
Benchmarks/sim/sim, and others on x86-64.

llvm-svn: 55475
 2008-08-28 17:22:54 +00:00
Evan Cheng
28b0b18082 If a copy isn't coalesced, but its src is defined by trivial computation. Re-materialize the src to replace the copy. 
llvm-svn: 55467
 2008-08-28 07:53:51 +00:00
Dale Johannesen
ae522b8463 This test crashes on non-x86 host; make SSE explicit. 
Feel free to fix a better way!

llvm-svn: 55456
 2008-08-28 01:51:09 +00:00
Dan Gohman
5e5f1c9e8f Basic FastISel support for floating-point constants. 
llvm-svn: 55401
 2008-08-27 01:09:54 +00:00
Chris Lattner
c5c00890e5 If an xmm register is referenced explicitly in an inline asm, make sure to 
assign it to a version of the xmm register with the regclass that matches its
type.  This fixes PR2715, a bug handling some crazy xpcom case in mozilla.

llvm-svn: 55358
 2008-08-26 06:19:02 +00:00
Evan Cheng
569b489cf5 Try approach to moving call address load inside of callseq_start. Now it's done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot. 
llvm-svn: 55338
 2008-08-25 21:27:18 +00:00
Owen Anderson
27491bbf2c Add support for fast isel of (integer) immediate materialization pattens, and use them to support 
bitcast of constants in fast isel.

llvm-svn: 55325
 2008-08-25 20:20:32 +00:00
Dale Johannesen
6431c39237 Adjust grep's for new code sequence. 
llvm-svn: 55320
 2008-08-25 18:53:58 +00:00
Evan Cheng
2b9f879a99 Fix asm printing of MOVSDto64mr and MOV64toSDrm. 
llvm-svn: 55300
 2008-08-25 04:11:42 +00:00
Bill Wendling
05e1910595 Fix this test. Don't null out the file, just XFAIL it until patch can be fixed. 
llvm-svn: 55296
 2008-08-24 21:48:46 +00:00
Bill Wendling
5728cf59fd Temporarily reverting r55292. It's causing a bootstraping failure: 
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc ... src/libiberty/make-temp-file.c -o make-temp-file.o
Assertion failed: (Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] && "Wrong topological sorting"), function InitDAGTopologicalSorting, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp, line 508.
../../../../llvm-gcc.src/libiberty/hashtab.c:955: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
make[4]: *** [hashtab.o] Error 1
make[4]: *** Waiting for unfinished jobs....
make[3]: *** [multi-do] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libiberty] Error 2
make: *** [all] Error 2

llvm-svn: 55295
 2008-08-24 21:45:30 +00:00
Evan Cheng
a600778748 Move callseq_start above the call address load to allow load to be folded into the call node. 
llvm-svn: 55292
 2008-08-24 19:19:55 +00:00
Anton Korobeynikov
496a2865db Testcase for 64bit maskmovq 
llvm-svn: 55239
 2008-08-23 15:53:47 +00:00
Dale Johannesen
a8dbf73ffd Test all currently supported atomic builtins on x86-{32,64}. 
These just test that they go through the BE.

llvm-svn: 55208
 2008-08-22 22:39:21 +00:00
Dan Gohman
a398d11527 Factor out the predicate check code from DAGISelEmitter.cpp 
and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.

llvm-svn: 55156
 2008-08-22 00:20:26 +00:00
Bill Wendling
8ff0d8f829 Testcase for PR2585. 
llvm-svn: 55151
 2008-08-21 23:04:49 +00:00
Dan Gohman
4562b2bcfe Add -mattr=sse2 so this test doesn't fail on non-x86 hosts. 
llvm-svn: 55145
 2008-08-21 22:34:25 +00:00
Dale Johannesen
6fe9da3acc Make x86 and sse2 explicit for non-x86 hosts. 
llvm-svn: 55141
 2008-08-21 21:26:06 +00:00
Evan Cheng
ef2509b3ba Fix a number of byval / memcpy / memset related codegen issues. 
1. x86-64 byval alignment should be max of 8 and alignment of type. Previously the code was not doing what the commit message was saying.
2. Do not use byte repeat move and store operations. These are slow.

llvm-svn: 55139
 2008-08-21 21:00:15 +00:00
Dan Gohman
42fa2945d3 getelementptr doesn't work on x86-64 yet, because it 
has MOV64ri32 and no plain MOV64ri.

llvm-svn: 55126
 2008-08-21 17:28:42 +00:00
Dan Gohman
f4269f7bea MVT::getMVT uses iPTR for pointer types, while we need the actual 
intptr_t type in this case. FastISel can now select simple
getelementptr instructions.

llvm-svn: 55125
 2008-08-21 17:25:26 +00:00
Dan Gohman
a6e647dd7c Basic fast-isel support for instructions with constant int operands. 
llvm-svn: 55099
 2008-08-21 01:41:07 +00:00
Dan Gohman
bb28e0fc6d Add a -march line for this test, and run it on x86-64 too for fun. 
llvm-svn: 55030
 2008-08-20 00:56:07 +00:00
Dan Gohman
455abe7436 Add FastISel support for floating-point operations. 
llvm-svn: 55021
 2008-08-20 00:23:20 +00:00
Dan Gohman
ce636764de Add FastISel support for several more binary operators. 
llvm-svn: 55020
 2008-08-20 00:11:48 +00:00
Bill Wendling
ab7c8c091e Add support for the __sync_sub_and_fetch atomics and friends for X86. The code 
was already present, but not hooked up to anything.

llvm-svn: 55018
 2008-08-19 23:09:18 +00:00
Dan Gohman
d5c84e8061 Fast-isel is now *minimally* functional. Add a testcase to 
demonstrate the extent of its capabilities. Note that it
only attempts to operate on one of the blocks in this
testcase.

llvm-svn: 55016
 2008-08-19 22:37:59 +00:00
Dale Johannesen
15b76de064 Add support for 8 and 16 bit forms of __sync 
builtins on X86.

Change "lock" instructions to be on a separate line.
This is needed to work around a bug in the Darwin
assembler.

llvm-svn: 54999
 2008-08-19 18:47:28 +00:00
Evan Cheng
6534c78383 Fix a (u)comiss intrinsic lowering bug. It was using anyext which can return junk in higher bits. Patch by Nate Begeman. 
llvm-svn: 54903
 2008-08-17 19:22:34 +00:00
Dan Gohman
b0f5e18201 Improve support for vector casts in LLVM IR and CodeGen. 
llvm-svn: 54784
 2008-08-14 20:04:46 +00:00
Dan Gohman
096cdc6059 Allow SelectionDAG to create EXTRACT_VECTOR_ELT nodes with 
non-constant indices. Only a few of the peephole checks require
a constant index.

llvm-svn: 54764
 2008-08-13 21:51:37 +00:00
Dan Gohman
6789ef32d7 Improve the grep commands for this test to be tolerant of ABI 
differences, and to be more specific.

llvm-svn: 54648
 2008-08-11 20:10:41 +00:00
Dan Gohman
a27ed39f05 Take the FrameOffset into account when computing the alignment 
of stack objects. This fixes PR2656.

llvm-svn: 54646
 2008-08-11 18:27:03 +00:00
Dan Gohman
ac992cdc1c Add an EXTRACTPSmr pattern to match the pattern that 
X86ISelLowering creates.

llvm-svn: 54544
 2008-08-08 18:30:21 +00:00
Evan Cheng
4708df4776 It's not legal to output a GV in a coalesced section if it's used in an ARM PIC relative constantpool. 
llvm-svn: 54519
 2008-08-08 06:56:16 +00:00
Nick Lewycky
19a341cf57 Don't crash printing the asm for a ConstantExpr PtrToInt just because the int 
is narrower than the pointer. This testcase emits:

  .byte (((17) - 16) & 255)

llvm-svn: 54517
 2008-08-08 06:34:07 +00:00
Bruno Cardoso Lopes
f8906a40ab Support added for ctlz intrinsic, test case added. 
llvm-svn: 54516
 2008-08-08 06:16:31 +00:00
Bruno Cardoso Lopes
91abeb9458 [Last] Batch 7 of Mips CodeGen tests 
llvm-svn: 54512
 2008-08-08 04:12:42 +00:00
Bruno Cardoso Lopes
c4f524b9d1 Batch 6 of Mips CodeGen tests 
llvm-svn: 54511
 2008-08-08 04:11:30 +00:00
Bruno Cardoso Lopes
772cf1643c Batch 5 of Mips CodeGen tests 
llvm-svn: 54510
 2008-08-08 04:09:57 +00:00
Bruno Cardoso Lopes
7d4b844ee8 Batch 4 of Mips CodeGen tests 
llvm-svn: 54509
 2008-08-08 04:08:30 +00:00
Bruno Cardoso Lopes
06380b7221 Batch 3 of Mips CodeGen tests 
llvm-svn: 54508
 2008-08-08 04:05:51 +00:00
Bruno Cardoso Lopes
96efb82258 Batch 2 of Mips CodeGen tests 
llvm-svn: 54507
 2008-08-08 04:03:25 +00:00
Bruno Cardoso Lopes
42b4e15d50 Batch 1 of Mips CodeGen tests, more coming... 
I had a lot of simple local codegen tests and they are now ready to be placed
in test/CodeGen. 

llvm-svn: 54506
 2008-08-08 03:58:34 +00:00
Anton Korobeynikov
52d0ff92cc Print section flags ok on platforms, which use '@' as comment string. Fix test. 
llvm-svn: 54460
 2008-08-07 09:55:06 +00:00
Dan Gohman
74fa421281 Re-enable elimination of unnecessary SUBREG_TO_REG instructions in 
LowerSubregs, and fix an x86-64 isel bug that this exposed.

SUBREG_TO_REG for x86-64 implicit zero extension is only safe for
isel to generate when the source is known to always have zeros in
the high 32 bits. The EXTRACT_SUBREG instruction does not clear
the high 32 bits.

llvm-svn: 54444
 2008-08-07 02:54:50 +00:00
Dan Gohman
1674a7c2f3 Add an extra example that shouldn't get an and instruction. 
llvm-svn: 54443
 2008-08-07 02:23:06 +00:00
Dan Gohman
cc784f1662 Re-introduce the 8-bit subreg zext-inreg patterns for x86-32, 
this time using MOV32to32_ and MOV16to16_. Thanks to Evan for
suggesting this.

llvm-svn: 54418
 2008-08-06 18:27:21 +00:00
Evan Cheng
f4d1119fbd Fix PR2620: Fix X86cmppd selection code so it expects operands to be v2f64. 
llvm-svn: 54376
 2008-08-05 22:19:15 +00:00
Evan Cheng
a07795a0c3 Fix PR2596: out of bound reference. 
llvm-svn: 54375
 2008-08-05 21:51:46 +00:00
Owen Anderson
d1185e4da3 Update the remaining tests not to use -disable-correct-folding, and remove two 
that couldn't be updated.

llvm-svn: 54359
 2008-08-05 18:19:14 +00:00
Owen Anderson
117b0e405d One more -disable-correct-folding case removed. 
llvm-svn: 54358
 2008-08-05 18:08:56 +00:00
Owen Anderson
c5fd801d85 Remove another -disable-correct-folding use. 
llvm-svn: 54357
 2008-08-05 18:05:58 +00:00
Owen Anderson
f845ea8d52 Eliminate another use of -disable-correct-folding. 
llvm-svn: 54356
 2008-08-05 18:03:01 +00:00
Owen Anderson
4c7ea0c270 This check is unnecessary, and getting rid of it removes a use of -disable-correct-folding. 
llvm-svn: 54355
 2008-08-05 17:52:54 +00:00
Owen Anderson
7fca48d0bd Remove the need for -disable-correct-folding from this test. 
llvm-svn: 54354
 2008-08-05 17:49:52 +00:00
Evan Cheng
754148a2ec Fix PR2568: Fix bug that cause redudant kill marker after its live interval has been extended due to coalescing. 
llvm-svn: 54346
 2008-08-05 07:10:38 +00:00
Owen Anderson
231111faf9 Update these tests to work by disabling the new correct CFG generation. This flag should ONLY be used to for tests like these. 
llvm-svn: 54334
 2008-08-04 23:55:29 +00:00
Dan Gohman
60ea311ec8 Fix SDISel lowering of PHI nodes to use ComputeValueVTs. 
This allows it to work correctly on aggregate values.
This fixes PR2623.

llvm-svn: 54331
 2008-08-04 23:42:46 +00:00
Dan Gohman
af429b3e52 Fix SDISel lowering of zeroinitializer and undef to use ComputeValueVTs. 
This allows it to work correctly on nested aggregate values.
This fixes PR2625.

llvm-svn: 54330
 2008-08-04 23:30:41 +00:00
Dale Johannesen
c1ae4b8c08 Make sse2 explicit, for non-x86 hosts. 
llvm-svn: 54251
 2008-07-31 20:16:33 +00:00
Dan Gohman
f691fc703d Improve dagcombining for sext-loads and sext-in-reg nodes. 
llvm-svn: 54239
 2008-07-31 00:50:31 +00:00
Dan Gohman
4ca56a8993 Don't look for leaf values to store when lowering stores of 
empty structs. This fixes PR2612.

llvm-svn: 54226
 2008-07-30 18:36:51 +00:00
Dan Gohman
6f3fa16fd9 I missed this file in r54223. movzbl is now used instead 
of movzbw here.

llvm-svn: 54224
 2008-07-30 18:23:34 +00:00
Dan Gohman
efb5d2ce6e Reapply r54147 with a constraint to only use the 8-bit 
subreg form on x86-64, to avoid the problem with x86-32
having GPRs that don't have 8-bit subregs.

Also, change several 16-bit instructions to use 
equivalent 32-bit instructions. These have a smaller
encoding and avoid partial-register updates.

llvm-svn: 54223
 2008-07-30 18:09:17 +00:00
Mon P Wang
fb483982f5 Added support for overloading intrinsics (atomics) based on pointers 
to different address spaces.  This alters the naming scheme for those
intrinsics, e.g., atomic.load.add.i32 => atomic.load.add.i32.p0i32

llvm-svn: 54195
 2008-07-30 04:36:53 +00:00
Duncan Sands
c3d73fbfc0 Fix PR2609. If a label is deleted, then it needs 
to be marked invalid regardless of whether it is
a debug, an exception handling or (hopefully) a
GC label.

llvm-svn: 54172
 2008-07-29 20:56:02 +00:00
Dan Gohman
ebe629a4b2 Revert 54147. 
llvm-svn: 54148
 2008-07-29 01:02:18 +00:00
Dan Gohman
1816900fd1 Add x86 isel patterns to match what would be a ZERO_EXTEND_INREG operation, 
which is represented in codegen as an 'and' operation. This matches them
with movz instructions, instead of leaving them to be matched by and
instructions with an immediate field.

llvm-svn: 54147
 2008-07-28 22:18:25 +00:00
Dan Gohman
a5a50a8853 Fix embedded CRLF characters. 
llvm-svn: 54125
 2008-07-27 18:37:58 +00:00
Nate Begeman
1396e3d206 Fix test RUN line 
llvm-svn: 54040
 2008-07-25 19:08:59 +00:00
Nate Begeman
5523d40e4b Disable mov{L, LP, HP, HLP, *DUP} shuffles for mmx 
mmx needs its own fancy shuffle logic based on unpack; for now we get correct but awful code.

Also commit Mon Ping's VSETCC patch

llvm-svn: 54039
 2008-07-25 19:05:58 +00:00
Dan Gohman
6d394147f2 This test needs -aggressive-remat enabled. 
llvm-svn: 54015
 2008-07-25 15:25:32 +00:00
Evan Cheng
d4eb684258 Teach ARM isLegalAddressingMode to handle unknown type without crashing. This fixes pr2589. 
llvm-svn: 54004
 2008-07-25 00:55:17 +00:00
Dan Gohman
680e1bd958 Enable rematerialization of constants using AliasAnalysis::pointsToConstantMemory, 
and knowledge of PseudoSourceValues. This unfortunately isn't sufficient to allow
constants to be rematerialized in PIC mode -- the extra indirection is a
complication.

llvm-svn: 54000
 2008-07-25 00:02:30 +00:00
Dan Gohman
da5c2b50b8 Add target triples so these tests behave as expected on non-darwin hosts. 
llvm-svn: 53991
 2008-07-24 18:08:01 +00:00
Evan Cheng
9c8cac5fd7 Fix a catastrophic PPC64 ABI bug: i32 operands which are passed in memory (all of the parameter registers are used) are loaded from sp offsets that were off by 4. 
llvm-svn: 53979
 2008-07-24 08:17:07 +00:00
Evan Cheng
055f5e6ed0 New test case. 
llvm-svn: 53971
 2008-07-24 00:22:05 +00:00
Evan Cheng
20c9cdbe69 Fix PR2485: do all 4-element SSE shuffles in max. of 2 shuffle instructions. 
Based on patch by Nicolas Capens.

llvm-svn: 53939
 2008-07-23 00:22:17 +00:00
Duncan Sands
550e0de239 LegalizeTypes support for VSETCC. Fixes PR2575. 
llvm-svn: 53938
 2008-07-22 23:54:03 +00:00
Evan Cheng
1aa928a8e6 Fix pr2566: incorrect assumption about bit_convert. It doesn't not have to output a vector value. Patch by Nicolas Capens! 
llvm-svn: 53932
 2008-07-22 20:42:56 +00:00
Evan Cheng
901d469e05 Fix PR2574: implement v2f32 scalar_to_vector. 
llvm-svn: 53927
 2008-07-22 18:39:19 +00:00
Bill Wendling
98b6e63176 Fix for first part of PR2562. Generate the "pinsrw" instruction for inserts 
into v4i16 vectors.

llvm-svn: 53807
 2008-07-20 02:32:23 +00:00
Anton Korobeynikov
6f354293fe Testcase for PR2549 
llvm-svn: 53785
 2008-07-19 06:31:12 +00:00
Duncan Sands
ef45c602b6 Softfloat support for FDIV. Patch by 
Richard Pennington.

llvm-svn: 53773
 2008-07-18 21:18:48 +00:00
Dan Gohman
b97c076af4 In the CBackend, use casts to force integer add, subtract, and 
multiply to be done as unsigned, so that they have well defined
behavior on overflow. This fixes PR2408.

llvm-svn: 53767
 2008-07-18 18:43:12 +00:00
Evan Cheng
d26080487b Subreg live interval valno may not have a corresponding def machineinstr since it's less precise. 
llvm-svn: 53734
 2008-07-17 19:48:53 +00:00
Evan Cheng
48b2f3dfe9 Add nounwind. 
llvm-svn: 53733
 2008-07-17 19:48:04 +00:00
Dan Gohman
8981962672 Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk 
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.

Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.

This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.

These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.

llvm-svn: 53728
 2008-07-17 19:10:17 +00:00
Duncan Sands
c3331602f9 LegalizeTypes support for what seems to be the 
only missing ppc long double operations: FNEG
and FP_EXTEND.

llvm-svn: 53723
 2008-07-17 17:35:14 +00:00
Duncan Sands
778e45e748 Turn LegalizeTypes back off again for the moment: 
it is breaking Darwin bootstrap due to missing
functionality.

llvm-svn: 53721
 2008-07-17 17:06:03 +00:00
Duncan Sands
3448d4087f Add support for promoting and expanding AssertZext 
and AssertSext.  Needed when passing huge integer
parameters with the zeroext or signext attributes.

llvm-svn: 53684
 2008-07-16 16:03:07 +00:00
Duncan Sands
a8b538544a Test passing of integer parameters for integers 
of all sizes from i1 to i256.  The code is not
always that great, for example (x86)
        movw    %di, %ax
        movw    %ax, i17_s
where the store could be directly from %di.

llvm-svn: 53677
 2008-07-16 13:37:36 +00:00
Duncan Sands
be15f51092 Test codegen of loads and stores of all integer 
sizes from i1 to i256.  The generated code is
like one huge bug report of things that the DAG
combiner fails to simplify!

llvm-svn: 53676
 2008-07-16 13:10:20 +00:00
Duncan Sands
b2e1ddbd0b Turn on LegalizeTypes by default. 
llvm-svn: 53671
 2008-07-16 11:36:51 +00:00
Duncan Sands
35d3e774ed The atomic.cmp.swap promotion logic is wrong: it 
simply does the atomic.cmp.swap on the larger type,
which means it blows away whatever is sitting in
the bytes just after the memory location, i.e.
causes a buffer overflow.  This really requires
target specific code, which is why LegalizeTypes
doesn't try to handle this case generically.  The
existing (wrong) code in LegalizeDAG will go away
automatically once the type legalization code is
removed from LegalizeDAG so I'm leaving it there
for the moment.  Meanwhile, don't test for this
feature.

llvm-svn: 53669
 2008-07-16 08:09:48 +00:00
Duncan Sands
7ca2df2319 LegalizeTypes support for fabs on ppc long double. 
llvm-svn: 53613
 2008-07-15 15:02:44 +00:00
Duncan Sands
58eb5e35da LegalizeTypes support for promotion of bswap. 
In LegalizeDAG the value is zero-extended to
the new type before byte swapping.  It doesn't
matter how the extension is done since the new
bits are shifted off anyway after the swap, so
extend by any old rubbish bits.  This results
in the final assembler for the testcase being
one line shorter.

llvm-svn: 53604
 2008-07-15 10:18:22 +00:00
Duncan Sands
710be60c23 LegalizeTypes support for promotion of SIGN_EXTEND_INREG. 
llvm-svn: 53603
 2008-07-15 10:14:24 +00:00
Evan Cheng
05e5317cab Fix PR2536: a nasty spiller bug. If a two-address instruction uses a register but the use portion of its live range is not part of its liveinterval, it must be defined by an implicit_def. In that case, do not spill the use. e.g. 
8   %reg1024<def> = IMPLICIT_DEF
12  %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2

The live range [12, 14) are not part of the r1024 live interval since it's defined by an implicit def. It will not conflicts with live interval of r1025. Now suppose both registers are spilled, you can easily see a situation where both registers are reloaded before the INSERT_SUBREG and both target registers that would overlap.

llvm-svn: 53503
 2008-07-12 01:56:02 +00:00
Duncan Sands
52f1dbf139 Port a shift-by-1 optimization from LegalizeDAG: it 
was presumably added after the rest of the code was
copied to LegalizeTypes.

llvm-svn: 53459
 2008-07-11 16:54:57 +00:00
Bill Wendling
9f17caa9a9 The frame address on an x86-64 box needs to be offset by -8, not -4. 
llvm-svn: 53450
 2008-07-11 07:18:52 +00:00
Bill Wendling
3be8dca83f Put CPPBackend tests into their own directory and run them only if they're 
supported.

llvm-svn: 53427
 2008-07-10 22:35:32 +00:00
Chris Lattner
5f3c587276 Fix an altivec constant miscompilation that Duncan found through 
his work on legalizetypes.

llvm-svn: 53410
 2008-07-10 16:33:38 +00:00
Evan Cheng
02a618dc56 Fix for PR2472. Use movss to set lower 32-bits of a zero XMM vector. 
llvm-svn: 53386
 2008-07-10 01:08:23 +00:00
Anton Korobeynikov
f710ada483 Testcase for PR2024 
llvm-svn: 53327
 2008-07-09 14:09:41 +00:00
Dan Gohman
6057cf766c Refactor the tablegen DAGISelEmitter code for outputing calls to 
getTargetNode and SelectNodeTo to reduce duplication, and to
make some of the getTargetNode code available to SelectNodeTo.
Use SelectNodeTo instead of getTargetNode in several new
interesting cases, as it mutates nodes in place instead of
creating new ones.

This triggers some scheduling behavior differences due to nodes
being presented to the scheduler in a different order. Some of the
arbitrary scheduling decisions it makes are now arbitrarily made
differently. This is visible in CodeGen/PowerPC/LargeAbsoluteAddr.ll,
where a trivial scheduling difference led to a trivial register
allocation difference.

llvm-svn: 53203
 2008-07-07 21:00:17 +00:00
Evan Cheng
cf3a4ad46d Fix two serious LSR bugs. 
1. LSR runOnLoop is always returning false regardless if any transformation is made.
2. AddUsersIfInteresting can create new instructions that are added to DeadInsts. But there is a later early exit which prevents them from being freed.

llvm-svn: 53193
 2008-07-07 19:51:32 +00:00
Dale Johannesen
51edab312c Considering predecessors of exit blocks gets 
us a little more tail merging.

llvm-svn: 52986
 2008-07-01 21:50:49 +00:00
Chris Lattner
95fecdd63a Implement split and scalarize for SELECT_CC, fixing PR2504 
llvm-svn: 52887
 2008-06-30 02:43:01 +00:00
Chris Lattner
153b6695b8 test doesn't need eh info 
llvm-svn: 52811
 2008-06-27 03:14:20 +00:00
Dale Johannesen
76f5dc0cc4 Allow for rounding up of stack frame. 
llvm-svn: 52751
 2008-06-26 01:55:32 +00:00
Chris Lattner
2b67ff8632 when we know the signbit of an input to uint_to_fp is zero, 
change it to sint_to_fp on targets where that is cheaper (and
visaversa of course).  This allows us to compile uint_to_fp to:

_test:
	movl	4(%esp), %eax
	shrl	$23, %eax
	cvtsi2ss	%eax, %xmm0
	movl	8(%esp), %eax
	movss	%xmm0, (%eax)
	ret

instead of:

	.align	3
LCPI1_0:					##  double
	.long	0	## double least significant word 4.5036e+15
	.long	1127219200	## double most significant word 4.5036e+15
	.text
	.align	4,0x90
	.globl	_test
_test:
	subl	$12, %esp
	movl	16(%esp), %eax
	shrl	$23, %eax
	movl	%eax, (%esp)
	movl	$1127219200, 4(%esp)
	movsd	(%esp), %xmm0
	subsd	LCPI1_0, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movl	20(%esp), %eax
	movss	%xmm0, (%eax)
	addl	$12, %esp
	ret

llvm-svn: 52747
 2008-06-26 00:16:49 +00:00
Evan Cheng
71fbfe73c1 - Fix a x86 vector isel bug: illegal transformation of a vector_shuffle into a 
shift.
- Add a readme entry for a missing vector_shuffle optimization that results in
  awful codegen.

llvm-svn: 52740
 2008-06-25 20:52:59 +00:00
Mon P Wang
7d89d61387 Added MemOperands to Atomic operations since Atomics touches memory. 
Added abstract class MemSDNode for any Node that have an associated MemOperand
Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and
atomic.lss => atomic.load.sub

llvm-svn: 52706
 2008-06-25 08:15:39 +00:00
Evan Cheng
bab5925a0b Enable two-address remat by default. 
llvm-svn: 52701
 2008-06-25 01:16:38 +00:00
Dale Johannesen
244433ebb1 v2f32 is now a valid (MMX) type which breaks this 
test (doesn't work for any MMX vector types, it's
not me).  Rewritten to use v2i16 which is generic
and going to stay that way; I think that preserves
the point of the test.

llvm-svn: 52692
 2008-06-24 22:03:36 +00:00
Evan Cheng
a62f5f0f82 If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. 
llvm-svn: 52670
 2008-06-24 07:10:51 +00:00
Bill Wendling
2501066409 This situation can occur: 
,------.
    |      |
    |      v
    |   t2 = phi ... t1 ...
    |      |
    |      v
    |   t1 = ...
    |  ... = ... t1 ...
    |      |
    `------'

where there is a use in a PHI node that's a predecessor to the defining
block. We don't want to mark all predecessors as having the value "alive" in
this case. Also, the assert was too restrictive and didn't handle this case.

llvm-svn: 52655
 2008-06-23 23:41:14 +00:00
Bill Wendling
d6b7d457cf Make test work on non-x86 machines (like my G4 PPC). 
llvm-svn: 52619
 2008-06-23 06:16:31 +00:00
Duncan Sands
1dd6ef8f8e Support for load/store of expanded float types. I 
don't know if a truncating store is possible here,
but added support for it anyway.

llvm-svn: 52577
 2008-06-21 17:00:47 +00:00
Evan Cheng
1d07cd32c2 Undo spill weight tweak. Need to investigate the performance regressions. 
llvm-svn: 52572
 2008-06-21 06:45:54 +00:00
Evan Cheng
4006f4cdf0 ISD::UNDEF should be expanded recursively / iteratively. 
llvm-svn: 52508
 2008-06-19 22:01:11 +00:00
Eli Friedman
570aa6f801 Fix a bug with <8 x i16> shuffle lowering on X86 where parts of the 
shuffle could be skipped.  The check is invalid because the loop index i 
doesn't correspond to the element actually inserted. The correct check is
already done a few lines earlier, for whether the element is already in 
the right spot, so this shouldn't have any effect on the codegen for 
code that was already correct.

llvm-svn: 52486
 2008-06-19 06:09:51 +00:00
Evan Cheng
919b735586 New test case. 
llvm-svn: 52483
 2008-06-19 01:50:24 +00:00
Evan Cheng
ee801276b3 This also got better (55 - 51 instructions). But doing one more re-materialization. 
llvm-svn: 52482
 2008-06-19 01:50:13 +00:00
Evan Cheng
56e17b525c This got better. 
llvm-svn: 52481
 2008-06-19 01:46:43 +00:00
Evan Cheng
8cfd1d39a1 Do not issue identity copies. 
llvm-svn: 52373
 2008-06-16 22:52:53 +00:00
Evan Cheng
d27948e716 - Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. 
- Mark lots of X86 intrinsics as "Commutative" to allow load folding.

llvm-svn: 52353
 2008-06-16 20:29:38 +00:00
Evan Cheng
2e99c9cbf8 Teach the spiller to commute instructions in order to fold a reload. This hits 410 times on 444.namd and 122 times on 252.eon. 
llvm-svn: 52266
 2008-06-13 23:58:02 +00:00
Duncan Sands
40c8db881a Disable some DAG combiner optimizations that may be 
wrong for volatile loads and stores.  In fact this
is almost all of them!  There are three types of
problems: (1) it is wrong to change the width of
a volatile memory access.  These may be used to
do memory mapped i/o, in which case a load can have
an effect even if the result is not used.  Consider
loading an i32 but only using the lower 8 bits.  It
is wrong to change this into a load of an i8, because
you are no longer tickling the other three bytes.  It
is also unwise to make a load/store wider.  For
example, changing an i16 load into an i32 load is
wrong no matter how aligned things are, since the
fact of loading an additional 2 bytes can have
i/o side-effects.  (2) it is wrong to change the
number of volatile load/stores: they may be counted
by the hardware.  (3) it is wrong to change a volatile
load/store that requires one memory access into one
that requires several.  For example on x86-32, you
can store a double in one processor operation, but to
store an i64 requires two (two i32 stores).  In a
multi-threaded program you may want to bitcast an i64
to a double and store as a double because that will
occur atomically, and be indivisible to other threads.
So it would be wrong to convert the store-of-double
into a store of an i64, because this will become two
i32 stores - no longer atomic.  My policy here is
to say that the number of processor operations for
an illegal operation is undefined.  So it is alright
to change a store of an i64 (requires at least two
stores; but could be validly lowered to memcpy for
example) into a store of double (one processor op).
In short, if the new store is legal and has the same
size then I say that the transform is ok.  It would
also be possible to say that transforms are always
ok if before they were illegal, whether after they
are illegal or not, but that's more awkward to do
and I doubt it buys us anything much.
However this exposed an interesting thing - on x86-32
a store of i64 is considered legal!  That is because
operations are marked legal by default, regardless of
whether the type is legal or not.  In some ways this
is clever: before type legalization this means that
operations on illegal types are considered legal;
after type legalization there are no illegal types
so now operations are only legal if they really are.
But I consider this to be too cunning for mere mortals.
Better to do things explicitly by testing AfterLegalize.
So I have changed things so that operations with illegal
types are considered illegal - indeed they can never
map to a machine operation.  However this means that
the DAG combiner is more conservative because before
it was "accidentally" performing transforms where the
type was illegal because the operation was nonetheless
marked legal.  So in a few such places I added a check
on AfterLegalize, which I suppose was actually just
forgotten before.  This causes the DAG combiner to do
slightly more than it used to, which resulted in the X86
backend blowing up because it got a slightly surprising
node it wasn't expecting, so I tweaked it.

llvm-svn: 52254
 2008-06-13 19:07:40 +00:00
Evan Cheng
66ce588b87 Fix some tests. 
llvm-svn: 52245
 2008-06-12 21:23:38 +00:00
Matthijs Kooijman
d07ffc50fa Don't try to compile tests for the ev56 alpha subtarget, which hasn't been 
supported since r33492.

llvm-svn: 52237
 2008-06-12 13:44:26 +00:00
Dale Johannesen
47cee90b57 Fix parameter spelling: sse not sse1 
llvm-svn: 52185
 2008-06-10 17:57:58 +00:00
Matthijs Kooijman
00a807266e Fix some more quoting issues in RUN lines, this time regarding unintended 
variable expansions involving the $ character.

This fixes 4 tests that were not running properly before.

llvm-svn: 52183
 2008-06-10 16:10:32 +00:00
Matthijs Kooijman
281711dc95 Remove double pipes in RUN commandlines. 
This fixes 5 testcases that were not being run properly before.

llvm-svn: 52180
 2008-06-10 15:11:36 +00:00
Matthijs Kooijman
c638fe5b8b For all RUN lines starting with "not", redirect stderr to /dev/null so tests 
don't fail when (expected) error output is produced. This fixes 17 tests.

While I was there, I also made all RUN lines of the form "not llvm-as..." a bit
more consistent, they now all redirect stderr and stdout to /dev/null and use
input redirect to read their input.

llvm-svn: 52174
 2008-06-10 12:57:32 +00:00
Dan Gohman
f5602924ae Convert several tests to use temporary files instead of redundantly 
executing the test commands.

llvm-svn: 52163
 2008-06-10 00:36:41 +00:00
Rafael Espindola
feaadb1e05 add support for PIC on linux x86-64 
llvm-svn: 52139
 2008-06-09 09:52:31 +00:00
Anton Korobeynikov
aed2cbb0a1 Remove invalid test 
llvm-svn: 52093
 2008-06-08 16:59:10 +00:00
Anton Korobeynikov
a9fa994d9b Testcase for PR2418 
llvm-svn: 52047
 2008-06-06 16:08:56 +00:00
Evan Cheng
e77d6a1a2d Fix a memcpy lowering bug. Even though the memcpy alignment is smaller than the desired alignment, the frame destination alignment may still be larger than the desired alignment. Don't change its alignment to something smaller. 
llvm-svn: 51970
 2008-06-04 23:37:54 +00:00