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485 Commits

Author SHA1 Message Date
Vincent Lejeune
677331bc8f R600: Use a refined heuristic to choose when switching clause 
This is using a hint from AMD APP OpenCL Programming Guide with
empirically tweaked parameters.
I used Unigine Heaven 3.0 to determine best parameters on my system
(i7 2600/Radeon 6950/Kernel 3.9.4) the benchmark :
it went from 38.8 average fps to 39.6, which is ~3% gain.
(Lightmark 2008.2 gain is much more marginal: from 537 to 539)

There is no lit test provided as the parameter were determined
empirically and it it would be nearly impossiblet to find a test
program that check for optimal behavior.

llvm-svn: 183593
 2013-06-07 23:30:34 +00:00
Vincent Lejeune
2f252fdf26 R600: Anti dep better handled in tex clause 
llvm-svn: 183592
 2013-06-07 23:30:26 +00:00
Tom Stellard
7c091ffbf7 R600: Fix calculation of stack offset in AMDGPUFrameLowering 
We weren't computing structure size correctly and we were relying on
the original alloca instruction to compute the offset, which isn't
always reliable.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183568
 2013-06-07 20:52:05 +00:00
Tom Stellard
0ffa8d28b1 R600: Rework subtarget info and remove AMDILDevice classes 
This should simplify the subtarget definitions and make it easier to
add new ones.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183566
 2013-06-07 20:37:48 +00:00
Bill Wendling
aa15a56463 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183561
 2013-06-07 20:28:55 +00:00
Tom Stellard
f4646ab025 R600: Fix the fetch limits for R600 generation GPUs 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>

https://bugs.freedesktop.org/show_bug.cgi?id=64257

llvm-svn: 183560
 2013-06-07 20:28:55 +00:00
Tom Stellard
1ffd5f5a26 R600: Move Subtarget feature definitions into AMDGPU.td 
This is the convention used by the other targets.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183559
 2013-06-07 20:28:49 +00:00
Tom Stellard
17c5c164b3 R600: Remove unnecessary include 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183558
 2013-06-07 20:28:43 +00:00
Benjamin Kramer
8a5e172647 R600: Don't compare iterators of different maps. 
Found be libstdc's debug mode.

llvm-svn: 183549
 2013-06-07 19:59:34 +00:00
Benjamin Kramer
ed67a770b9 Vincent says the element is at most once in the vector, so we don't need a full std::remove. 
llvm-svn: 183541
 2013-06-07 18:18:12 +00:00
Benjamin Kramer
0c09c2c229 R600: Fix a potential iterator invalidation issue. 
As a bonus this reduces the loop from O(n^2) to O(n).

llvm-svn: 183532
 2013-06-07 16:13:49 +00:00
Vincent Lejeune
016ed40e3b R600: Remove an extra break in R600OptimizeVectorRegisters.cpp 
llvm-svn: 183528
 2013-06-07 15:44:53 +00:00
Vincent Lejeune
aeaa3d375a R600: Rewrite an awkward loop in R600MachineScheduler 
llvm-svn: 183458
 2013-06-06 23:08:32 +00:00
Vincent Lejeune
607107c791 R600: Remove leftover code in R600MachineScheduler.cpp 
Spotted by Benjamin Kramer.

llvm-svn: 183413
 2013-06-06 14:18:29 +00:00
Bill Wendling
b592e0c3af Cast to the correct type. Pointer, not reference. 
llvm-svn: 183385
 2013-06-06 05:39:29 +00:00
NAKAMURA Takumi
230c4940c2 R600OptimizeVectorRegisters.cpp: Tweak a warning. [-Wsometimes-uninitialized] 
FIXME: Is it false alarm?
llvm-svn: 183371
 2013-06-06 02:15:12 +00:00
NAKAMURA Takumi
7d98129541 R600OptimizeVectorRegisters.cpp: Suppress a warning. [-Wunused-variable] 
llvm-svn: 183370
 2013-06-06 02:15:06 +00:00
NAKAMURA Takumi
3381a4cf72 Trailing linefeed. 
llvm-svn: 183369
 2013-06-06 02:15:00 +00:00
Bill Wendling
03a97218ab Cast to the proper type. 
llvm-svn: 183365
 2013-06-06 01:04:21 +00:00
Tom Stellard
34a63fe157 R600: Replace predicate loop with predicate function 
llvm-svn: 183351
 2013-06-05 23:39:50 +00:00
Vincent Lejeune
dd2a468cbd R600: Add a pass that merge Vector Register 
Previously commited @183279 but tests were failing, reverted @183286
It was broken because @183336 was missing, now it's there.

llvm-svn: 183343
 2013-06-05 21:38:04 +00:00
Vincent Lejeune
cc7d08e974 R600: Schedule copy from phys register at beginning of block 
It allows regalloc pass to remove them by trivially assigning associated reg

llvm-svn: 183336
 2013-06-05 20:27:35 +00:00
Tom Stellard
ecf6bd2eaa R600: Make sure to schedule AR register uses and defs in the same clause 
Reviewed-by: vljn at ovi.com
llvm-svn: 183294
 2013-06-05 03:43:06 +00:00
Rafael Espindola
f5e919b2e6 Revert "R600: Add a pass that merge Vector Register" 
This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing.

llvm-svn: 183286
 2013-06-05 01:48:30 +00:00
Vincent Lejeune
57d56af481 R600: Add a pass that merge Vector Register 
llvm-svn: 183279
 2013-06-04 23:17:26 +00:00
Vincent Lejeune
7c89765008 R600: Const/Neg/Abs can be folded to dot4 
llvm-svn: 183278
 2013-06-04 23:17:15 +00:00
Vincent Lejeune
8d2ef79cb9 R600: Swizzle texture/export instructions 
llvm-svn: 183229
 2013-06-04 15:04:53 +00:00
Aaron Ballman
c198459ea4 Silencing an MSVC warning about mixing bool and unsigned int. 
llvm-svn: 183176
 2013-06-04 01:03:03 +00:00
Tom Stellard
0c2bbb2a1f R600/SI: Add support for work item and work group intrinsics 
llvm-svn: 183138
 2013-06-03 17:40:18 +00:00
Tom Stellard
0faf53682e R600/SI: Add a calling convention for compute shaders 
llvm-svn: 183137
 2013-06-03 17:40:11 +00:00
Tom Stellard
47a52f3e69 R600/SI: Custom lower i64 sign_extend 
llvm-svn: 183136
 2013-06-03 17:40:03 +00:00
Tom Stellard
c08ab0862e R600/SI: Adjust some instructions' out register class after ISel 
This is necessary to avoid generating VGPR to SGPR copies in some
cases.

llvm-svn: 183135
 2013-06-03 17:39:58 +00:00
Tom Stellard
29284f6cc9 R600/SI: Handle REG_SEQUENCE in fitsRegClass() 
llvm-svn: 183134
 2013-06-03 17:39:54 +00:00
Tom Stellard
45c3f3e363 R600/SI: Handle nodes with glue results correctly SITargetLowering::foldOperands() 
llvm-svn: 183133
 2013-06-03 17:39:50 +00:00
Tom Stellard
d58c6099f1 R600/SI: Fixup CopyToReg register class in PostprocessISelDAG() 
The CopyToReg nodes will sometimes try to copy a value from a VGPR to an
SGPR.  This kind of copy is not possible, so we need to detect
VGPR->SGPR copies and do something else.  The current strategy is to
replace these copies with VGPR->VGPR copies and hope that all the users
of CopyToReg can accept VGPRs as arguments.

llvm-svn: 183132
 2013-06-03 17:39:46 +00:00
Tom Stellard
7e44e13b15 R600/SI: Add support for global loads 
llvm-svn: 183131
 2013-06-03 17:39:43 +00:00
Tom Stellard
8e0ca8c4b9 R600/SI: Rework MUBUF store instructions 
The lowering of stores is now mostly handled in the tablegen files.  No
more BUFFER_STORE nodes I generated during legalization.

llvm-svn: 183130
 2013-06-03 17:39:37 +00:00
Vincent Lejeune
991eb7f653 R600: 3 op instructions have no write bit but the result are store in PV 
llvm-svn: 183111
 2013-06-03 15:56:12 +00:00
Vincent Lejeune
97b4286f95 R600: CALL_FS consumes a stack size entry 
llvm-svn: 183108
 2013-06-03 15:44:42 +00:00
Vincent Lejeune
55871f8f8a R600: use capital letter for PV channel 
llvm-svn: 183107
 2013-06-03 15:44:35 +00:00
Vincent Lejeune
66af4ee12a R600: Constraints input regs of interp_xy,_zw 
llvm-svn: 183106
 2013-06-03 15:44:16 +00:00
Ahmed Bougacha
2263547c8f Make SubRegIndex size mandatory, following r183020. 
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.

llvm-svn: 183061
 2013-05-31 23:45:26 +00:00
Patrik Hagglund
5402d55791 Temporary fix to get rid of gcc warning. 
llvm-svn: 182832
 2013-05-29 07:32:08 +00:00
Andrew Trick
2790ee3a8e Track IR ordering of SelectionDAG nodes 2/4. 
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

llvm-svn: 182703
 2013-05-25 02:42:55 +00:00
Tom Stellard
dee18e3abb R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg 
Patch by: Vincent Lejeune

https://bugs.freedesktop.org/show_bug.cgi?id=64877

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 182600
 2013-05-23 18:26:42 +00:00
Benjamin Kramer
620125412f Move passes from namespace llvm into anonymous namespaces. Sort includes while there. 
llvm-svn: 182594
 2013-05-23 17:10:37 +00:00
Benjamin Kramer
0d26c557b0 R600: Hide symbols of implementation details. 
Also removes an unused function.

llvm-svn: 182587
 2013-05-23 15:43:05 +00:00
Aaron Ballman
1068da3397 Setting the default value (fixes CRT assertions about uninitialized variable use when doing debug MSVC builds), and fixing coding style. 
llvm-svn: 182585
 2013-05-23 14:55:00 +00:00
Rafael Espindola
152d42bba8 Fix 32 bit build in c++11 mode. 
The error was:
error: non-constant-expression cannot be narrowed from type 'long long' to 'long' in initializer list [-Wc++11-narrowing]
        MI.getOperand(6).getImm() & 0x1F,

llvm-svn: 182584
 2013-05-23 13:22:30 +00:00
Rafael Espindola
62a4be044f Fix a leak on the r600 backend. 
This should bring the valgrind bot back to life.

llvm-svn: 182561
 2013-05-23 03:31:47 +00:00
Rafael Espindola
3c1e81fa1a clang-format this file. 
llvm-svn: 182560
 2013-05-23 03:28:39 +00:00
Rafael Espindola
c88b0cb7cf Fix use after free (pr16103). 
llvm-svn: 182482
 2013-05-22 15:31:11 +00:00
Rafael Espindola
4aa7f7fd2b Check that a function starts with llvm. before using GET_FUNCTION_RECOGNIZER. 
Fixes a use of uninitialized memory found by asan and valgind.

llvm-svn: 182480
 2013-05-22 14:57:42 +00:00
NAKAMURA Takumi
e448601de9 R600ISelLowering.cpp: Avoid "using namespace Intrinsic;" to appease MSC. Specify namespaces explicitly here. 
MSC is confused about "memcpy" between <cstring> and llvm::Intrinsic::memcpy, when llvm::Intrinsic were exposed.

llvm-svn: 182452
 2013-05-22 06:37:31 +00:00
NAKAMURA Takumi
256566af93 R600: Whitespace and untabify. 
llvm-svn: 182451
 2013-05-22 06:37:25 +00:00
Owen Anderson
5a2e4b2e02 Create an FPOW SDNode opcode def in the target independent .td file rather than in a specific backend. 
llvm-svn: 182450
 2013-05-22 06:36:09 +00:00
Rafael Espindola
9fa2758841 Attempt to fix the mingw32 bot. 
This should hopefully fix
http://lab.llvm.org:8011/builders/clang-x86_64-darwin11-self-mingw32

llvm-svn: 182446
 2013-05-22 02:30:47 +00:00
Rafael Espindola
ff498d2344 s/u_int32_t/uint32_t/ 
llvm-svn: 182444
 2013-05-22 01:36:19 +00:00
Rafael Espindola
c584e29854 Fix warning in non-assert build. 
llvm-svn: 182443
 2013-05-22 01:29:38 +00:00
Benjamin Kramer
66d4343951 R600: Fix bug detected by GCC warning. 
R600TextureIntrinsicsReplacer.cpp:232: warning: the address of ‘ArgsType’ will always evaluate as ‘true’

This doesn't have any effect on the output as a vararg intrinsic behaves the
same way as a non-vararg one.

llvm-svn: 182293
 2013-05-20 15:58:43 +00:00
Tom Stellard
8c433f74be R600/SI: Use a multiclass for MUBUF_Load_Helper 
This will simplify the instructions and also the pattern definitions.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182288
 2013-05-20 15:02:31 +00:00
Tom Stellard
20519ba9b1 R600/SI: Add a pattern for S_LOAD_DWORDX2_* instructions 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182287
 2013-05-20 15:02:28 +00:00
Tom Stellard
d72698331e R600/SI: Add pattern for rotr 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182286
 2013-05-20 15:02:24 +00:00
Tom Stellard
5ca265d214 R600: Swap the legality of rotl and rotr 
The hardware supports rotr and not rotl.

llvm-svn: 182285
 2013-05-20 15:02:19 +00:00
Tom Stellard
1609774b15 R600/SI: Add patterns for 64-bit shift operations 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182284
 2013-05-20 15:02:12 +00:00
Tom Stellard
ad64547aac R600/SI: Use the same names for VOP3 operands and encoding fields 
This makes it possible to reorder the operands without breaking the
encoding.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182283
 2013-05-20 15:02:08 +00:00
Tom Stellard
9e5dc799d9 R600/SI: Make fitsRegClass() operands const 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182282
 2013-05-20 15:02:01 +00:00
Matt Arsenault
118196f0ca Add LLVMContext argument to getSetCCResultType 
llvm-svn: 182180
 2013-05-18 00:21:46 +00:00
Rafael Espindola
aabd77b198 Fix the build in c++11 mode. 
The errors were:

non-constant-expression cannot be narrowed from type 'int64_t' (aka 'long') to 'uint32_t' (aka 'unsigned int') in initializer list

and

non-constant-expression cannot be narrowed from type 'long' to 'uint32_t' (aka 'unsigned int') in initializer list

llvm-svn: 182168
 2013-05-17 22:45:52 +00:00
Vincent Lejeune
c8aad4509a R600: Lower int_load_input to copyFromReg instead of Register node 
It solves a bug uncovered by dot4 patch where the register class of
int_load_input use was ignored.

llvm-svn: 182130
 2013-05-17 16:51:06 +00:00
Vincent Lejeune
5a2e018ab6 R600: Use bottom up scheduling algorithm 
llvm-svn: 182129
 2013-05-17 16:50:56 +00:00
Vincent Lejeune
2bf65b1826 R600: Use depth first scheduling algorithm 
It should increase PV substitution opportunities and lower gpr
usage (pending computations path are "flushed" sooner)

llvm-svn: 182128
 2013-05-17 16:50:44 +00:00
Vincent Lejeune
a140216a0a R600: Replace big texture opcode switch in scheduler by usesTC/usesVC 
llvm-svn: 182127
 2013-05-17 16:50:37 +00:00
Vincent Lejeune
152473c61c R600: Relax some vector constraints on Dot4. 
Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.

llvm-svn: 182126
 2013-05-17 16:50:32 +00:00
Vincent Lejeune
0c663b698a R600: Improve texture handling 
llvm-svn: 182125
 2013-05-17 16:50:20 +00:00
Vincent Lejeune
b57cb76b6d R600: Rename 128 bit registers. 
Almost all instructions that takes a 128 bits reg as input (fetch, export...)
have the abilities to swizzle their argument and output. Instead of printing
default swizzle for each 128 bits reg, rename T*.XYZW to T* and let instructions
print potentially optimized swizzles themselves.

llvm-svn: 182124
 2013-05-17 16:50:09 +00:00
Vincent Lejeune
d391d51989 R600: Some factorization 
llvm-svn: 182123
 2013-05-17 16:50:02 +00:00
Vincent Lejeune
bf991c018d R600: Factorize Fetch size limit inside AMDGPUSubTarget 
llvm-svn: 182122
 2013-05-17 16:49:55 +00:00
Vincent Lejeune
d39a89783b R600: prettier dump of clamp 
llvm-svn: 182121
 2013-05-17 16:49:49 +00:00
Tom Stellard
a4cc081e08 R600: Fix encoding for R600 family GPUs 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>

https://bugs.freedesktop.org/show_bug.cgi?id=64193
https://bugs.freedesktop.org/show_bug.cgi?id=64257
https://bugs.freedesktop.org/show_bug.cgi?id=64320

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 182113
 2013-05-17 15:23:21 +00:00
Tom Stellard
b91da0601d R600: Pass MCSubtargetInfo reference to R600CodeEmitter 
llvm-svn: 182112
 2013-05-17 15:23:12 +00:00
Christian Konig
34f0d6eaf2 R600/SI: return undef instead of null for skipped arguments 
This is a candidate for the stable branch.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=64694

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182084
 2013-05-17 09:46:48 +00:00
Tom Stellard
5f6b8d7e47 R600/SI: Add processor type for Hainan asic 
Patch by: Alex Deucher

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 181792
 2013-05-14 14:42:56 +00:00
Rafael Espindola
44f36ace35 Remove unused fields and arguments. 
llvm-svn: 181706
 2013-05-13 14:34:48 +00:00
Rafael Espindola
237980d752 Remove the MachineMove class. 
It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.

I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.

llvm-svn: 181680
 2013-05-13 01:16:13 +00:00
Rafael Espindola
4e52b3900b Fix the R600 build. 
llvm-svn: 181621
 2013-05-10 18:31:42 +00:00
Tom Stellard
7edf38bf1f R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns 
The BFE optimization was the only one we were actually using, and it was
emitting an intrinsic that we don't support.

https://bugs.freedesktop.org/show_bug.cgi?id=64201

Reviewed-by: Christian König <christian.koenig@amd.com>

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 181580
 2013-05-10 02:09:45 +00:00
Tom Stellard
ed363c57b2 R600: Expand SUB for v2i32/v4i32 
Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 181579
 2013-05-10 02:09:39 +00:00
Tom Stellard
3ca3d250c6 R600: Expand MUL for v4i32/v2i32 
Fixes piglit test for OpenCL builtin mul24, and allows mad24 to run.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 181578
 2013-05-10 02:09:34 +00:00
Tom Stellard
56fef8261c R600: Expand SRA for v4i32/v2i32 
v2: Add v4i32 test

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 181577
 2013-05-10 02:09:29 +00:00
Tom Stellard
5d4a5a0d37 R600: Expand vselect for v4i32 and v2i32 
v2: Add vselect v4i32 test

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 181576
 2013-05-10 02:09:24 +00:00
Tom Stellard
3a335f24af R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode 
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181269
 2013-05-06 23:02:19 +00:00
Tom Stellard
57e8e4e921 R600/SI: Handle arbitrary destination type in SITargetLowering::adjustWritemask 
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181268
 2013-05-06 23:02:15 +00:00
Tom Stellard
d2ec929c52 R600/SI: Add intrinsic for texture image loading 
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181267
 2013-05-06 23:02:12 +00:00
Tom Stellard
4ed2501894 R600/SI: Add pattern for uint_to_fp 
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181266
 2013-05-06 23:02:07 +00:00
Tom Stellard
7d53018f9b R600/SI: Add patterns for integer maxima / minima 
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181265
 2013-05-06 23:02:04 +00:00
Tom Stellard
2c5ed6e6ce R600/SI: Add pattern for AMDGPU.trunc intrinsic 
Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 181263
 2013-05-06 23:02:00 +00:00
Tom Stellard
740d847e2c R600: Remove dead code from the CodeEmitter v2 
v2:
  - Replace switch statement with TSFlags query

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181229
 2013-05-06 17:50:57 +00:00
Tom Stellard
fb8e73f3af R600: Emit config values in register / value pairs 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181228
 2013-05-06 17:50:51 +00:00
Tom Stellard
6c3f6e1b02 R600: Stop emitting the instruction type byte before each instruction 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181225
 2013-05-06 17:50:44 +00:00
Tom Stellard
ebe049fd75 R600: Emit ISA for CALL_FS_* instructions 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 181223
 2013-05-06 17:50:26 +00:00
Tom Stellard
2165728987 R600: Expand vector or, shl, srl, and xor nodes 
llvm-svn: 181035
 2013-05-03 17:21:31 +00:00
Tom Stellard
9015d64c2e R600: BFI_INT is a vector-only instruction 
llvm-svn: 181034
 2013-05-03 17:21:24 +00:00
Tom Stellard
f2fd0109a0 R600: Add pattern for SHA-256 Ma function 
This can be optimized using the BFI_INT instruction.

llvm-svn: 181033
 2013-05-03 17:21:20 +00:00
Tom Stellard
00f307d8e4 R600: Clean up comments in Processors.td 
llvm-svn: 181032
 2013-05-03 17:21:14 +00:00
Vincent Lejeune
5d7b2a4aea R600: Signed literals are 64bits wide 
llvm-svn: 180960
 2013-05-02 21:53:03 +00:00
Vincent Lejeune
3ff31b75b3 R600: If previous bundle is dot4, PV valid chan is always X 
llvm-svn: 180959
 2013-05-02 21:52:55 +00:00
Vincent Lejeune
33415b0699 R600: Improve asmPrint of ALU clause 
llvm-svn: 180957
 2013-05-02 21:52:40 +00:00
Vincent Lejeune
62da1453e1 R600: Prettier asmPrint of Alu 
llvm-svn: 180956
 2013-05-02 21:52:30 +00:00
Tom Stellard
6f9f86852b R600: Use new tablegen syntax for patterns 
All but two patterns have been converted to the new syntax.  The
remaining two patterns will require COPY_TO_REGCLASS instructions, which
the VLIW DAG Scheduler cannot handle.

llvm-svn: 180922
 2013-05-02 15:30:12 +00:00
Tom Stellard
ccaeffd7d5 R600/SI: remove nonsense select pattern 
Fortunately this pattern never matched, otherwise
we would have generated incorrect code.

Signed-off-by: Christian K??nig <christian.koenig@amd.com>
llvm-svn: 180921
 2013-05-02 15:30:07 +00:00
Vincent Lejeune
8054d1e2f8 R600: Always use texture cache for compute shaders 
This will improve the performance of memory reads.

llvm-svn: 180762
 2013-04-30 00:14:44 +00:00
Vincent Lejeune
29f24e0ce8 R600: use native for alu 
llvm-svn: 180761
 2013-04-30 00:14:38 +00:00
Vincent Lejeune
c6ba980992 R600: Packetize instructions 
llvm-svn: 180760
 2013-04-30 00:14:27 +00:00
Vincent Lejeune
176c8200bc R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips 
llvm-svn: 180759
 2013-04-30 00:14:17 +00:00
Vincent Lejeune
7878fed9de R600: Add a Bank Swizzle operand 
llvm-svn: 180758
 2013-04-30 00:14:08 +00:00
Vincent Lejeune
b2f40c2a8c R600: Take inner dependency into tex/vtx clauses 
llvm-svn: 180757
 2013-04-30 00:14:00 +00:00
Vincent Lejeune
4d300cefe8 R600: Turn TEX/VTX into native instructions 
llvm-svn: 180756
 2013-04-30 00:13:53 +00:00
Vincent Lejeune
e641cd06c9 R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions 
v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache

llvm-svn: 180755
 2013-04-30 00:13:39 +00:00
Vincent Lejeune
1b276d48e1 R600: Add some new processor variants 
llvm-svn: 180753
 2013-04-30 00:13:27 +00:00
Vincent Lejeune
fabf120f32 R600: Clean up instruction class definitions 
llvm-svn: 180752
 2013-04-30 00:13:20 +00:00
Vincent Lejeune
f8d86cf88b R600: config section now reports use of killgt 
llvm-svn: 180751
 2013-04-30 00:13:13 +00:00
Tom Stellard
33e7a52e1c R600: Use correct CF_END instruction on Northern Island GPUs 
llvm-svn: 180735
 2013-04-29 22:23:58 +00:00
Tom Stellard
a22d2b47f3 R600: Fix encoding of CF_END_{EG, R600} instructions 
The EOP bit was not being encoded.

llvm-svn: 180734
 2013-04-29 22:23:54 +00:00
Tom Stellard
de2ad0a8f1 R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE 
We need to intialize this to something and since clang does not set
the shader type attribute and clang is used only for compute shaders,
initializing it to COMPUTE seems like the best choice.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 180620
 2013-04-26 18:32:24 +00:00
Tom Stellard
222f7ab2fb R600: Initialize BooleanVectorContents 
Fixes test/CodeGen/R600/setcc.ll

llvm-svn: 180231
 2013-04-24 23:56:18 +00:00
Tom Stellard
48d161332e R600: Use SHT_PROGBITS for the .AMDGPU.config section 
The libelf implementation that is distributed here:
http://www.mr511.de/software/english.html
will not parse sections that are marked SHT_NULL.

llvm-svn: 180230
 2013-04-24 23:56:14 +00:00
Vincent Lejeune
3666f07489 R600: Use .AMDGPU.config section to emit stacksize 
llvm-svn: 180124
 2013-04-23 17:34:12 +00:00
Vincent Lejeune
e5ba5f1b14 R600: Add CF_END 
llvm-svn: 180123
 2013-04-23 17:34:00 +00:00
Matt Arsenault
b7287bba9b Remove unused DwarfSectionOffsetDirective string 
The value isn't actually used, and setting it emits a COFF specific
directive.

llvm-svn: 180064
 2013-04-22 22:49:11 +00:00
Michael Liao
3b258b6b24 ArrayRefize getMachineNode(). No functionality change. 
llvm-svn: 179901
 2013-04-19 22:22:57 +00:00
Tom Stellard
017c53ebbd R600: Add pattern for the BFI_INT instruction 
llvm-svn: 179830
 2013-04-19 02:11:06 +00:00
Tom Stellard
db47653487 R600/SI: Use InstFlag for VOP3 modifier operands 
InstFlag has a default value of 0 and will simplify the VOP3 patterns.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179829
 2013-04-19 02:11:00 +00:00
Vincent Lejeune
cd0483fb18 R600: Make Export Instruction not duplicable 
llvm-svn: 179686
 2013-04-17 15:17:39 +00:00
Vincent Lejeune
a1a9b1752d R600: Export is emitted as a CF_NATIVE inst 
llvm-svn: 179685
 2013-04-17 15:17:32 +00:00
Vincent Lejeune
966453087f R600: Emit used GPRs count 
llvm-svn: 179684
 2013-04-17 15:17:25 +00:00
Tom Stellard
bd67f8cd81 R600/SI: Emit config values in register value pairs. 
Instead of emitting config values in a predefined order, the code
emitter will now emit a 32-bit register index followed by the 32-bit
config value.

llvm-svn: 179546
 2013-04-15 17:51:35 +00:00
Tom Stellard
a44e2e18a1 R600/SI: Emit configuration value in the .AMDGPU.config ELF section 
llvm-svn: 179545
 2013-04-15 17:51:30 +00:00
Tom Stellard
cb4468b00a R600: Emit ELF formatted code rather than raw ISA. 
llvm-svn: 179544
 2013-04-15 17:51:21 +00:00
NAKAMURA Takumi
c9309ae42b R600ControlFlowFinalizer.cpp: Fix a warning. [-Wunused-variable] 
llvm-svn: 179263
 2013-04-11 04:16:27 +00:00
NAKAMURA Takumi
1837d9ec3e Whitespace. 
llvm-svn: 179262
 2013-04-11 04:16:22 +00:00
Michel Danzer
c1562afdde R600/SI: Add pattern for AMDGPUurecip 
21 more little piglits with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 179186
 2013-04-10 17:17:56 +00:00
Vincent Lejeune
daa1e69206 R600: Add VTX_READ_* and RAT_WRITE_CACHELESS_* when computing cf addr 
llvm-svn: 179174
 2013-04-10 13:29:20 +00:00
Christian Konig
f40f671bab R600/SI: dynamical figure out the reg class of MIMG 
Depending on the number of bits set in the writemask.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179166
 2013-04-10 08:39:16 +00:00
Christian Konig
76cd1a76c2 R600/SI: adjust writemask to only the used components 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179165
 2013-04-10 08:39:08 +00:00
Christian Konig
ffddac18a4 R600/SI: remove image sample writemask 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179164
 2013-04-10 08:39:01 +00:00
Vincent Lejeune
cbdacdc057 R600: Control Flow support for pre EG gen 
llvm-svn: 179020
 2013-04-08 13:05:49 +00:00
Tom Stellard
8ad4f7c25b R600/SI: Add support for buffer stores v2 
v2:
  - Use the ADDR64 bit

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178931
 2013-04-05 23:31:51 +00:00
Tom Stellard
379d612a66 R600/SI: Use same names for corresponding MUBUF operands and encoding fields 
The code emitter knows how to encode operands whose name matches one of
the encoding fields.  If there is no match, the code emitter relies on
the order of the operand and field definitions to determine how operands
should be encoding.  Matching by order makes it easy to accidentally break
the instruction encodings, so we prefer to match by name.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178930
 2013-04-05 23:31:44 +00:00
Tom Stellard
7dd3fda85d R600: Add RV670 processor 
This is an R600 GPU with double support.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178929
 2013-04-05 23:31:40 +00:00
Tom Stellard
917d7412f1 R600/SI: Add processor types for each SI variant 
Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178928
 2013-04-05 23:31:35 +00:00
Tom Stellard
17fba38a4b R600/SI: Avoid generating S_MOVs with 64-bit immediates v2 
SITargetLowering::analyzeImmediate() was converting the 64-bit values
to 32-bit and then checking if they were an inline immediate.  Some
of these conversions caused this check to succeed and produced
S_MOV instructions with 64-bit immediates, which are illegal.

v2:
  - Clean up logic

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178927
 2013-04-05 23:31:20 +00:00
Vincent Lejeune
3a22d07044 R600: Use a mask for offsets when encoding instructions 
llvm-svn: 178763
 2013-04-04 14:00:09 +00:00
Vincent Lejeune
d5f0b3821e R600: Fix wrong address when substituting ENDIF 
llvm-svn: 178762
 2013-04-04 14:00:03 +00:00
Vincent Lejeune
a680946842 R600: Take export into account when computing cf address 
llvm-svn: 178761
 2013-04-04 13:59:59 +00:00
Vincent Lejeune
6a4ef74f44 R600: Fix last ALU of a clause being emitted in a separate clause 
llvm-svn: 178675
 2013-04-03 18:24:47 +00:00
Vincent Lejeune
9bc67cfa08 R600: Factorize maximum alu per clause in a single location 
llvm-svn: 178667
 2013-04-03 16:49:34 +00:00
Vincent Lejeune
bab4692335 R600: Simplify data structure and add DEBUG to R600ControlFlowFinalizer 
llvm-svn: 178665
 2013-04-03 16:24:09 +00:00
Vincent Lejeune
6b257b347d R600: Consider KILLGT as an ALU instruction 
Mesa does not override llvm behavior wrt KILLGT anymore so llvm
has to handle KILLGT on its own.

llvm-svn: 178664
 2013-04-03 16:24:04 +00:00
NAKAMURA Takumi
9ce5fbdaab Target/R600: Fix CMake build to add missing files. 
llvm-svn: 178508
 2013-04-01 22:05:58 +00:00
Vincent Lejeune
dc0e12bd5b R600: Add support for native control flow 
llvm-svn: 178505
 2013-04-01 21:48:05 +00:00
Vincent Lejeune
8b37b0c9c6 R600/SI: Share code recording ShaderTypeAttribute between generations 
llvm-svn: 178504
 2013-04-01 21:47:53 +00:00
Vincent Lejeune
11918406b3 R600: Emit CF_ALU and use true kcache register. 
llvm-svn: 178503
 2013-04-01 21:47:42 +00:00
Vincent Lejeune
30dc10604e R600: Emit native instructions for tex 
llvm-svn: 178452
 2013-03-31 19:33:04 +00:00
Eric Christopher
43672e076b These two are default in the constructor for MCAsmInfo. 
llvm-svn: 178293
 2013-03-28 21:37:18 +00:00
Christian Konig
510c335233 R600/SI: add SETO/SETUO patterns 
6 more piglit tests.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 178145
 2013-03-27 15:27:31 +00:00
Christian Konig
fb305cbcea R600/SI: add cummuting of rev instructions 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 178127
 2013-03-27 09:12:59 +00:00
Christian Konig
231ee3f1ae R600/SI: add mulhu/mulhs patterns 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 178126
 2013-03-27 09:12:51 +00:00
Christian Konig
c90c1dabd1 R600/SI: add srl/sha patterns for SI 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 178125
 2013-03-27 09:12:44 +00:00
NAKAMURA Takumi
f508219ce8 R600/SIMCCodeEmitter.cpp: Prune a couple of unused members, STI and Ctx. [-Wunused-private-field] 
llvm-svn: 178065
 2013-03-26 19:42:48 +00:00
Christian Konig
3548ce0f01 R600/SI: improve post ISel folding 
Not only fold immediates, but avoid unnecessary copies as well.

Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178024
 2013-03-26 14:04:17 +00:00
Christian Konig
d8fe8c3e97 R600/SI: improve vector interpolation 
Prevent loading M0 multiple times.

Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178023
 2013-03-26 14:04:12 +00:00
Christian Konig
ed8b6b28fe R600/SI: avoid unecessary subreg extraction in IMAGE_SAMPLE 
Just define the address as unknown instead of VReg_32.

Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178022
 2013-03-26 14:04:07 +00:00
Christian Konig
0560f719ba R600/SI: switch back to RegPressure scheduling 
Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178021
 2013-03-26 14:04:02 +00:00
Christian Konig
ab305ffb6a R600/SI: mark most intrinsics as readnone v2 
They read from constant register space anyway.

v2: fix lit tests

Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178020
 2013-03-26 14:03:57 +00:00
Christian Konig
cbe34c372c R600/SI: replace WQM intrinsic 
Just enable WQM when we see an LDS interpolation instruction.

Signed-off-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178019
 2013-03-26 14:03:50 +00:00
Christian Konig
b0fdffcca6 R600/SI: fix ELSE pseudo op handling 
Restore the EXEC mask early, otherwise a copy might end up not beeing executed.

Candidate for the mesa stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 178018
 2013-03-26 14:03:44 +00:00
Christian Konig
eefc5141a1 R600: fix DenseMap with pointer key iteration in the structurizer 
Use a MapVector on types where the iteration order matters.
Otherwise we doesn't always produce a deterministic output.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 177999
 2013-03-26 10:24:20 +00:00
Michel Danzer
2f63b04c7c R600: Use legacy (0 * anything = 0) MUL instructions for pow intrinsics 
Fixes wrong lighting in some corner cases with r600g and radeonsi, e.g.
manifested by failure of two piglit/glean tests and intermittent black
patches in many apps.

Tested on SI and RS880.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62012 [radeonsi]
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58150 [r600g]

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 177730
 2013-03-22 14:09:10 +00:00
Christian Konig
0a9c8621db R600/SI: implement indirect adressing for SI 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 177277
 2013-03-18 11:34:16 +00:00
Christian Konig
ff83146b66 R600/SI: add float vector types 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 177276
 2013-03-18 11:34:10 +00:00
Christian Konig
c6dc69ea48 R600/SI: add shl pattern 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 177275
 2013-03-18 11:34:05 +00:00
Christian Konig
d88cf7af71 R600/SI: add BUFFER_LOAD_DWORD pattern 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 177274
 2013-03-18 11:34:00 +00:00
Christian Konig
56e24dd872 R600/SI: implement SI.load.const intrinsic 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 177273
 2013-03-18 11:33:55 +00:00
Christian Konig
4450771405 R600/SI: enable all S_LOAD and S_BUFFER_LOAD opcodes 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 177272
 2013-03-18 11:33:50 +00:00
Christian Konig
b06666d87e R600/SI: fix inserting waits for all defines 
Unfortunately the previous fix for inserting waits for unordered
defines wasn't sufficient, cause it's possible that even ordered
defines are only partially used (or not used at all).

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 177271
 2013-03-18 11:33:45 +00:00
Vincent Lejeune
cd12dadb5c R600: Factorize code handling Const Read Port limitation 
llvm-svn: 177078
 2013-03-14 15:50:45 +00:00
Vincent Lejeune
44444f0162 R600: Remove unused Outputs variable 
llvm-svn: 176967
 2013-03-13 20:13:25 +00:00
Vincent Lejeune
712c6f4f44 R600: Fix JUMP handling so that MachineInstr verification can occur 
This allows R600 Target to use the newly created -verify-misched llc flag

llvm-svn: 176819
 2013-03-11 18:15:06 +00:00
NAKAMURA Takumi
ea460bbbe4 R600MachineScheduler.cpp: Fix use cases of dbgs(). Don't include <iostream> here. 
llvm-svn: 176797
 2013-03-11 08:19:28 +00:00
Tom Stellard
963bae7608 R600: Optimize another selectcc case 
fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
     selectcc x, y, a, b, cc

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 176700
 2013-03-08 15:37:11 +00:00
Tom Stellard
2eae31f648 R600: Improve custom lowering of select_cc 
Two changes:
1. Prefer SET* instructions when possible
2. Handle the CND*_INT case with floating-point args

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 176699
 2013-03-08 15:37:09 +00:00
Tom Stellard
3f88348d66 R600: Change operation action from Custom to Expand for BR_CC 
Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 176698
 2013-03-08 15:37:07 +00:00
Tom Stellard
54e0b366e8 R600: Change operation action from Custom to Expand for SETCC 
Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 176697
 2013-03-08 15:37:05 +00:00
Tom Stellard
62d91841c1 R600: Set BooleanContents to ZeroOrNegativeOneBooleanContent 
Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 176696
 2013-03-08 15:37:03 +00:00
Michel Danzer
395066d259 R600/SI: Use source scheduler 
This is certainly not the last word on scheduling for this target, but
right now this allows a few apps to run / finish with radeonsi, most
notably UT2004 / Lightsmark. They fail to compile some shaders with the
default scheduler because it ends up trying to spill registers, which
we don't support yet (and which is probably a bad idea in general for
performance if it can be avoided).

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 176687
 2013-03-08 10:58:01 +00:00
Christian Konig
02d24d8232 R600/SI: rework input interpolation v2 
v2: update CMakeLists.txt as well

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 176626
 2013-03-07 09:04:14 +00:00
Christian Konig
943b5734b1 R600/SI: remove SI_vs_load_buffer_index 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 176625
 2013-03-07 09:04:04 +00:00
Christian Konig
d4afea4949 R600/SI: remove SGPR address space v2 
v2: fix R600 regressions

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 176624
 2013-03-07 09:03:59 +00:00
Christian Konig
b39290c18e R600/SI: add proper formal parameter handling for SI 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 176623
 2013-03-07 09:03:52 +00:00