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Commit Graph

2102 Commits

Author SHA1 Message Date
Jim Grosbach
f3607eac5d NEON Two-operand assembly aliases for VSRA.
llvm-svn: 148821
2012-01-24 17:55:36 +00:00
Jim Grosbach
47f7ce80b8 Remove redundant test file.
llvm-svn: 148820
2012-01-24 17:55:32 +00:00
Jim Grosbach
630dd380c7 NEON Two-operand assembly aliases for VSLI.
llvm-svn: 148819
2012-01-24 17:49:15 +00:00
Jim Grosbach
42c0f99aa0 NEON Two-operand assembly aliases for VSRI.
llvm-svn: 148818
2012-01-24 17:46:58 +00:00
Jim Grosbach
703b0bb646 Tidy up.
llvm-svn: 148817
2012-01-24 17:46:54 +00:00
Jim Grosbach
3be662b372 NEON VST4(multiple 4 element structures) assembly parsing.
llvm-svn: 148764
2012-01-24 00:58:13 +00:00
Jim Grosbach
ca32a49eb5 NEON VLD4(multiple 4 element structures) assembly parsing.
llvm-svn: 148762
2012-01-24 00:43:17 +00:00
Jim Grosbach
a4687dcf5a NEON VST3(single element from one lane) assembly parsing.
llvm-svn: 148755
2012-01-24 00:07:41 +00:00
Jim Grosbach
048162ddf9 NEON VST3(multiple 3-element structures) assembly parsing.
llvm-svn: 148748
2012-01-23 23:45:44 +00:00
Jim Grosbach
8035fac461 NEON VLD3(multiple 3-element structures) assembly parsing.
llvm-svn: 148745
2012-01-23 23:20:46 +00:00
Devang Patel
327773a25b Intel syntax: Robustify parsing of memory operand's displacement experssion.
llvm-svn: 148737
2012-01-23 22:35:25 +00:00
Jim Grosbach
dd667a11d3 NEON VLD3 lane-indexed assembly parsing and encoding.
llvm-svn: 148734
2012-01-23 21:53:26 +00:00
Rafael Espindola
9f3a003d3c Add support for .cfi_signal_frame. Fixes pr11762.
llvm-svn: 148733
2012-01-23 21:51:52 +00:00
Devang Patel
3c6289f43a Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]
llvm-svn: 148721
2012-01-23 20:20:06 +00:00
Jim Grosbach
0eeacbfe2e Simplify some NEON assembly pseudo definitions.
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.

llvm-svn: 148718
2012-01-23 19:39:08 +00:00
Devang Patel
9698de5bf3 Intel syntax: Parse segment registers.
llvm-svn: 148712
2012-01-23 18:31:58 +00:00
Devang Patel
0ecda3fc14 Intel syntax: Robustify register parsing.
llvm-svn: 148591
2012-01-20 22:32:05 +00:00
Devang Patel
0638a44a24 Intel syntax: Parse ... PTR [-8]
llvm-svn: 148570
2012-01-20 21:21:01 +00:00
Devang Patel
e836c95860 Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.
llvm-svn: 148569
2012-01-20 21:14:06 +00:00
Jim Grosbach
4579f05f36 NEON use vmov.i32 to splat some f32 values into vectors.
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.

rdar://10616677

llvm-svn: 148556
2012-01-20 18:09:51 +00:00
Devang Patel
b42cea31aa Post process 'and', 'sub' instructions and select better encoding, if available.
llvm-svn: 148489
2012-01-19 18:40:55 +00:00
Devang Patel
27ef211648 Intel syntax: There is no need to create unary expr for simple negative displacement.
llvm-svn: 148486
2012-01-19 18:15:51 +00:00
Devang Patel
999eaa4b85 Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available.
llvm-svn: 148485
2012-01-19 17:53:25 +00:00
Jim Grosbach
48afa48c3e Add testcase.
llvm-svn: 148454
2012-01-19 01:36:59 +00:00
Jim Grosbach
b7ab9edb4e Thumb2 alternate syntax for LDR(literal) and friends.
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".

rdar://10250964

llvm-svn: 148432
2012-01-18 22:46:46 +00:00
Devang Patel
ee49d825b1 Process instructions after match to select alternative encoding which may be more desirable.
llvm-svn: 148431
2012-01-18 22:42:29 +00:00
Jim Grosbach
a1e220fa82 Thumb2 relaxation for LDR(literal).
If the fixup is out of range for the Thumb1 instruction, relax it
to the Thumb2 encoding instead.

rdar://10711829

llvm-svn: 148424
2012-01-18 21:54:16 +00:00
Jim Grosbach
e6d2a7a097 MC tweak symbol difference resolution for non-local symbols.
When the non-local symbol in the expression is in the same fragment
as the second symbol, the assembler can still evaluate the expression
without needing a relocation.

For example, on ARM:
_foo:
	ldr lr, (_foo - 4)

rdar://10348687

llvm-svn: 148341
2012-01-17 22:14:39 +00:00
Jim Grosbach
095e519996 Tidy up.
llvm-svn: 148339
2012-01-17 22:03:42 +00:00
Devang Patel
e03a4f051f Intel syntax: Fix parser match class to check memory operand size.
llvm-svn: 148338
2012-01-17 21:48:03 +00:00
Devang Patel
4585b536ee Intel syntax: Parse "BYTE PTR [RDX + RCX]"
llvm-svn: 148334
2012-01-17 21:25:10 +00:00
Devang Patel
388aa8feb0 Intel syntax: Do not unncessarily create plus expression for memory operand displacement.
llvm-svn: 148321
2012-01-17 19:08:07 +00:00
Devang Patel
84d275a823 Intel syntax: Ignore mnemonic aliases.
llvm-svn: 148316
2012-01-17 18:30:45 +00:00
Devang Patel
b1e07175c4 Intel syntax: Robustify memory operand parsing.
llvm-svn: 148312
2012-01-17 18:00:18 +00:00
Devang Patel
79b7ed0c82 Add new test.
llvm-svn: 148128
2012-01-13 18:45:31 +00:00
Devang Patel
807fee533d Remove test case, as Chris suggested.
llvm-svn: 148039
2012-01-12 19:54:02 +00:00
Devang Patel
3f85289ef8 Add test case to check intel syntax parsing.
llvm-svn: 148034
2012-01-12 18:40:46 +00:00
Kevin Enderby
9c7eec9282 The error check for using -g with a .s file already containing dwarf .file
directives was in the wrong place and getting triggered incorectly with a
cpp .file directive.  This change fixes that and adds a test case.

llvm-svn: 147951
2012-01-11 18:04:47 +00:00
Rafael Espindola
c326212da6 Add big endian mips support. Based on a patch by Jack Carter.
llvm-svn: 147924
2012-01-11 04:04:14 +00:00
Rafael Espindola
fff89417f5 Add the skeleton of an asm parser for mips.
llvm-svn: 147923
2012-01-11 03:56:41 +00:00
Kevin Enderby
75f4b470f9 Various crash reporting tools have a problem with the dwarf generated for
assembly source when it generates the TAG_subprogram dwarf debug info for
the labels that have nothing between them as in this bit of assembly source:

% cat ZeroLength.s 
_func1:
_func2:
 nop

One solution would be to not emit the subsequent labels with the same address
and use the next label with a different address or the end of the section for
the AT_high_pc value of the TAG_subprogram.

Turns out in llvm-mc it is not possible in all cases to determine of two
symbols have the same value at the point we put out the TAG_subprogram dwarf
debug info.

So we will have llvm-mc instead of putting out TAG_subprogram's put out
DW_TAG_label's.  And the DW_TAG_label does not have a AT_high_pc value which
avoids the problem.

This commit is only the functional change to make the diffs clear as to what is
really being changed.  The next commit will be to clean up the names of such
things like MCGenDwarfSubprogramEntry to something like MCGenDwarfLabelEntry.

rdar://10666925

llvm-svn: 147860
2012-01-10 17:52:29 +00:00
Rafael Espindola
2d545fa143 Split Finish into Finish and FinishImpl to have a common place to do end of
file error checking. Use that to error on an unfinished cfi_startproc.

The error is not nice, but is already better than a segmentation fault.

llvm-svn: 147717
2012-01-07 03:13:18 +00:00
Craig Topper
b4db8689ee Add disassembler support for VPERMIL2PD and VPERMIL2PS.
llvm-svn: 147368
2011-12-30 06:23:39 +00:00
Craig Topper
089be4fefa Add FMA4 instructions to disassembler.
llvm-svn: 147367
2011-12-30 05:20:36 +00:00
Rafael Espindola
db7319d272 Implement cfi_restore. Patch by Brian Anderson!
llvm-svn: 147356
2011-12-29 21:43:03 +00:00
Craig Topper
97e84c23a1 Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions.
llvm-svn: 147353
2011-12-29 20:43:40 +00:00
Rafael Espindola
27298c6f33 Implement .cfi_escape. Patch by Brian Anderson!
llvm-svn: 147352
2011-12-29 20:24:47 +00:00
Craig Topper
bcfd070378 Expose FMA3 instructions to the disassembler.
llvm-svn: 147351
2011-12-29 20:03:14 +00:00
Jim Grosbach
a678ad9ecc ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
rdar://10558523

llvm-svn: 147189
2011-12-22 22:19:05 +00:00
Rafael Espindola
eba1c0eb00 Fix incorrect relocation generation. Patch by Kristof Beyls.
Fixes PR11214.

llvm-svn: 147180
2011-12-22 21:36:43 +00:00
Jim Grosbach
100e3aaffa ARM assembler should accept shift-by-zero for any shifted-immediate operand.
Just treat it as-if the shift wasn't there at all. 'as' compatibility.

rdar://10604767

llvm-svn: 147153
2011-12-22 18:04:04 +00:00
Akira Hatanaka
e7bcf63d98 Local dynamic TLS model for direct object output. Create the correct TLS MIPS
ELF relocations.

Patch by Jack Carter.

llvm-svn: 147118
2011-12-22 01:05:17 +00:00
Jim Grosbach
7d31680e2d ARM VFP optional data type on VMOV GPR<-->SPR.
llvm-svn: 147104
2011-12-21 23:24:15 +00:00
Jim Grosbach
2bbc41fa26 Thumb2 assembly parsing of 'mov rd, rn, rrx'.
Maps to the RRX instruction. Missed this case earlier.

rdar://10615373

llvm-svn: 147096
2011-12-21 21:04:19 +00:00
Jim Grosbach
91faf5d15f Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
These map to the ASR, LSR, LSL, ROR instruction definitions.

rdar://10615373

llvm-svn: 147094
2011-12-21 20:54:00 +00:00
Jim Grosbach
f7236d1084 ARM NEON assmebly parsing for VLD2 to all lanes instructions.
llvm-svn: 147069
2011-12-21 19:40:55 +00:00
Jim Grosbach
6bd1044b03 ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
llvm-svn: 147025
2011-12-21 00:38:54 +00:00
Jim Grosbach
0768f2c420 Enable and fix a test.
llvm-svn: 147011
2011-12-20 23:20:00 +00:00
Jim Grosbach
8978194025 ARM assembly parsing and encoding for VST2 single-element, double spaced.
llvm-svn: 146990
2011-12-20 20:46:29 +00:00
Jim Grosbach
3f48367a1b ARM enable a few more tests.
llvm-svn: 146985
2011-12-20 20:03:00 +00:00
Jim Grosbach
8156a5dcee ARM assembly parsing and encoding for VLD2 single-element, double spaced.
llvm-svn: 146983
2011-12-20 19:21:26 +00:00
Jim Grosbach
3f5493c136 ARM assembly shifts by zero should be plain 'mov' instructions.
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.

rdar://10604663

llvm-svn: 146937
2011-12-20 00:59:38 +00:00
Jim Grosbach
343f270350 ARM assembly parsing and encoding support for LDRD(label).
rdar://9932658

llvm-svn: 146921
2011-12-19 23:06:24 +00:00
Jim Grosbach
797a88284c ARM NEON two-operand aliases for VPADD.
rdar://10602276

llvm-svn: 146895
2011-12-19 19:51:03 +00:00
Jim Grosbach
520db82971 ARM NEON implied destination aliases for VMAX/VMIN.
llvm-svn: 146885
2011-12-19 18:57:38 +00:00
Jim Grosbach
f4ca84a7ab ARM NEON relax parse time diagnostics for alignment specifiers.
There's more variation that we need to handle. Error checking will need
to be on operand predicates.

llvm-svn: 146884
2011-12-19 18:31:43 +00:00
Rafael Espindola
549d0683b1 Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the
asm parsing and testcase.

llvm-svn: 146801
2011-12-17 01:14:52 +00:00
Eli Friedman
f626b19bda Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.
llvm-svn: 146709
2011-12-15 23:46:18 +00:00
Jim Grosbach
30f4b285a6 ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.
llvm-svn: 146699
2011-12-15 22:56:33 +00:00
Jim Grosbach
b79d2a8f50 ARM NEON VTBL/VTBX assembly parsing and encoding.
llvm-svn: 146691
2011-12-15 22:27:11 +00:00
Jim Grosbach
75db252aee ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
llvm-svn: 146605
2011-12-14 23:25:46 +00:00
Kevin Enderby
bc6d6388c2 Improve the implementation of .incbin directive by replacing a loop by using
getStreamer().EmitBytes.  Suggestion by Benjamin Kramer!

llvm-svn: 146599
2011-12-14 22:34:45 +00:00
Jim Grosbach
83520a5b70 ARM NEON fix alignment encoding for VST2 w/ writeback.
Add tests for w/ writeback instruction parsing and encoding.

llvm-svn: 146594
2011-12-14 21:49:24 +00:00
Kevin Enderby
b0b669eb26 Add the .incbin directive which takes the binary data from a file and emits
it to the streamer.  rdar://10383898

llvm-svn: 146592
2011-12-14 21:47:48 +00:00
Jim Grosbach
44829ab9d2 ARM NEON VST2 assembly parsing and encoding.
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.

llvm-svn: 146579
2011-12-14 19:35:22 +00:00
Jim Grosbach
54372eef76 ARM/Thumb2 'cmp rn, #imm' alias to cmn.
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.

rdar://10552389

llvm-svn: 146567
2011-12-14 17:30:24 +00:00
Jim Grosbach
628ae663ef ARM assembler support for the target-specific .req directive.
rdar://10549683

llvm-svn: 146543
2011-12-14 02:16:11 +00:00
Jim Grosbach
089ad574d8 Thumb2 assembler aliases for "mov(shifted register)"
rdar://10549767

llvm-svn: 146520
2011-12-13 22:45:11 +00:00
Jim Grosbach
bd33fc6efd ARM LDM/STM system instruction variants.
rdar://10550269

llvm-svn: 146519
2011-12-13 21:48:29 +00:00
Jim Grosbach
7db50010cc Test for 146516
llvm-svn: 146517
2011-12-13 21:06:59 +00:00
Jim Grosbach
13d3509445 ARM thumb2 parsing of "rsb rd, rn, #0".
rdar://10549741

llvm-svn: 146515
2011-12-13 20:50:38 +00:00
Jim Grosbach
dfec87fe2f ARM NEON two-operand aliases for VQDMULH.
llvm-svn: 146514
2011-12-13 20:40:37 +00:00
Jim Grosbach
0ba5ba4535 ARM pre-UAL NEG mnemonic for convenience when porting old code.
llvm-svn: 146511
2011-12-13 20:23:22 +00:00
Akira Hatanaka
23f439aca1 Add test/MC/Mips/dg.exp.
llvm-svn: 146472
2011-12-13 04:12:49 +00:00
Akira Hatanaka
a9290d5ab9 Move direct object emitter test to directory test/MC/Mips. Rename it to
elf-relsym.ll.

llvm-svn: 146470
2011-12-13 03:50:34 +00:00
Nick Lewycky
90a4c39a28 Don't rely on a particular version string for llvm.
llvm-svn: 146456
2011-12-13 00:34:14 +00:00
Jan Sjödin
b9e2da0d9a XOP instructions and encoding tests.
llvm-svn: 146407
2011-12-12 19:37:49 +00:00
Roman Divacky
a450b8b2c8 Add support for gnu_indirect_function.
llvm-svn: 146377
2011-12-12 17:34:04 +00:00
Chandler Carruth
afb8199f38 Don't assume things about the exact details of the LLVM version number,
such as what VCS information is attached.

llvm-svn: 146333
2011-12-10 21:40:31 +00:00
Rafael Espindola
9b9d35cc05 Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas
does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.

llvm-svn: 146311
2011-12-10 02:28:43 +00:00
Jim Grosbach
356ad6d232 ARM assembly aliases for BIC<-->AND (immediate).
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.

rdar://10550057

llvm-svn: 146283
2011-12-09 22:02:17 +00:00
Jim Grosbach
489e81da30 ARM assembly parsing and encoding for VLD2 with writeback.
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.

Add tests for the instruction variants now supported.

llvm-svn: 146278
2011-12-09 21:28:25 +00:00
Rafael Espindola
b5c511f7b7 Handle reloc_signed_4byte in here. Not doing so was a regression from my
previous commit. It is strange that we see it in 32 bits. We already
have a fixme about it.

llvm-svn: 146273
2011-12-09 19:57:29 +00:00
Kevin Enderby
63cf89d532 The second part of support for generating dwarf for assembly source files. This
generates the dwarf Compile Unit DIE and a dwarf subprogram DIE for each
non-temporary label.

The next part will be to get the clang driver to enable this when assembling
a .s file.  rdar://9275556

llvm-svn: 146262
2011-12-09 18:09:40 +00:00
Rafael Espindola
82e22767cf Handle the case of the magical _GLOBAL_OFFSET_TABLE_ showing up in a
symbol difference. This matches gas behavior and fixes PR11513.

We still don't handle _GLOBAL_OFFSET_TABLE_ in data sections.

llvm-svn: 146238
2011-12-09 03:03:58 +00:00
Jim Grosbach
62873cae5f ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
llvm-svn: 146194
2011-12-08 22:19:04 +00:00
Jim Grosbach
a33fa8aa88 ARM VSHR implied destination operand form aliases.
llvm-svn: 146192
2011-12-08 22:06:06 +00:00
Jim Grosbach
af9cc198cf Tidy up a bit.
llvm-svn: 146190
2011-12-08 22:04:40 +00:00
Jim Grosbach
78020c4642 ARM VSUB implied destination operand form aliases.
llvm-svn: 146182
2011-12-08 20:56:26 +00:00
Jim Grosbach
957be45ccf Tidy up a bit.
llvm-svn: 146181
2011-12-08 20:53:19 +00:00
Jim Grosbach
a33af36947 ARM VQADD implied destination operand form aliases.
llvm-svn: 146179
2011-12-08 20:49:43 +00:00
Jim Grosbach
405e213008 ARM a few more VMUL implied destination operand form aliases.
llvm-svn: 146177
2011-12-08 20:42:35 +00:00
Jim Grosbach
e1fe053f6e ARM NEON two-operand aliases for VSHL(immediate).
llvm-svn: 146125
2011-12-08 01:30:04 +00:00
Jim Grosbach
3e9384b103 ARM NEON two-operand aliases for VSHL(register).
llvm-svn: 146123
2011-12-08 01:12:35 +00:00
Jim Grosbach
3b4d5c0510 ARM optional destination operand variants for VEXT instructions.
llvm-svn: 146114
2011-12-08 00:43:47 +00:00
Jim Grosbach
0c64182f7c Tidy up.
llvm-svn: 146113
2011-12-08 00:41:54 +00:00
Jim Grosbach
c1cf417595 ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
llvm-svn: 146111
2011-12-08 00:31:07 +00:00
Jim Grosbach
6146f79b7d ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
For 'gas' compatibility.

llvm-svn: 146106
2011-12-07 23:40:58 +00:00
Jim Grosbach
dd3788b044 ARM two-operand aliases for VAND/VEOR/VORR instructions.
llvm-svn: 146095
2011-12-07 23:08:12 +00:00
Jim Grosbach
da0a3e310a ARM two-operand aliases for VADDW instructions.
llvm-svn: 146093
2011-12-07 23:01:10 +00:00
Jim Grosbach
ecf9c2bb21 ARM two-operand aliases for VADD instructions.
llvm-svn: 146091
2011-12-07 22:52:54 +00:00
Jim Grosbach
2f57374e32 Darwin assembler improved relocs when w/o subsections_via_symbols.
When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.

llvm-svn: 146054
2011-12-07 19:46:59 +00:00
Jim Grosbach
1ccae84fa7 Thumb2 alias for long-form pop and friends.
rdar://10542474

llvm-svn: 146046
2011-12-07 18:32:28 +00:00
Jim Grosbach
81cb9952c9 ARM support the .arm and .thumb directives for assembly mode switching.
llvm-svn: 146042
2011-12-07 18:04:19 +00:00
Jim Grosbach
3352ab97ca ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
llvm-svn: 146039
2011-12-07 17:51:15 +00:00
Jim Grosbach
61d2b8b2f9 Tidy up. Move MachO tests to MachO directory.
llvm-svn: 146038
2011-12-07 17:50:28 +00:00
NAKAMURA Takumi
ed2be25205 test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it.
FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856)
llvm-svn: 145925
2011-12-06 06:48:26 +00:00
Jim Grosbach
5b4f7d74de ARM mode 'mul' operand ordering tweak.
Same as r145922, just for ARM mode.

llvm-svn: 145923
2011-12-06 05:28:00 +00:00
Jim Grosbach
dc7d42f559 Thumb2: MUL two-operand form encoding operand order fix.
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.

rdar://10532439

llvm-svn: 145922
2011-12-06 05:03:45 +00:00
Jim Grosbach
8bdbe92631 Thumb2 encoding choice correction for PLD.
Using encoding T1 for offset of #0 and encoding T2 for #-0.

rdar://10532413

llvm-svn: 145919
2011-12-06 04:49:29 +00:00
NAKAMURA Takumi
ea8cc0e506 test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM.
MC/MachO assumes x86.

llvm-svn: 145916
2011-12-06 03:56:05 +00:00
Jim Grosbach
0fd3f58ea2 Fix ARM handling of tBcc branch relaxation.
rdar://10069056

llvm-svn: 145885
2011-12-06 01:08:19 +00:00
Jim Grosbach
74bbb6454e Tweak ADDrr fix. Bad check for explicit .w
llvm-svn: 145863
2011-12-05 22:27:04 +00:00
Jim Grosbach
6584358d09 Update tests for r145860. Add a few new ones.
llvm-svn: 145861
2011-12-05 22:21:28 +00:00
Jim Grosbach
655b017748 Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
rdar://10529348

llvm-svn: 145851
2011-12-05 21:06:26 +00:00
Jim Grosbach
9c017fb254 ARM assembly parsing for the rest of the VMUL data type aliases.
Finish up rdar://10522016.

llvm-svn: 145846
2011-12-05 20:29:59 +00:00
Jim Grosbach
6ae4df64e7 ARM tests for VLD1 single lane w/ writeback.
llvm-svn: 145713
2011-12-02 22:03:52 +00:00
Jim Grosbach
a568ef0db6 Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
Add the 16-bit lane variants while I'm at it.

llvm-svn: 145693
2011-12-02 18:52:30 +00:00
Jan Sjödin
2dfb343ffa Support for encoding all FMA4 instructions and tablegen patterns for all
remaining FMA4 instructions and intrinsics with tests.

llvm-svn: 145525
2011-11-30 22:09:42 +00:00
Jim Grosbach
3129a92b38 Add some tests for all-lanes VLD1 parsing.
llvm-svn: 145512
2011-11-30 19:37:38 +00:00
Jim Grosbach
538759efa7 ARM assembly parsing and encoding for four-register VST1.
llvm-svn: 145450
2011-11-29 22:58:48 +00:00
Jim Grosbach
fc7e76b194 Enable some VST1 tests and add a few more.
llvm-svn: 145443
2011-11-29 22:40:32 +00:00
Michael J. Spencer
5fade79478 MC/X86/COFF: Allow quotes in names when targeting MS/Windows,
as MC is the only assembler we support.

This splits MS/Windows and GNU/Windows ASM infos into two seperate classes.
While there is currently only one difference, full MS C++ ABI support will
require many more.

llvm-svn: 145409
2011-11-29 18:00:06 +00:00
Chris Lattner
9d1e8420ff Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic.
llvm-svn: 145171
2011-11-27 06:54:59 +00:00
Wesley Peck
13edec82a8 Add several new instructions supported by the latest MicroBlaze.
These instructions are not generated by the backend yet, this will come in a later commit.

llvm-svn: 145161
2011-11-27 05:16:58 +00:00
Bruno Cardoso Lopes
626d04cc6f This patch contains support for encoding FMA4 instructions and
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.

Patch by Jan Sjodin

llvm-svn: 145133
2011-11-25 19:33:42 +00:00
Benjamin Kramer
d03fc374bd X86: alias cqo to cqto.
llvm-svn: 145121
2011-11-24 12:02:46 +00:00
Jim Grosbach
1b837af2bd Remove obsolete test.
The PLD encoding is checked via the .s file now.

llvm-svn: 144853
2011-11-16 22:50:38 +00:00
Jim Grosbach
fe5f0cfa29 Generalize the fixup info for ARM mode.
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.

llvm-svn: 144852
2011-11-16 22:48:37 +00:00
Jim Grosbach
8fae277866 Update test for r144842.
llvm-svn: 144851
2011-11-16 22:46:27 +00:00
Jim Grosbach
044acb8bee ARM assembly parsing for register range syntax for VLD/VST register lists.
For example,
vld1.f64 {d2-d5}, [r2,:128]!

Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!

It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.

rdar://10451128

llvm-svn: 144727
2011-11-15 23:19:15 +00:00
Jim Grosbach
b8ebc386df ARM assembly parsing two operand forms for shift instructions.
llvm-svn: 144713
2011-11-15 22:27:54 +00:00
Jim Grosbach
4d0ad5a4e0 ARM alternate size suffices for VTRN instructions.
rdar://10435076

llvm-svn: 144694
2011-11-15 20:49:46 +00:00
Jim Grosbach
8987b277cb ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.
Yet more of rdar://10435076.

llvm-svn: 144691
2011-11-15 20:29:42 +00:00
Jim Grosbach
f0690cd90c ARM assembly parsing for two-operand form of 'mul' instruction.
rdar://10449856.

llvm-svn: 144689
2011-11-15 20:14:51 +00:00
Jim Grosbach
8b1d4c989c ARM assembly parsing for two-operand form of 'mul' instruction.
Ongoing rdar://10435114.

llvm-svn: 144688
2011-11-15 20:02:06 +00:00
Jim Grosbach
e4933acaa7 Testcase for r144684.
llvm-svn: 144685
2011-11-15 19:56:17 +00:00
Owen Anderson
35f049f1fb Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
llvm-svn: 144683
2011-11-15 19:55:00 +00:00
Jim Grosbach
df951fa128 Thumb2 assembly parsing for mul.w in IT block fix.
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.

rdar://10449281

llvm-svn: 144679
2011-11-15 19:29:45 +00:00
Jim Grosbach
6846540505 ARM parsing datatype suffix variants for non-writeback VST1 instructions.
rdar://10435076

llvm-svn: 144593
2011-11-14 23:43:46 +00:00
Jim Grosbach
a1a28df278 ARM parsing datatype suffix variants for non-writeback VLD1 instructions.
rdar://10435076

llvm-svn: 144592
2011-11-14 23:32:59 +00:00
Jim Grosbach
00283a5c8e ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.
rdar://10435076

llvm-svn: 144587
2011-11-14 23:11:19 +00:00
Jim Grosbach
4a2f107b04 ARM VLDR/VSTR instructions don't need a size suffix.
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

llvm-svn: 144583
2011-11-14 23:03:21 +00:00
Jim Grosbach
13b7ab7527 ARM optional size suffix for VLDR/VSTR syntax.
llvm-svn: 144427
2011-11-11 23:34:43 +00:00
Jim Grosbach
1d581ecb00 ARM allow Q registers in vldm/vstm register lists.
rdar://9672822

llvm-svn: 144407
2011-11-11 21:27:40 +00:00
Jim Grosbach
bd7df609b7 Thumb2 parsing for push/pop w/ hi registers in the reglist.
rdar://10130228.

llvm-svn: 144331
2011-11-10 23:17:11 +00:00
Jim Grosbach
c3651cb620 Thumb MUL assembly parsing for 3-operand form.
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.

rdar://10428630

llvm-svn: 144322
2011-11-10 22:10:12 +00:00
Jim Grosbach
f5943e4c5e ARM assembly parsing for LSR/LSL/ROR(immediate).
More of rdar://9704684

llvm-svn: 144301
2011-11-10 19:18:01 +00:00
Jim Grosbach
b66dfc2999 ARM assembly parsing for ASR(immediate).
Start of rdar://9704684

llvm-svn: 144293
2011-11-10 16:44:55 +00:00
Jim Grosbach
8591bd2bab Thumb2 assembly parsing STMDB w/ optional .w suffix.
rdar://10422955

llvm-svn: 144242
2011-11-09 23:44:23 +00:00
Benjamin Kramer
89ebc7ab4b Simplify some uses of utohexstr.
As a side effect hex is printed lowercase instead of uppercase now.

llvm-svn: 144013
2011-11-07 21:00:59 +00:00
Owen Anderson
ac9fd95057 Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction.
llvm-svn: 143557
2011-11-02 18:03:14 +00:00
Kevin Enderby
b5dc88b394 Fixed a bug in the code to create a dwarf file and directory table entires when
it is separating the directory part from the basename of the FileName.  Noticed 
that this:

  .file 1 "dir/foo"

when assembled got the two parts switched.  Using the Mac OS X dwarfdump tool
it can be seen easily:

% dwarfdump -a a.out
include_directories[  1] = 'foo'
                Dir  Mod Time   File Len   File Name
                ---- ---------- ---------- ---------------------------
file_names[  1]    1 0x00000000 0x00000000 dir
...

Which should be:
...
include_directories[  1] = 'dir'
                Dir  Mod Time   File Len   File Name
                ---- ---------- ---------- ---------------------------
file_names[  1]    1 0x00000000 0x00000000 foo

llvm-svn: 143521
2011-11-01 23:39:05 +00:00
Owen Anderson
0d69f6aa51 Fix disassembly of some VST1 instructions.
llvm-svn: 143507
2011-11-01 22:18:13 +00:00
Rafael Espindola
dd7a1f625b Move test to the X86 directory, note the PR number and only run MC once.
llvm-svn: 143352
2011-10-31 17:23:09 +00:00
Owen Anderson
d7700cb13f More not-crashing NEON disassembly updates for the vld refactoring.
llvm-svn: 143351
2011-10-31 17:17:32 +00:00
Jim Grosbach
f3285dba99 Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
  mov r2, #-3
becomes
  mvn r2, #2

rdar://10349224

llvm-svn: 143235
2011-10-28 22:36:30 +00:00
Owen Anderson
9e033c5b03 Fix illegal disassembly testcase.
llvm-svn: 143231
2011-10-28 21:45:09 +00:00
Owen Anderson
3dd6c949a5 Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
llvm-svn: 143208
2011-10-28 18:02:13 +00:00
Jim Grosbach
72ab459378 Thumb2 ADD/SUB instructions encoding selection outside IT block.
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).

rdar://10348481

llvm-svn: 143201
2011-10-28 16:57:07 +00:00
NAKAMURA Takumi
2ea569c7e0 test/MC/AsmParser/2011-09-06-NoNewline.s: Add explicit -mtriple=i386. It uses X86 instruction.
FIXME: Would it be reproduced without target-specific operands?
FIXME: Why run llvm-mc as the same input by 3 times?
llvm-svn: 143195
2011-10-28 14:12:30 +00:00
Jim Grosbach
dac7815a91 ARM Allow 'q' registers in VLD/VST vector lists.
Just treat it as if the constituent D registers where specified.

rdar://10348896

llvm-svn: 143167
2011-10-28 00:06:50 +00:00
Owen Anderson
f22cd77ceb Add testcase for r143162.
llvm-svn: 143163
2011-10-27 22:54:14 +00:00
Kevin Enderby
837c1d56a2 Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and
not depend on In32BitMode.  Use the sysexitq mnemonic for the version with the
REX.W prefix and only allow it only In64BitMode.  rdar://9738584

llvm-svn: 143112
2011-10-27 17:40:41 +00:00
Jim Grosbach
4f7964293a Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.
rdar://10348844

llvm-svn: 143110
2011-10-27 17:33:59 +00:00
Jim Grosbach
e1ec953149 Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.
rdar://10348584

llvm-svn: 143108
2011-10-27 17:16:55 +00:00
Jim Grosbach
e3c6fa663f Thumb2 ldr pc-relative encoding fixes.
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.

More of rdar://10348687

llvm-svn: 143068
2011-10-26 22:22:01 +00:00
Jim Grosbach
fabe0f2f0b ARM assembly parsing and encoding for VLD1 with writeback.
Four entry register lists.

llvm-svn: 142882
2011-10-25 00:14:01 +00:00
Jim Grosbach
688186941f ARM assembly parsing and encoding for VLD1 w/ writeback.
Three entry register list variation.

llvm-svn: 142876
2011-10-24 23:26:05 +00:00
Jim Grosbach
cf4fba1dd0 ARM assembly parsing and encoding for VLD1 w/ writeback.
One and two length register list variants.

llvm-svn: 142861
2011-10-24 22:16:58 +00:00
Owen Anderson
b0e09258e7 Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
llvm-svn: 142817
2011-10-24 18:04:29 +00:00
Jim Grosbach
0bb9a86fc7 Update test for r142801.
llvm-svn: 142806
2011-10-24 17:26:26 +00:00
Craig Topper
3cb62dca0f Add X86 SARX, SHRX, and SHLX instructions.
llvm-svn: 142779
2011-10-23 22:18:24 +00:00
Craig Topper
0e63b4485c Add X86 RORX instruction
llvm-svn: 142741
2011-10-23 07:34:00 +00:00
Craig Topper
7019cf1b80 Add X86 MULX instruction for disassembler.
llvm-svn: 142738
2011-10-23 00:33:32 +00:00
Jim Grosbach
d964cf8939 Assembly parsing for 4-register sequential variant of VLD2.
llvm-svn: 142704
2011-10-21 23:58:57 +00:00
Jim Grosbach
a6e536367e Assembly parsing for 2-register sequential variant of VLD2.
llvm-svn: 142691
2011-10-21 22:21:10 +00:00
Jim Grosbach
68dfc88f95 Assembly parsing for 4-register variant of VLD1.
llvm-svn: 142682
2011-10-21 20:35:01 +00:00
Jim Grosbach
2c1ca90ac9 Assembly parsing for 3-register variant of VLD1.
llvm-svn: 142675
2011-10-21 20:02:19 +00:00
Jim Grosbach
6bb38d0e97 ARM VLD parsing and encoding.
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.

llvm-svn: 142670
2011-10-21 18:54:25 +00:00
Owen Anderson
2021ad2133 Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
llvm-svn: 142626
2011-10-20 22:23:58 +00:00
Owen Anderson
8067075218 Fix decoding tests for fixed MSR encodings.
llvm-svn: 142624
2011-10-20 22:01:48 +00:00
Owen Anderson
ffca195c01 Fix tests for corrected MSR encodings.
llvm-svn: 142622
2011-10-20 21:53:19 +00:00
Jim Grosbach
e9d1df8266 ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.
llvm-svn: 142583
2011-10-20 15:04:25 +00:00
Jim Grosbach
954465d59a Tidy up formatting.
llvm-svn: 142582
2011-10-20 14:57:47 +00:00
Jim Grosbach
972f26d936 ARM VTBX (one register) assembly parsing and encoding.
llvm-svn: 142581
2011-10-20 14:48:50 +00:00
Rafael Espindola
01d11bcdf0 Fix parsing of a line with only a # in it.
llvm-svn: 142537
2011-10-19 18:48:52 +00:00
Craig Topper
b1fa647871 Rename PEXTR to PEXT. Add intrinsics for BMI instructions.
llvm-svn: 142480
2011-10-19 07:48:35 +00:00
Jim Grosbach
6110df7008 Tidy up formatting.
llvm-svn: 142422
2011-10-18 21:09:01 +00:00
Jim Grosbach
de82cec744 Tidy up formatting.
llvm-svn: 142421
2011-10-18 21:08:16 +00:00