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Author SHA1 Message Date
Wesley Peck
7274c73974 1. Change MBlaze indirect branches to use absolute branch BRALD instead of pc relative branch BRLD. 
2. Make sure that the MBlaze stack is aligned to 4-byte boundaries.
3. Determine frame indexes that should be placed in the callers stack frame, as per the MBlaze ABI, and place them in the correct locations.

llvm-svn: 121639
 2010-12-12 20:52:31 +00:00
Benjamin Kramer
a638216447 Generalize the and-icmp-select instcombine further by allowing selects of the form 
(x & 2^n) ? 2^m+C : C

we can offset both arms by C to get the "(x & 2^n) ? 2^m : 0" form, optimize the
select to a shift and apply the offset afterwards.

llvm-svn: 121609
 2010-12-11 10:49:22 +00:00
Benjamin Kramer
5a1721f4ac Factor the (x & 2^n) ? 2^m : 0 instcombine into its own method and generalize it 
to catch cases where n != m with a shift.

llvm-svn: 121608
 2010-12-11 09:42:59 +00:00
Evan Cheng
b6773d7e1f (or (and (shl A, #shamt), mask), B) => ARMbfi B, A, ~mask where lsb(mask) == #shamt. rdar://8752056 
llvm-svn: 121606
 2010-12-11 04:11:38 +00:00
Jim Grosbach
98dcdf10c2 Add FIXME 
llvm-svn: 121598
 2010-12-10 23:41:10 +00:00
Owen Anderson
47a78db79b Attempt to get Thumb2 branch fixups working properly. 
llvm-svn: 121593
 2010-12-10 23:02:28 +00:00
Owen Anderson
8424ab65e2 Fix merge error in my last fix to Thumb2 vldr fixups. 
llvm-svn: 121588
 2010-12-10 22:53:48 +00:00
Owen Anderson
f310c92333 Fixups for Thumb2 vldr's need to have the effective PC aligned as well. 
llvm-svn: 121587
 2010-12-10 22:46:47 +00:00
Bill Wendling
7f1cea7009 The MCFixupKindInfo table needs to be in the order that the enums were 
declared. Add a note specifying this and spruce up the list a bit.

llvm-svn: 121586
 2010-12-10 22:37:19 +00:00
Owen Anderson
e85fabac75 Provide the necessary post-encoder hook for Thumb2 encodings of VMOV and friends. 
llvm-svn: 121585
 2010-12-10 22:32:08 +00:00
Bob Wilson
d30768fe3e Add float patterns for Neon vld1-lane/dup and vst1-lane operations. 
llvm-svn: 121583
 2010-12-10 22:13:32 +00:00
Bob Wilson
ae683e722f Remove unused arguments. 
llvm-svn: 121582
 2010-12-10 22:13:24 +00:00
Owen Anderson
aaf97da84b Fix encoding of Thumb1 LDRB and STRB. 
llvm-svn: 121581
 2010-12-10 22:11:13 +00:00
Jim Grosbach
d7f424dec3 Trailing whitespace. 
llvm-svn: 121580
 2010-12-10 21:57:34 +00:00
Owen Anderson
44ad90c850 Fix Thumb2 encodings of STREX and LDREX. 
llvm-svn: 121579
 2010-12-10 21:52:38 +00:00
Jim Grosbach
82dd80c956 Correct encoding of rotation immediate for Thumb2 instructions. rdar://8755999 
llvm-svn: 121525
 2010-12-10 21:24:18 +00:00
Jim Grosbach
63853d61e1 Fix encoding of 'U' bit for Thumb2 STRD/LDRD instructions. rdar://8755726 
llvm-svn: 121524
 2010-12-10 21:05:07 +00:00
Jim Grosbach
467e860805 More trivial cleanup. No need to define the EncoderMethod property type. Can 
just assign to it.

llvm-svn: 121523
 2010-12-10 20:53:44 +00:00
Jim Grosbach
5696d964ca Tidy up. 
llvm-svn: 121522
 2010-12-10 20:51:35 +00:00
Jim Grosbach
401391235f Trailing whitespace. 
llvm-svn: 121521
 2010-12-10 20:47:29 +00:00
Bob Wilson
5ff13f9d5c Fix some invalid alignments for Neon vld-dup and vld/st-lane instructions. 
Alignments smaller than the total size of the memory being loaded or stored,
unless the alignment is 8 bytes, are not allowed.  Add tests for this, too.

llvm-svn: 121506
 2010-12-10 19:37:42 +00:00
Jim Grosbach
4a414e1973 Teach isCSRestore() that ARM/Thumb2 functions will use post-modify LDR 
instructions to restore a single register rather than an LDM instruction.
rdar://8754999

llvm-svn: 121498
 2010-12-10 18:41:15 +00:00
Jim Grosbach
a378c43eae Thumb unconditional branch binary encoding. rdar://8754994 
llvm-svn: 121496
 2010-12-10 18:21:33 +00:00
Jim Grosbach
905301a7d8 Thumb conditional branch binary encodings. rdar://8745367 
llvm-svn: 121493
 2010-12-10 17:13:40 +00:00
Rafael Espindola
0e665e502d Fixed version of 121434 with no new memory leaks. 
llvm-svn: 121471
 2010-12-10 07:39:47 +00:00
Rafael Espindola
676ea9d9b4 Fix cmake build. 
llvm-svn: 121462
 2010-12-10 04:28:37 +00:00
Rafael Espindola
011e168728 Revert my previous patch to make the valgrind bots happy. 
llvm-svn: 121461
 2010-12-10 04:01:09 +00:00
NAKAMURA Takumi
e3f485b0dc lib/Target/CMakeLists.txt: Add missing lib/Target/TargetAsmInfo.cpp, following up to r121434. 
llvm-svn: 121454
 2010-12-10 02:15:24 +00:00
Kevin Enderby
a2efb1ad4e Fix the leak from r121401 of the Operands erased in the list but not deleted. 
llvm-svn: 121450
 2010-12-10 01:41:56 +00:00
Nate Begeman
8c00ecd290 Add some missing predicates. 
llvm-svn: 121445
 2010-12-10 00:54:26 +00:00
Nate Begeman
cb6d1c8193 Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. 
llvm-svn: 121439
 2010-12-10 00:26:57 +00:00
Rafael Espindola
03ad1e8f1f Initial support for the cfi directives. This is just enough to get 
f:
        .cfi_startproc
        nop
        .cfi_endproc

assembled (on ELF).

llvm-svn: 121434
 2010-12-09 23:48:29 +00:00
Bill Wendling
f8eaf8a243 Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of the 
t_addrmode_s# address modes is used for ASM printing, not for encoding.
<rdar://problem/8745375>

llvm-svn: 121417
 2010-12-09 21:49:07 +00:00
Nate Begeman
4a62a3e229 Add support for AVX to materialize +0.0 when doing scalar FP. 
llvm-svn: 121415
 2010-12-09 21:43:51 +00:00
Owen Anderson
4be3b6db5c Use the new IsAligned fixup flag to improve fixup encodings for Thumb2 branches. This is still not perfect, 
but it gets many more of them correct than it did previously.

llvm-svn: 121414
 2010-12-09 21:34:47 +00:00
Owen Anderson
a8ac35b468 Fix an issue in some Thumb fixups, where the effective PC address needs to be 4-byte aligned when calculating 
the offset.  Add a new fixup flag to represent this, and use it for the one fixups that I have a testcase for needing
this.  It's quite likely that the other Thumb fixups will need this too, and to have their fixup encoding logic
adjusted accordingly.

llvm-svn: 121408
 2010-12-09 20:27:52 +00:00
Jim Grosbach
61fe7b9ee5 Rename CB/CBZ specific fixup accordingly. 
llvm-svn: 121404
 2010-12-09 19:50:12 +00:00
Kevin Enderby
55cb19813e Add support for parsing ARM arithmetic instructions that update or don't update 
the condition codes.  Where the ones that do have an 's' suffix and the ones
that don't don't have the suffix.  The trick is if MatchInstructionImpl() fails
we try again after adding a CCOut operand with the correct value and removing
the 's' if present.  Four simple test cases added for now, lots more to come.

llvm-svn: 121401
 2010-12-09 19:19:43 +00:00
Jim Grosbach
9b3730fc77 Rename the encoder method for t_cbtarget to match. 
llvm-svn: 121399
 2010-12-09 19:04:53 +00:00
Jim Grosbach
57d420438a Thumb needs a few different encoding schemes for branch targets. Rename 
t_brtarget to be more specific.

llvm-svn: 121398
 2010-12-09 19:01:46 +00:00
Jim Grosbach
8bc33cc6e5 ARM stm/ldm instructions require more than one register in the register list. 
Otherwise, a plain str/ldr should be used instead. Make sure we account for
that in prologue/epilogue code generation.
rdar://8745460

llvm-svn: 121391
 2010-12-09 18:31:13 +00:00
Bruno Cardoso Lopes
93e5c2fb64 Add ROTR and ROTRV mips32 instructions. Patch by Akira Hatanaka 
llvm-svn: 121377
 2010-12-09 17:32:30 +00:00
Bruno Cardoso Lopes
0f5478218e Fix delay slot filler for non mips1 targets. Patch by Akira Hatanaka 
llvm-svn: 121376
 2010-12-09 17:31:11 +00:00
Kalle Raiskila
18da80f675 Dont' feed ILA two inputs - it takes just one. 
llvm-svn: 121372
 2010-12-09 16:17:31 +00:00
Jim Grosbach
4ad6abd006 tidy up. 
llvm-svn: 121371
 2010-12-09 16:15:41 +00:00
Jim Grosbach
9adf657f1a 80 columns. 
llvm-svn: 121370
 2010-12-09 16:14:46 +00:00
Eric Christopher
0e40452eb0 Rewrite the darwin tlv support to use a chain and return to copying 
the output to the correct register. Fixes a hidden problem uncovered
by the last patch where we'd try to DAG combine our MVT::Other node
oddly.

llvm-svn: 121358
 2010-12-09 06:25:53 +00:00
Wesley Peck
33ba317cf6 Reworking the stack layout generated by the MBlaze backend. 
llvm-svn: 121355
 2010-12-09 03:42:04 +00:00
Owen Anderson
96545f21b9 Fix encoding of the immediate operands on post-indexed LDR and friends. 
llvm-svn: 121354
 2010-12-09 02:56:12 +00:00
Eric Christopher
ea350b4c4b Fix up some comments. 
llvm-svn: 121351
 2010-12-09 01:57:45 +00:00
Owen Anderson
767a95816d Fix Thumb2 fixups for ldr. 
llvm-svn: 121350
 2010-12-09 01:51:07 +00:00
Jim Grosbach
5658d982b4 Add a textual message to the assert. 
llvm-svn: 121349
 2010-12-09 01:23:51 +00:00
Jim Grosbach
da9353523f Add a sanity check assert() for t2ADD/SUBrSPi instructions that they really are 
referencing the stack pointer as they say they are.

llvm-svn: 121347
 2010-12-09 01:22:19 +00:00
Jim Grosbach
fb71e10e93 When using multiple instructions to reference a frame index, make sure to 
update the opcode when necessary as well as the source register.

llvm-svn: 121346
 2010-12-09 01:22:13 +00:00
Jim Grosbach
e38a2a39c6 The add/sub SP instructions are really pseudos. The assembler should ignore 
them.

llvm-svn: 121345
 2010-12-09 01:21:27 +00:00
Matt Beaumont-Gay
a8aa446938 Remove unused variables 
llvm-svn: 121343
 2010-12-09 01:04:43 +00:00
Owen Anderson
43177d405a Fix typo in Thumb2 branch fixup. 
llvm-svn: 121342
 2010-12-09 01:02:09 +00:00
Eric Christopher
64e662fce9 Stop confusing people, it's not really a chain, or a tumor. 
llvm-svn: 121340
 2010-12-09 00:57:19 +00:00
Bill Wendling
baf852a1d6 Remove extraneous semicolon. 
llvm-svn: 121338
 2010-12-09 00:51:54 +00:00
Bill Wendling
9205cc6ea8 Attempt to make the bit-twiddling readable resulted in the binary value being 
overwritten.

llvm-svn: 121337
 2010-12-09 00:44:33 +00:00
Bill Wendling
cd8fdfd65f The BLX instruction is encoded differently than the BL, because why not? In 
particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.

Attempt to get the encoding at slightly more correct with this.

llvm-svn: 121336
 2010-12-09 00:39:08 +00:00
Eric Christopher
0100a8fda4 Remove extraneous copy from DAG conversion for darwin tls. This was 
popping up at O0 when it wasn't folded and the fast allocator would
complain.

llvm-svn: 121330
 2010-12-09 00:27:58 +00:00
Owen Anderson
b956593730 Fix Thumb2 BCC encoding and fixups. 
llvm-svn: 121329
 2010-12-09 00:27:41 +00:00
Eric Christopher
cc8a622ca4 Add rsp to the uses for the same reason as 32-bit. 
llvm-svn: 121328
 2010-12-09 00:26:41 +00:00
Kevin Enderby
988dab6b5c Allow a slash, '/', as a prefix separator for X86. rdar://8741045 
llvm-svn: 121320
 2010-12-08 23:57:59 +00:00
Jason W Kim
e270068021 Style nit and whitespace cleanup 
llvm-svn: 121317
 2010-12-08 23:35:25 +00:00
Jim Grosbach
5a00173ead Clean up the add/sub w/ SP source reg instructions in Thumb2 a bit. Add a FIXME 
for more thorough cleanup.

llvm-svn: 121315
 2010-12-08 23:30:19 +00:00
Jim Grosbach
2eda2e0be9 Fix T2TwoRegImm and use it for t2ADDrSPi12 and friends. 
llvm-svn: 121314
 2010-12-08 23:24:29 +00:00
Jason W Kim
e8047d9ec4 Removed dead comment. 
llvm-svn: 121313
 2010-12-08 23:19:44 +00:00
Jason W Kim
2e6e50c1b0 ARM/MC/ELF TPsoft is now a proper pseudo inst. 
Added test to check bl __aeabi_read_tp gets emitted properly for ELF/ASM
as well as ELF/OBJ (including fixup)

Also added support for ELF::R_ARM_TLS_IE32

llvm-svn: 121312
 2010-12-08 23:14:44 +00:00
Jim Grosbach
7a9e43e642 T2TwoRegImm isn't right for t2SUBrSPi12. Use T2I instead. 
llvm-svn: 121311
 2010-12-08 23:13:01 +00:00
Jim Grosbach
4f11f0f871 Add operand encoding for Thumb2 subw SP + imm. rdar://8745434 
llvm-svn: 121310
 2010-12-08 23:12:09 +00:00
Jim Grosbach
a423fbc4c7 Add operand encoding for Thumb2 addw Rn + imm. rdar://8745434 
llvm-svn: 121309
 2010-12-08 23:04:16 +00:00
Bill Wendling
9756f7c7b0 Support the "target" encodings for the CB[N]Z instructions. 
llvm-svn: 121308
 2010-12-08 23:01:43 +00:00
Evan Cheng
9fcb62eed1 Fix an obvious cut-n-paste error. 
llvm-svn: 121307
 2010-12-08 23:01:18 +00:00
Jim Grosbach
51082ed2a4 Add operand encoding for Thumb2 addw SP + imm. rdar://8745434 
llvm-svn: 121305
 2010-12-08 22:50:19 +00:00
Jim Grosbach
e1eb84a44a Parameterize opcode encoding bits for Thumb2 extended precision integer 
multiply instructions.

llvm-svn: 121301
 2010-12-08 22:38:41 +00:00
Jim Grosbach
13c16125f1 Fix operand encoding for Thumb2 extended precision multiplies. rdar://8745555 
llvm-svn: 121297
 2010-12-08 22:29:28 +00:00
Jim Grosbach
063c38c6df Simplify T2 operand assignment notation a bit. No need to specify a bit range 
for the source field when it's the whole thing that's being referenced.

llvm-svn: 121291
 2010-12-08 22:10:43 +00:00
Jim Grosbach
5e900612ff Tweak ARM fixup value adjustments for Thumb to better handle the half-word 
ordering of thumb mode.

llvm-svn: 121280
 2010-12-08 20:32:07 +00:00
Andrew Trick
fb72ca2129 Generalize PostRAHazardRecognizer so it can be used in any pass for 
both forward and backward scheduling. Rename it to
ScoreboardHazardRecognizer (Scoreboard is one word). Remove integer
division from the scoreboard's critical path.

llvm-svn: 121274
 2010-12-08 20:04:29 +00:00
Owen Anderson
d5c17d5981 Improve comment. 
llvm-svn: 121272
 2010-12-08 19:31:11 +00:00
Jim Grosbach
16cdaf34bc Add initializer. 
llvm-svn: 121262
 2010-12-08 15:36:45 +00:00
Evan Cheng
5582f058f4 Add comments. 
llvm-svn: 121238
 2010-12-08 06:29:02 +00:00
Bill Wendling
dac1f24d98 Add support for loading from a constant pool. 
llvm-svn: 121226
 2010-12-08 01:57:09 +00:00
Jim Grosbach
d4eea7c10d Let target asm backends see assembler flags as they go by. Use that to handle 
thumb vs. arm mode differences in WriteNopData().

llvm-svn: 121219
 2010-12-08 01:16:55 +00:00
Owen Anderson
d00dc39a11 Simplify the byte reordering logic slightly. 
llvm-svn: 121216
 2010-12-08 00:21:33 +00:00
Owen Anderson
ba5edcfe05 VLDR fixups need special handling under Thumb. While the encoding is the same, 
the order of the bytes in the data stream is flipped around.

llvm-svn: 121215
 2010-12-08 00:18:36 +00:00
Matt Beaumont-Gay
5e680ad101 Fix a warning about a variable which is only used in an assertion. 
llvm-svn: 121206
 2010-12-07 23:26:21 +00:00
Bill Wendling
45bdb13970 Cleanup in the Darwin end. No functionality change. 
llvm-svn: 121198
 2010-12-07 23:11:00 +00:00
Evan Cheng
3bd9b95b4d Fix a bad prologue / epilogue codegen bug where the compiler would emit illegal 
vpush instructions to save / restore VFP / NEON registers like this:
vpush {d8,d10,d11}
vpop {d8,d10,d11}

vpush and vpop do not allow gaps in the register list.
rdar://8728956

llvm-svn: 121197
 2010-12-07 23:08:38 +00:00
Bill Wendling
4399d09458 A bit of cleanup: early exit ApplyFixup and cache the Fixup offset. No 
functionality change.

llvm-svn: 121195
 2010-12-07 23:05:20 +00:00
Jim Grosbach
77b631549c Binary encoding for ARM tLDRspi and tSTRspi. 
llvm-svn: 121186
 2010-12-07 21:50:47 +00:00
Owen Anderson
a23e10f29d Fix Thumb2 encoding of the S bit. 
llvm-svn: 121182
 2010-12-07 20:50:15 +00:00
Jim Grosbach
1aa6a676cf Refactor the ARM CMPz* patterns to just use the normal CMP instructions when 
possible. They were duplicates for everything exception the source pattern
before.

llvm-svn: 121179
 2010-12-07 20:41:06 +00:00
Evan Cheng
9af09ebf8b Code clean up; no functionality change. 
llvm-svn: 121176
 2010-12-07 20:11:46 +00:00
Evan Cheng
0295c17fbc Code clean up; no functionality change. 
llvm-svn: 121172
 2010-12-07 19:59:34 +00:00
Bruno Cardoso Lopes
e11d870459 Remove target specific node MipsISD::CMov, which is not used because all conditional moves are directly matched using tablegen patterns. If there's a need in the future, we can introduce it again 
llvm-svn: 121164
 2010-12-07 19:04:14 +00:00
Bruno Cardoso Lopes
0e14644599 Match a pattern generated by a dag combiner opt where: 
(select (load (load tga0)) (load tga1)) => (load (select (load tga0) tga1))

Thanks to Akira for pointing that.

llvm-svn: 121163
 2010-12-07 19:00:20 +00:00
Jim Grosbach
c99517ecc6 Encode the literal field for tCMPzi instruction. 
llvm-svn: 121153
 2010-12-07 17:48:24 +00:00
Benjamin Kramer
fb17a54866 Add parens to pacify gcc. 
llvm-svn: 121142
 2010-12-07 15:50:35 +00:00
Jay Foad
79e18ed269 PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and 
zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method
trunc(), to be const and to return a new value instead of modifying the
object in place.

llvm-svn: 121120
 2010-12-07 08:25:19 +00:00
NAKAMURA Takumi
7947c9770a lib/Target/X86/X86MCAsmInfo.cpp: [PR8741] On Win64, specify explicit PrivateGlobalPrefix as ".L". 
Or, global symbols @Lxxxx might be treated as temporal symbol by MCSymbol.

llvm-svn: 121103
 2010-12-07 02:43:45 +00:00
Owen Anderson
81f8b084e6 Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it. 
llvm-svn: 121082
 2010-12-07 00:45:21 +00:00
Jim Grosbach
2d361b9318 Add fixup for Thumb1 BL/BLX instructions. 
llvm-svn: 121072
 2010-12-06 23:57:07 +00:00
Wesley Peck
ffdbf99b57 Adding bug fix that was suppose to be part of 121044. 
patch contributed by Jack Whitham!

llvm-svn: 121049
 2010-12-06 22:19:28 +00:00
Wesley Peck
996c76c27e Fixed reversed operands for IDIV and CMP instructions in MBlaze backend. 
Use BRAD instead of BRD for indirect branches in MBlaze backend.

patch contributed by Jack Whitham!

llvm-svn: 121044
 2010-12-06 22:06:49 +00:00
Wesley Peck
b168ddedaa Fix a 16-bit immediate value detection bug in the MBlaze delay slot filler. 
Address more hazards in the MBlaze delay slot filler.

patch contributed by Jack Whitham!

llvm-svn: 121037
 2010-12-06 21:11:01 +00:00
Rafael Espindola
65c25aef87 Remove the instruction fragment to data fragment lowering since it was causing 
freed data to be read. I will open a bug to track it being reenabled.

llvm-svn: 121028
 2010-12-06 19:08:48 +00:00
Owen Anderson
8e9cb84ea2 Revert r121021, which broke the buildbots. 
llvm-svn: 121026
 2010-12-06 18:57:40 +00:00
Jim Grosbach
f2e0e808ba Trailing whitespace. 
llvm-svn: 121024
 2010-12-06 18:47:44 +00:00
Owen Anderson
0c51a02230 Improve handling of Thumb2 PC-relative loads by converting LDRpci (and friends) to Pseudos. 
llvm-svn: 121021
 2010-12-06 18:35:51 +00:00
Jim Grosbach
6c27b4f3cf Encode the register operand of ARM CondCode operands correctly. ARM::CPSR if 
the instruction is predicated, reg0 otherwise.

llvm-svn: 121020
 2010-12-06 18:30:57 +00:00
Jim Grosbach
c79c6290ee The ARM AsmMatcher needs to know that the CCOut operand is a register value, 
not an immediate. It stores either ARM::CPSR or reg0.

llvm-svn: 121018
 2010-12-06 18:21:12 +00:00
Rafael Espindola
3e954d16f4 Second try at making direct object emission produce the same results 
as llc + llvm-mc. This time ELF is not changed and I tested that llvm-gcc
bootstrap on darwin10 using darwin9's assembler and linker.

llvm-svn: 121006
 2010-12-06 17:27:56 +00:00
Che-Liang Chiou
cd2878d421 ptx: add shift instructions 
llvm-svn: 120982
 2010-12-06 04:00:03 +00:00
Evan Cheng
4d9d54e44e Eliminate unneeded #include's. 
llvm-svn: 120971
 2010-12-05 23:41:43 +00:00
NAKAMURA Takumi
594d4094ca ARM/CMakeLists.txt: Add missing MLxExpansionPass.cpp since r120960. 
llvm-svn: 120966
 2010-12-05 23:08:57 +00:00
Evan Cheng
12561e250d Code clean up. 
llvm-svn: 120965
 2010-12-05 23:03:45 +00:00
Evan Cheng
854ec53564 Remove an unused variable. 
llvm-svn: 120964
 2010-12-05 23:03:35 +00:00
Evan Cheng
fc78767730 Making use of VFP / NEON floating point multiply-accumulate / subtraction is 
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
   of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
   additional pipeline stall. So it's frequently better to single codegen
   vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
   stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
   vmla + vmla is very bad. But this isn't ideal either:
     vmul
     vadd
     vmla
   Instead, we want to expand the second vmla:
     vmla
     vmul
     vadd
   Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
   faster.

Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.

A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
   compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
   fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
   vmla / vmls will trigger one of the special hazards.

Work in progress, only A+B are enabled.

llvm-svn: 120960
 2010-12-05 22:04:16 +00:00
Chris Lattner
e30adfb732 Teach X86ISelLowering that the second result of X86ISD::UMUL is a flags 
result.  This allows us to compile:

void *test12(long count) {
      return new int[count];
}

into:

test12:
	movl	$4, %ecx
	movq	%rdi, %rax
	mulq	%rcx
	movq	$-1, %rdi
	cmovnoq	%rax, %rdi
	jmp	__Znam                  ## TAILCALL

instead of:

test12:
	movl	$4, %ecx
	movq	%rdi, %rax
	mulq	%rcx
	seto	%cl
	testb	%cl, %cl
	movq	$-1, %rdi
	cmoveq	%rax, %rdi
	jmp	__Znam

Of course it would be even better if the regalloc inverted the cmov to 'cmovoq',
which would eliminate the need for the 'movq %rdi, %rax'.

llvm-svn: 120936
 2010-12-05 07:49:54 +00:00
Chris Lattner
76601e7a99 it turns out that when ".with.overflow" intrinsics were added to the X86 
backend that they were all implemented except umul.  This one fell back
to the default implementation that did a hi/lo multiply and compared the
top.  Fix this to check the overflow flag that the 'mul' instruction
sets, so we can avoid an explicit test.  Now we compile:

void *func(long count) {
      return new int[count];
}

into:

__Z4funcl:                              ## @_Z4funcl
	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
	seto	%cl                     ## encoding: [0x0f,0x90,0xc1]
	testb	%cl, %cl                ## encoding: [0x84,0xc9]
	movq	$-1, %rdi               ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
	cmoveq	%rax, %rdi              ## encoding: [0x48,0x0f,0x44,0xf8]
	jmp	__Znam                  ## TAILCALL

instead of:

__Z4funcl:                              ## @_Z4funcl
	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
	testq	%rdx, %rdx              ## encoding: [0x48,0x85,0xd2]
	movq	$-1, %rdi               ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
	cmoveq	%rax, %rdi              ## encoding: [0x48,0x0f,0x44,0xf8]
	jmp	__Znam                  ## TAILCALL

Other than the silly seto+test, this is using the o bit directly, so it's going in the right
direction.

llvm-svn: 120935
 2010-12-05 07:30:36 +00:00
Chris Lattner
16bafb2414 generalize the previous check to handle -1 on either side of the 
select, inserting a not to compensate.  Add a missing isZero check
that I lost somehow.

This improves codegen of:

void *func(long count) {
      return new int[count];
}

from:

__Z4funcl:                              ## @_Z4funcl
	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
	testq	%rdx, %rdx              ## encoding: [0x48,0x85,0xd2]
	movq	$-1, %rdi               ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
	cmoveq	%rax, %rdi              ## encoding: [0x48,0x0f,0x44,0xf8]
	jmp	__Znam                  ## TAILCALL
                                        ## encoding: [0xeb,A]

to:

__Z4funcl:                              ## @_Z4funcl
	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
	cmpq	$1, %rdx                ## encoding: [0x48,0x83,0xfa,0x01]
	sbbq	%rdi, %rdi              ## encoding: [0x48,0x19,0xff]
	notq	%rdi                    ## encoding: [0x48,0xf7,0xd7]
	orq	%rax, %rdi              ## encoding: [0x48,0x09,0xc7]
	jmp	__Znam                  ## TAILCALL
                                        ## encoding: [0xeb,A]

llvm-svn: 120932
 2010-12-05 02:00:51 +00:00
Chris Lattner
474ed0aa9b Improve an integer select optimization in two ways: 
1. generalize 
    (select (x == 0), -1, 0) -> (sign_bit (x - 1))
to:
    (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y

2. Handle the identical pattern that happens with !=:
   (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y

cmov is often high latency and can't fold immediates or
memory operands.  For example for (x == 0) ? -1 : 1, before 
we got:

< 	testb	%sil, %sil
< 	movl	$-1, %ecx
< 	movl	$1, %eax
< 	cmovel	%ecx, %eax

now we get:

> 	cmpb	$1, %sil
> 	sbbl	%eax, %eax
> 	orl	$1, %eax

llvm-svn: 120929
 2010-12-05 01:23:24 +00:00
Bill Wendling
2b53c0830d Initialize HasPOPCNT. 
llvm-svn: 120923
 2010-12-04 23:57:24 +00:00
Benjamin Kramer
851691ddb2 Add patterns for the x86 popcnt instruction. 
- Also adds a new POPCNT subtarget feature that is currently enabled if the target
  supports SSE4.2 (nehalem) or SSE4A (barcelona).

llvm-svn: 120917
 2010-12-04 20:32:23 +00:00
Benjamin Kramer
77faee6ba1 Simplify code. No functionality change. 
llvm-svn: 120907
 2010-12-04 14:22:24 +00:00
Bob Wilson
20c65a9d33 The Thumb tADDrSPi instruction is not valid when the destination is SP. 
Check for that and try narrowing it to tADDspi instead.  Radar 8724703.

llvm-svn: 120892
 2010-12-04 04:40:19 +00:00
Rafael Espindola
9215947c83 There are two reasons why we might want to use 
foo = a - b
.long foo
instead of just
.long a - b

First, on darwin9 64 bits the assembler produces the wrong result. Second,
if "a" is the end of the section all darwin assemblers (9, 10 and mc) will not
consider a - b to be a constant but will if the dummy foo is created.

Split how we handle these cases. The first one is something MC should take care
of. The second one has to be handled by the caller.

llvm-svn: 120889
 2010-12-04 03:21:47 +00:00
Jim Grosbach
4c10ffa7c3 Encode condition code for Thumb1 conditional branch instruction. 
llvm-svn: 120865
 2010-12-04 00:20:40 +00:00
Jim Grosbach
1dac8796d5 Correctly size-reduce the t2CMPzrr instruction to tCMPzr when possible. 
tCMPzhir has undefined behavior when both source registers are low registers.
rdar://8728577

llvm-svn: 120858
 2010-12-03 23:54:18 +00:00
Bill Wendling
7e27f17312 Use correct variable names to match the patterns. 
llvm-svn: 120857
 2010-12-03 23:44:24 +00:00
Jim Grosbach
3b5c857f01 Match pattern operand names to expected encoding field names. This corrects the 
operand encoding ordering of the instruction.

llvm-svn: 120852
 2010-12-03 23:21:25 +00:00
Jim Grosbach
dbefb3e7e5 Remove incorrect BL target encoding (it's similar to, but not the same as the 
ARM instruction). Add encoding of bits 13 and 11.

llvm-svn: 120849
 2010-12-03 22:33:42 +00:00
Jim Grosbach
8cef570ed9 Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order 
halfword being emitted to the stream first. rdar://8728174

llvm-svn: 120848
 2010-12-03 22:31:40 +00:00
Nate Begeman
d4310b6d7c Revert this change since it breaks a couple of the AVX tests. 
I'm unclear if the tests are actually correct or not, but reverting for now.

llvm-svn: 120847
 2010-12-03 22:29:15 +00:00
Nate Begeman
deb26223bd Scalar f32/f64 are also subregs of ymm regs 
llvm-svn: 120844
 2010-12-03 21:54:39 +00:00
Nate Begeman
3911dcfd71 Remove SSE1-4 disable when AVX is enabled. While this may be useful for development, 
it completely breaks scalar fp in xmm regs when AVX is enabled.

llvm-svn: 120843
 2010-12-03 21:54:14 +00:00
Jim Grosbach
c69ad2176a When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the 
32-bit wide version by adding the .w suffix.

llvm-svn: 120838
 2010-12-03 20:33:01 +00:00
Benjamin Kramer
e27eff8888 Remove unused variable. 
llvm-svn: 120836
 2010-12-03 19:55:37 +00:00
Jim Grosbach
c8ce9a3453 Reduce t2 ldr/str instructions to the correct t1 versions when there's an 
immediate offset.

llvm-svn: 120833
 2010-12-03 19:47:11 +00:00
Jason W Kim
27bbab7e31 fix ARM::fixup_arm_branch, cleanup, and share more code between ELF and Darwin 
llvm-svn: 120832
 2010-12-03 19:40:23 +00:00
Jim Grosbach
25da270139 No need to declare EncoderMethod property anymore; just assign to it. 
llvm-svn: 120831
 2010-12-03 19:31:00 +00:00
Jim Grosbach
d0db6c9f0e Add FIXMEs. 
llvm-svn: 120824
 2010-12-03 18:37:17 +00:00
Jim Grosbach
dca34b5da7 Size reduction for tPUSH come from t2STMDB_UPD, not t2STMIA_UPD. 
llvm-svn: 120822
 2010-12-03 18:31:03 +00:00
Bill Wendling
b7df584ef7 Don't overwrite the opcode passed into the T1Special pattern. 
llvm-svn: 120782
 2010-12-03 02:02:58 +00:00
Bill Wendling
c4858cb4c3 Add Thumb encoding for some more instructions. 
llvm-svn: 120780
 2010-12-03 01:55:47 +00:00
Rafael Espindola
3e119b0bb4 Try to resolve symbol differences early, and if successful create a plain 
data fragment. This reduces the time to assemble the test in 8711 from 60s to
54s.

llvm-svn: 120767
 2010-12-03 00:55:40 +00:00
Bill Wendling
2f6a820abe The tLDR instruction wasn't encoded properly: 
<MCInst 2251 <MCOperand Reg:70> <MCOperand Reg:66> <MCOperand Imm:0> <MCOperand Reg:0> <MCOperand Imm:14> <MCOperand Reg:0>>

Notice that the "reg" here is 0, which is an invalid register. Put a check in
the code for this to prevent crashing.

llvm-svn: 120766
 2010-12-03 00:53:22 +00:00
Jim Grosbach
0bd3b0fd6c Trailing whitespace. 
llvm-svn: 120748
 2010-12-02 23:05:38 +00:00
Devang Patel
822facd787 Use set directive for StartMinusEndExpr. 
This is a fix for llvm-gcc-i386-darwin9 buildbot failure.

llvm-svn: 120742
 2010-12-02 21:32:30 +00:00
Jim Grosbach
b6d0c8d5b1 When expanding the MOVCCi32imm, make sure to use the ARM movt/movw opcodes, 
not thumb2.

llvm-svn: 120711
 2010-12-02 16:42:25 +00:00
Jim Grosbach
78ef3199c8 Fix copy/pasto in vmin.f32 encoding. 
llvm-svn: 120709
 2010-12-02 16:30:58 +00:00
Wesley Peck
09a4bffe09 Teaching MBlaze backend how to reverse branch conditions. 
llvm-svn: 120707
 2010-12-02 16:17:11 +00:00
Jim Grosbach
0e71db6919 Add support for binary encoding of ARM 'adr' instructions referencing constant 
pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291.

llvm-svn: 120635
 2010-12-02 00:28:45 +00:00
Devang Patel
409a5ff824 Revert r120580. 
llvm-svn: 120630
 2010-12-02 00:22:29 +00:00
Evan Cheng
4118b24aca Fix and re-enable tail call optimization of expanded libcalls. 
llvm-svn: 120622
 2010-12-01 22:59:46 +00:00
Jason W Kim
7d4b30652e fixing style nit: move class static to global static 
llvm-svn: 120619
 2010-12-01 22:46:50 +00:00
Bill Wendling
d85ff071c0 Add a post encoder method to the VFP instructions to convert them to the Thumb2 
encoding if we're in that mode.

llvm-svn: 120608
 2010-12-01 21:54:50 +00:00
Jim Grosbach
b1b1ff4271 Use the correct fixup type for ARM VLDR* 
llvm-svn: 120604
 2010-12-01 21:09:40 +00:00
Jim Grosbach
b2a12afa5f Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR 
instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.

llvm-svn: 120594
 2010-12-01 19:47:31 +00:00
Owen Anderson
8802c68592 Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax. 
llvm-svn: 120589
 2010-12-01 19:18:46 +00:00
Jason W Kim
d468d24fc9 kill trailing space 
llvm-svn: 120586
 2010-12-01 19:07:22 +00:00
Jim Grosbach
25b2b536f3 10 bits, not 12. 
llvm-svn: 120584
 2010-12-01 18:51:32 +00:00
Devang Patel
e68cb5a5cf Disable debug info for x86-darwin9 and earlier until PR 8715 and radar 8709290 are fixed. 
llvm-svn: 120580
 2010-12-01 16:59:34 +00:00
Duncan Sands
cd4f56b8e2 I don't think it makes any sense to assert that the target supports SSE3 here. 
The user (i.e. whoever generated a call to the intrinsic in the first place) is
essentially asking for a particular instruction to be placed in the assembler.
If that instruction won't execute on the target machine, that's their problem
not ours.  Two buildbots with processors that don't support SSE3 were barfing
on the apm.ll test in CodeGen/X86 because of this assertion.

llvm-svn: 120574
 2010-12-01 12:58:13 +00:00
Che-Liang Chiou
c61d8fa0e3 ptx: bug fix: use after free 
llvm-svn: 120571
 2010-12-01 11:45:53 +00:00
Jim Grosbach
a3e6ffffe5 Elaborate on FIXME. 
llvm-svn: 120552
 2010-12-01 04:01:17 +00:00
Jim Grosbach
b2044fcba1 Move the ARMAsmPrinter class defintiion into a header file. 
llvm-svn: 120551
 2010-12-01 03:45:07 +00:00
Evan Cheng
84162760b7 Speculatively disable x86 portion of r120501 to appease the x86_64 buildbot. 
llvm-svn: 120549
 2010-12-01 03:27:20 +00:00
Bill Wendling
e62557dc3c Remove "comparison of integers of different signs" warning by making the 
variable unsigned.

llvm-svn: 120541
 2010-12-01 02:49:04 +00:00
Bill Wendling
4fc1c4ee84 General cleanups of comments. 
llvm-svn: 120536
 2010-12-01 02:42:55 +00:00
Jason W Kim
4d960e071c ARM/MC/ELF relocation "hello world" for movw/movt. 
Lifted adjustFixupValue() from Darwin for sharing w ELF.
Test added
TODO:
  refactor ELFObjectWriter::RecordRelocation more.
  Possibly share more code with Darwin?
  Lots more relocations...

llvm-svn: 120534
 2010-12-01 02:40:06 +00:00
Bill Wendling
b7635b1ed3 Formatting. It's all the rage! 
llvm-svn: 120533
 2010-12-01 02:36:55 +00:00
Bill Wendling
8861fb7484 More refactoring. This time the T1pI pattern. 
llvm-svn: 120532
 2010-12-01 02:28:08 +00:00
Eric Christopher
5f7eeae6ba Refactor load/store handling again. Simplify and make some room for 
reg+reg handling.

llvm-svn: 120526
 2010-12-01 01:40:24 +00:00
Jan Wen Voung
c34fbc5bb1 Initialize an ARMConstantPoolValue field. 
llvm-svn: 120525
 2010-12-01 01:38:58 +00:00
Bill Wendling
ccfea264ff s/T1pIEncode/T1pILdStEncode/g 
s/T1pIEncodeImm/T1pILdStEncodeImm/g

llvm-svn: 120524
 2010-12-01 01:38:08 +00:00
Bill Wendling
517dd72f06 Renaming variables to coincide with documentation. No functionality change. 
llvm-svn: 120522
 2010-12-01 01:32:02 +00:00
Bill Wendling
8ebed2442e Refactor T1sI and T1sIt encodings into helper classes. 
llvm-svn: 120518
 2010-12-01 01:20:15 +00:00
Bill Wendling
60d0e1a06c Refactor the T1sIt encodings into a parent class to get rid of all of the "let" 
statements.

llvm-svn: 120512
 2010-12-01 00:48:44 +00:00
Owen Anderson
2299afbb49 Use by-name rather than by-order matching for NEON operands. 
llvm-svn: 120507
 2010-12-01 00:28:25 +00:00
Evan Cheng
f7e586d749 Enable sibling call optimization of libcalls which are expanded during 
legalization time. Since at legalization time there is no mapping from
SDNode back to the corresponding LLVM instruction and the return
SDNode is target specific, this requires a target hook to check for
eligibility. Only x86 and ARM support this form of sibcall optimization
right now.
rdar://8707777

llvm-svn: 120501
 2010-11-30 23:55:39 +00:00
Bill Wendling
6a48b15c80 Rename operands to match ARM documentation. No functionality change. 
llvm-svn: 120500
 2010-11-30 23:54:45 +00:00
Jim Grosbach
c8c81941f6 Fix typo. 
llvm-svn: 120499
 2010-11-30 23:51:41 +00:00
Jim Grosbach
ce4e8350aa Trailing whitespace. 
llvm-svn: 120497
 2010-11-30 23:29:24 +00:00
Jason W Kim
725321c3c7 Thanks to JimG for catching this! 
llvm-svn: 120494
 2010-11-30 23:27:18 +00:00
Bill Wendling
745e2de9dc Inline classes that were used in only one place. 
llvm-svn: 120488
 2010-11-30 23:16:25 +00:00
Bill Wendling
e85934f8a5 * Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as 
t_addrmode_s4, but with a different scaling factor.

* Encode the Thumb1 load and store instructions. This involved a bit of
  refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
  were removed.

llvm-svn: 120482
 2010-11-30 22:57:21 +00:00
Owen Anderson
5aff471eb8 Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the 
Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allows us to fold away at least one codegen-only pattern.

llvm-svn: 120481
 2010-11-30 22:45:47 +00:00
Jim Grosbach
09095b4dd9 Fix handling of ARM negative pc-relative fixups for loads and stores. 
llvm-svn: 120480
 2010-11-30 22:40:36 +00:00
Eric Christopher
3a1c712e47 Move X86InstrFPStack.td over to PseudoI as well. 
llvm-svn: 120470
 2010-11-30 21:57:32 +00:00
Eric Christopher
b15c993a73 Migrate X86InstrControl.td to use PseudoI and fix a couple of 80-col violations 
while I'm in there.

llvm-svn: 120466
 2010-11-30 21:37:36 +00:00
Owen Anderson
20a6f2bd2e Provide Thumb2 encodings for a few miscellaneous instructions. 
llvm-svn: 120455
 2010-11-30 20:00:01 +00:00
Jim Grosbach
532d63789b Add FIXME 
llvm-svn: 120451
 2010-11-30 19:25:56 +00:00
Owen Anderson
5f7b3e919b Add encoding support for Thumb2 PLD and PLI instructions. 
llvm-svn: 120449
 2010-11-30 19:19:31 +00:00
Eric Christopher
95f0d1fe65 Noticed this on inspection, fix and update some comments. 
llvm-svn: 120447
 2010-11-30 19:14:07 +00:00
Jim Grosbach
aa96c057be Pseudo-ize ARM MOVPCRX 
llvm-svn: 120442
 2010-11-30 18:56:36 +00:00
Owen Anderson
6581027075 Provide encodings for a few more load/store variants. 
llvm-svn: 120439
 2010-11-30 18:38:28 +00:00