Anton Korobeynikov
058984f2a8
VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP.
...
llvm-svn: 100652
2010-04-07 18:20:13 +00:00
Johnny Chen
03c2e8a36c
Add NVTBLFrm to represent A8.6.406 VTBL, VTBX Vector Table Lookup Instructions.
...
These instructions use byte index in a control vector (M:Vm) to lookup byte
values in a table and generate a new vector (D:Vd). The table is specified via
a list of vectors, which can be:
{Dn}
{Dn D<n+1>}
{Dn D<n+1> D<n+2>}
{Dn D<n+1> D<n+2> D<n+3>}
llvm-svn: 99789
2010-03-29 01:14:22 +00:00
Chris Lattner
7f2800ea6c
fix integer negates to use the proper type for the zero vectors,
...
this also depends on the new "bitconvert dropping" behavior just
added to tblgen.
llvm-svn: 99757
2010-03-28 08:39:10 +00:00
Chris Lattner
36a0df5c96
fix vnot matching to explicitly specify the type of the
...
input to be v8i8 or v16i8, which buildvectors get canonicalized to.
This allows the patterns that were previously using a bare 'vnot' to
match, before they couldn't.
llvm-svn: 99754
2010-03-28 08:08:07 +00:00
Bob Wilson
6d9296abc6
Fix indentation.
...
llvm-svn: 99705
2010-03-27 04:01:23 +00:00
Bob Wilson
be89c51aa3
Add a format argument to the N3V and N3VX classes, removing the N3Vf class.
...
llvm-svn: 99704
2010-03-27 03:56:52 +00:00
Johnny Chen
794a9a3941
Add NVMulSLFrm to represent "3-register multiply with scalar" operations and set
...
it as the format for the appropriate N3V*SL*<> classes. These instructions
require special handling of the M:Vm field which encodes the restricted Dm and
the lane index within Dm.
Examples are A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar):
vmlal.s32 q3, d2, d10[0]
llvm-svn: 99690
2010-03-27 01:03:13 +00:00
Johnny Chen
0763231e02
Remove the duplicate multiclass N3VSh_QHSD and use N3VInt_QHSD which is modified
...
to now take a format argument. N3VDInt<> and N3VQInt<> are modified to take a
format argument as well.
llvm-svn: 99676
2010-03-26 23:49:07 +00:00
Johnny Chen
ca1d7dcfe4
Add NVExtFrm to represent NEON Vector Extract Instructions, that uses Inst{11-8}
...
to encode the byte location of the extracted result in the concatenation of the
operands, from the least significant end.
Modify VEXTd and VEXTq classes to use the format.
llvm-svn: 99659
2010-03-26 22:28:56 +00:00
Johnny Chen
4a97a176e7
Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not
...
follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm. The operand order of
N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).
Add a parent class N3Vf which requires passing a Format argument and which the
N3V class is modified to inherit from. N3V class represents the "normal"
3-Register NEON Instructions with N3RegFrm.
Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
Instructions and replace 8 invocations with it.
llvm-svn: 99655
2010-03-26 21:26:28 +00:00
Johnny Chen
a8b02d6451
Add N2RegVShLFrm and N2RegVShRFrm formats so that the disassembler can easily
...
dispatch to the appropriate routines to handle the different interpretations of
the shift amount encoded in the imm6 field. The Vd, Vm fields are interpreted
the same between the two, though.
See, for example, A8.6.367 VQSHL, VQSHLU (immediate) for N2RegVShLFrm format and
A8.6.368 VQSHRN, VQSHRUN for N2RegVShRFrm format.
llvm-svn: 99590
2010-03-26 01:07:59 +00:00
Johnny Chen
58278a364d
Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm to
...
expect a Format arg. N2VCvtD/N2VCvtQ are modified to use the NVCVTFrm format.
llvm-svn: 99548
2010-03-25 20:39:04 +00:00
Johnny Chen
cc491eff10
Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ,
...
instead of the current N2V. Format of NVDupLane instances are set to NEONFrm
currently.
llvm-svn: 99518
2010-03-25 17:01:27 +00:00
Johnny Chen
f53b3e5b12
Trivial formating change.
...
llvm-svn: 99428
2010-03-24 21:25:07 +00:00
Johnny Chen
3e5750fc46
Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm.
...
NVCVTFrm will later be used to describe "vcvt with fractional bits".
llvm-svn: 99415
2010-03-24 19:47:14 +00:00
Johnny Chen
31c01c1811
Reverted r99376. The disassembler will deal with the 2-reg format of these two
...
N3VX instructions using special case code.
llvm-svn: 99409
2010-03-24 18:46:34 +00:00
Johnny Chen
d31726dba1
Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler.
...
llvm-svn: 99376
2010-03-24 01:29:25 +00:00
Johnny Chen
dabf739480
Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm,
...
respectively, and add some more comment.
llvm-svn: 99373
2010-03-24 00:57:50 +00:00
Johnny Chen
8249bce25e
Add comment.
...
llvm-svn: 99327
2010-03-23 21:30:12 +00:00
Johnny Chen
415ce90919
Add New NEON Format NVdVmVCVTFrm.
...
Converted some of the NEON vcvt instructions to this format.
llvm-svn: 99326
2010-03-23 21:25:38 +00:00
Bob Wilson
195c570fd3
Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.
...
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP. The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.
llvm-svn: 99309
2010-03-23 18:54:46 +00:00
Bob Wilson
8ba51dc0bd
Rename some instructions to match the corresponding NEON opcode.
...
llvm-svn: 99266
2010-03-23 06:26:18 +00:00
Bob Wilson
58c4740582
Change VST1 instructions for loading Q register values to operate on pairs
...
of D registers. Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.
llvm-svn: 99265
2010-03-23 06:20:33 +00:00
Bob Wilson
2764399dd8
Change VLD1 instructions for loading Q register values to operate on pairs
...
of D registers. Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.
llvm-svn: 99261
2010-03-23 05:25:43 +00:00
Bob Wilson
0741acde00
Rename one more NEON instruction that I missed earlier.
...
llvm-svn: 99201
2010-03-22 20:31:39 +00:00
Bob Wilson
80b4f21ab7
Regroup some instructions. No functional change.
...
llvm-svn: 99192
2010-03-22 18:22:06 +00:00
Bob Wilson
f23a45e151
Rename some VLD1/VST1 instructions to match the implementation, i.e., the
...
corresponding NEON instructions, instead of operation they are currently
used for.
llvm-svn: 99189
2010-03-22 18:13:18 +00:00
Bob Wilson
8ff1029669
Remove some redundant instruction classes.
...
llvm-svn: 99187
2010-03-22 18:02:38 +00:00
Bob Wilson
0e5d42fb54
Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to
...
specify encoding bits in arguments instead of "let" expressions.
llvm-svn: 99185
2010-03-22 16:43:10 +00:00
Bob Wilson
73d7323c91
Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")
...
with changes to add a separate optional register update argument. Change all
the NEON instructions with address register writeback to use it.
llvm-svn: 99095
2010-03-20 22:13:40 +00:00
Bob Wilson
c0f7724ecd
Add instruction variants for VST2, VST3, and VST4 "store-lane" operations with
...
address register writeback.
llvm-svn: 99094
2010-03-20 21:57:36 +00:00
Bob Wilson
076aa52a4f
Add variants of VST2, VST3 and VST4 with address register writeback, and
...
rewrite the existing VST3 and VST4 instructions to use the same classes as
the others.
llvm-svn: 99093
2010-03-20 21:45:18 +00:00
Bob Wilson
7578eb20da
Add instructions for double-spaced VST3 and VST4 without address register
...
writeback, and refactor the existing double-spaced VST2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.
llvm-svn: 99090
2010-03-20 21:15:48 +00:00
Bob Wilson
1106af1257
Add VST1 instructions with address register writeback.
...
llvm-svn: 99083
2010-03-20 20:54:36 +00:00
Bob Wilson
88757e6720
Add instruction variants for VLD2, VLD3, and VLD4 "load-lane" operations with
...
address register writeback.
llvm-svn: 99082
2010-03-20 20:47:18 +00:00
Bob Wilson
e70bdcb2a7
Tidy some more comments and whitespace.
...
llvm-svn: 99081
2010-03-20 20:39:53 +00:00
Bob Wilson
7dacf6bb70
Add variants of VLD2, VLD3 and VLD4 with address register writeback, and
...
rewrite the existing VLD3 and VLD4 instructions to use the same classes as
the others.
llvm-svn: 99080
2010-03-20 20:10:51 +00:00
Bob Wilson
40ae450fb5
Tidy some comments and whitespace for consistency.
...
llvm-svn: 99078
2010-03-20 19:57:03 +00:00
Bob Wilson
a98f30a3a2
Rename some instructions for consistency and sanity: use "_UPD" suffix for
...
load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.
llvm-svn: 99066
2010-03-20 18:35:24 +00:00
Bob Wilson
d275bb2338
Add instructions for double-spaced VLD3 and VLD4 without address register
...
writeback, and refactor the existing double-spaced VLD2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.
llvm-svn: 99065
2010-03-20 18:14:26 +00:00
Bob Wilson
045d2c548a
Add VLD1 instructions with address register writeback.
...
llvm-svn: 99062
2010-03-20 17:59:03 +00:00
Bob Wilson
9501c478f7
Revert this change, since it was causing ARM performance regressions.
...
--- Reverse-merging r98889 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMISelLowering.h
U lib/Target/ARM/ARMInstrInfo.td
U lib/Target/ARM/ARMInstrVFP.td
U lib/Target/ARM/ARMISelLowering.cpp
U lib/Target/ARM/ARMInstrFormats.td
llvm-svn: 99010
2010-03-19 22:51:32 +00:00
Anton Korobeynikov
eeae840ed7
Get rid of target-specific fp <-> int nodes when still I'm here.
...
llvm-svn: 98889
2010-03-18 22:35:45 +00:00
Bob Wilson
504b4c8243
Refactor NEON ld/st instructions to hardcode class arguments that are constants.
...
No functional changes.
llvm-svn: 98860
2010-03-18 20:18:39 +00:00
Johnny Chen
b1d61d9be1
Revert 98745 with respect to the addition of NEONFrm subformats for disassembly.
...
There is a better way coming up.
llvm-svn: 98777
2010-03-17 23:26:50 +00:00
Johnny Chen
0212e0df47
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
...
instructions to help disassembly.
We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60.
And modified test cases to not expect '+' in +reg or #+num. For example,
; CHECK: ldr.w r9, [r7, #28 ]
llvm-svn: 98745
2010-03-17 17:52:21 +00:00
Bob Wilson
3778e7f389
Revert 98683. It is breaking something in the disassembler.
...
llvm-svn: 98692
2010-03-16 23:01:13 +00:00
Bob Wilson
79f10e6233
Remove redundant writeback flag from ARM address mode 6. Also remove the
...
optional register update argument, which is currently unused -- when we add
support for that, it can just be a separate operand.
llvm-svn: 98683
2010-03-16 21:44:40 +00:00
Bob Wilson
34aca030c5
--- Reverse-merging r98637 into '.':
...
U test/CodeGen/ARM/tls2.ll
U test/CodeGen/ARM/arm-negative-stride.ll
U test/CodeGen/ARM/2009-10-30.ll
U test/CodeGen/ARM/globals.ll
U test/CodeGen/ARM/str_pre-2.ll
U test/CodeGen/ARM/ldrd.ll
U test/CodeGen/ARM/2009-10-27-double-align.ll
U test/CodeGen/Thumb2/thumb2-strb.ll
U test/CodeGen/Thumb2/ldr-str-imm12.ll
U test/CodeGen/Thumb2/thumb2-strh.ll
U test/CodeGen/Thumb2/thumb2-ldr.ll
U test/CodeGen/Thumb2/thumb2-str_pre.ll
U test/CodeGen/Thumb2/thumb2-str.ll
U test/CodeGen/Thumb2/thumb2-ldrh.ll
U utils/TableGen/TableGen.cpp
U utils/TableGen/DisassemblerEmitter.cpp
D utils/TableGen/RISCDisassemblerEmitter.h
D utils/TableGen/RISCDisassemblerEmitter.cpp
U Makefile.rules
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/Makefile
U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
D lib/Target/ARM/Disassembler
U lib/Target/ARM/ARMInstrFormats.td
U lib/Target/ARM/ARMAddressingModes.h
U lib/Target/ARM/Thumb2ITBlockPass.cpp
llvm-svn: 98640
2010-03-16 16:59:47 +00:00
Johnny Chen
ff030064fb
Initial ARM/Thumb disassembler check-in. It consists of a tablgen backend
...
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.
We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60.
And modified test cases to not expect '+' in +reg or #+num. For example,
; CHECK: ldr.w r9, [r7, #28 ]
llvm-svn: 98637
2010-03-16 16:36:54 +00:00
Chris Lattner
5d97a9a10d
fix an ambiguous pattern, contrary to expectations, scalar_to_vector
...
doesn't have a type constraint on the scalar because we don't have
an 'sAny' type.
llvm-svn: 98527
2010-03-15 00:52:43 +00:00
Bob Wilson
41bb0dca48
Remove obsolete comments. VLDM is implemented in ARMInstrVFP.td.
...
llvm-svn: 98395
2010-03-12 22:00:08 +00:00
Chris Lattner
49ef2cd57b
fix a bunch of partially ambiguous patterns on ARM. As an
...
example, this:
(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))
is ambiguous because DPR contains both f64 and v2f32. tblgen
currently accidentally picks f64 because it's first in the
regclass.
llvm-svn: 97955
2010-03-08 18:51:21 +00:00
Johnny Chen
41ab970549
Added Vector Swap (VSWPd and VSWPq) instructions for disassembly only.
...
A8.6.405
llvm-svn: 97052
2010-02-24 20:06:07 +00:00
Johnny Chen
71bf8b1466
Fixed typo of opcodestr, should be "vst1", not "vld1".
...
llvm-svn: 97044
2010-02-24 18:00:40 +00:00
Johnny Chen
c31a44dd8b
Added for disassembly VST1 (multiple single elements) which stores elements to
...
memory from three or four registers and VST2 (multiple two-element structures)
which stores to memory from two double-spaced registers.
A8.6.391 & A8.6.393
llvm-svn: 97018
2010-02-24 02:57:20 +00:00
Johnny Chen
7e4227c8e1
Added for disassembly VLD1 (multiple single elements) which loads memory into
...
three or four registers and VLD2 (multiple two-element structures) which loads
memory into two double-spaced registers.
A8.6.307 & A8.6.310
llvm-svn: 96980
2010-02-23 20:51:23 +00:00
Johnny Chen
9077a6f901
Added versions of VCGE, VCGT, VCLE, and VCLT NEON instructions which compare to
...
(immediate #0 ) for disassembly only.
A8.6.283, A8.6.285, A8.6.287, A8.6.290
llvm-svn: 96856
2010-02-23 01:42:58 +00:00
Johnny Chen
b35408e8df
Added VCEQ (immediate #0 ) NEON instruction for disassembly only.
...
A8.6.281
llvm-svn: 96838
2010-02-23 00:33:12 +00:00
Bob Wilson
84fc0200bd
Use NEON vmin/vmax instructions for floating-point selects.
...
Radar 7461718.
llvm-svn: 96572
2010-02-18 06:05:53 +00:00
Bob Wilson
400e59ba21
Remove the NEON N2VSInt instruction class: it's only used in one place and
...
since it has no pattern, there's not much point in distinguishing an "N2VS"
class for intrinsics anyway.
llvm-svn: 96525
2010-02-17 22:42:54 +00:00
Bob Wilson
ea55421ec2
More cleanup for NEON:
...
* Use "S" abbreviation for scalar single FP registers in class and pattern
names, instead of keeping the "D" (for "double") abbreviation and tacking on
an "s" elsewhere in the name.
* Move the scalar single FP register classes and patterns to be more
consistent with other definitions in the file.
* Rename "VNEGf32d" definition to "VNEGfd" for consistency.
* Deleted the N2VDIntsPat pattern; N2VSPat is good enough.
llvm-svn: 96521
2010-02-17 22:23:11 +00:00
Bob Wilson
532656cffc
Wrap lines to 80 columns and generally try to clean up whitespace and
...
indentation. No functional changes.
llvm-svn: 96418
2010-02-17 00:31:29 +00:00
Johnny Chen
1f609fe5fd
Add VBIF/VBIT for disassembly only.
...
A8.6.279
llvm-svn: 95713
2010-02-09 23:05:23 +00:00
Bob Wilson
ac3735b7fb
Emit spaces after commas in Neon register lists. This is more consistent
...
with the rest of the assembly output, is easier to read, and matches the
expected output for gcc's Neon tests.
llvm-svn: 93703
2010-01-18 01:24:43 +00:00
Bob Wilson
72cf548263
The Neon "vtst" instruction takes a suffix that is the element size alone --
...
adding an "i" to the suffix, indicating that the elements are integers, is
accepted but not part of the standard syntax. This helps us pass a few more
of the Neon tests from gcc.
llvm-svn: 93677
2010-01-17 06:35:17 +00:00
Johnny Chen
e3171163da
For VLDM/VSTM (Advanced SIMD), set encoding bits Inst{11-8} to 0b1011.
...
llvm-svn: 90243
2009-12-01 17:37:06 +00:00
Johnny Chen
7f7f23087c
For VMOV (immediate), make some of the encoding bits (cmode and op) unspecified.
...
For VMOVv*i[16,32], op bit is don't care, and some cmode bits vary depending on
the immediate values.
Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
llvm-svn: 90173
2009-12-01 00:02:02 +00:00
Evan Cheng
8c9f6147cd
Massive refactoring of NEON instructions. Separate opcode from data size specifier suffix, move \t up stream to instruction format, and fix more 80 column violations.
...
This fixes the NEON asm printing so the "predicate" field is printed between the opcode and the data type suffix.
llvm-svn: 89706
2009-11-23 21:57:23 +00:00
Johnny Chen
e59a67f527
Partially revert r84730 by removing N2VDup from ARMInstrFormats.td and modifying
...
VDUPLND and VDUPLNQ to derive from N2V instead of N2VDup. VDUPLND and VDUPLNQ
now expect op19_18 and op17_16 as the first two args.
llvm-svn: 89699
2009-11-23 21:00:43 +00:00
Johnny Chen
9999d2524e
Revert r84572 by removing N3VImm from ARMInstrFormats.td now that we can specify
...
{?,?,?,?} as op11_8 for VEXTd and VEXTq.
llvm-svn: 89693
2009-11-23 20:09:13 +00:00
Johnny Chen
b49fe624e7
Partially revert r89377 by removing NLdStLN class definition from
...
ARMInstrFormats.td and fixing VLD[234]LN* and VST[234]LN* to derive from NLdSt
instead of NLdStLN.
llvm-svn: 89684
2009-11-23 18:16:16 +00:00
Johnny Chen
1116f46301
Make it clear that the index bit(s) of Vector Get Lane and Vector Set Lane
...
should be left unspecified now that Bob Wilson has fixed pr5470.
llvm-svn: 89676
2009-11-23 17:48:17 +00:00
Evan Cheng
a7496ef9a6
Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td.
...
llvm-svn: 89542
2009-11-21 06:21:52 +00:00
Johnny Chen
346e6b6cac
Added NLdStLN which is similar to NLdSt with the exception that op7_4 is not
...
fully specified at this level. Subclasses of NLdStLN can specify selective
bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside
ARMInstrNEON.td.
llvm-svn: 89377
2009-11-19 19:20:17 +00:00
Evan Cheng
a47f2ea71d
Use table to separate opcode from operands.
...
llvm-svn: 86965
2009-11-12 07:16:34 +00:00
Jim Grosbach
ea6c9c17f5
Use Unified Assembly Syntax for the ARM backend.
...
llvm-svn: 86494
2009-11-09 00:11:35 +00:00
Bob Wilson
e79354a831
Print VMOV (immediate) operands as hexadecimal values. Apple's assembler
...
will not accept negative values for these. LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates. Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.
llvm-svn: 86301
2009-11-06 23:33:28 +00:00
Anton Korobeynikov
9737bfedeb
Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364.
...
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
llvm-svn: 85766
2009-11-02 00:11:39 +00:00
Jim Grosbach
5b094f3b36
vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using
...
them for scalar floating point operations for now.
llvm-svn: 85697
2009-10-31 22:57:36 +00:00
Bob Wilson
41f94edfb0
Fix NEON VST2LN instruction encoding.
...
Patch by Johnny Chen.
llvm-svn: 84767
2009-10-21 17:54:01 +00:00
Bob Wilson
5f9ea75e2b
Revert 84732. It was the wrong fix.
...
llvm-svn: 84766
2009-10-21 17:52:34 +00:00
Bob Wilson
02d3df4a87
Fix some more NEON instruction encoding problems.
...
Thanks to Johnny Chen for discovering the problem.
llvm-svn: 84732
2009-10-21 02:27:20 +00:00
Bob Wilson
e85a3142bc
Leave some NEON instruction encoding bits unspecified instead of setting
...
a default value of zero. This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.
llvm-svn: 84730
2009-10-21 02:15:46 +00:00
Jim Grosbach
ea7293494f
Refs: A8-598.
...
Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.
Patch by Johnny Chen.
llvm-svn: 84572
2009-10-20 00:38:19 +00:00
Bob Wilson
c415e33929
Fix more NEON instruction encodings.
...
Patch by Johnny Chen.
llvm-svn: 84243
2009-10-16 03:58:44 +00:00
Bob Wilson
aa08dec009
Fix encoding bits for N3VLInt3_QHS multiclass with 8-bit elements.
...
Patch by Johnny Chen.
llvm-svn: 84206
2009-10-15 21:57:47 +00:00
Bob Wilson
db95c227fa
Fix instruction encoding bits for NEON VPADAL.
...
Patch by Johnny Chen.
llvm-svn: 84146
2009-10-14 21:43:17 +00:00
Jim Grosbach
d86f233722
Inst{11-8} for vshl should be 0b0101, not 0b1111.
...
Refs: A7-17 & A8-750.
Patch by Johnny Chen.
llvm-svn: 84131
2009-10-14 20:31:01 +00:00
Bob Wilson
8092fef09a
Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.
...
llvm-svn: 83600
2009-10-09 00:01:36 +00:00
Bob Wilson
979cb24a81
Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.
...
llvm-svn: 83598
2009-10-08 23:51:31 +00:00
Bob Wilson
233992bc56
Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.
...
llvm-svn: 83596
2009-10-08 23:38:24 +00:00
Bob Wilson
5b96a53ffe
Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.
...
Also fix some copy-and-paste errors in previous changes.
llvm-svn: 83590
2009-10-08 22:53:57 +00:00
Bob Wilson
7209d78713
Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.
...
llvm-svn: 83585
2009-10-08 22:27:33 +00:00
Bob Wilson
3a55fe2105
Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.
...
llvm-svn: 83568
2009-10-08 18:56:10 +00:00
Bob Wilson
276bdabb9a
Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83526
2009-10-08 05:18:18 +00:00
Bob Wilson
8aa1d328b5
Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83518
2009-10-08 00:28:28 +00:00
Bob Wilson
958e4ae815
Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83513
2009-10-08 00:21:01 +00:00
Bob Wilson
729cd181a2
Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83508
2009-10-07 23:54:04 +00:00
Bob Wilson
3cbf156518
Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83506
2009-10-07 23:39:57 +00:00
Bob Wilson
0ffa9679a5
Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83502
2009-10-07 22:57:01 +00:00
Bob Wilson
e7173601a3
Add some instruction encoding bits for NEON load/store instructions.
...
llvm-svn: 83490
2009-10-07 21:53:04 +00:00
Bob Wilson
cee91108da
Add codegen support for NEON vst4 intrinsics with 128-bit vectors.
...
llvm-svn: 83486
2009-10-07 20:49:18 +00:00
Bob Wilson
af14187764
Add codegen support for NEON vst3 intrinsics with 128-bit vectors.
...
llvm-svn: 83484
2009-10-07 20:30:08 +00:00
Bob Wilson
62a3e55cea
Add codegen support for NEON vst2 intrinsics with 128-bit vectors.
...
llvm-svn: 83482
2009-10-07 18:47:39 +00:00
Bob Wilson
9bb47b3e5d
Add codegen support for NEON vld4 intrinsics with 128-bit vectors.
...
llvm-svn: 83479
2009-10-07 18:09:32 +00:00
Bob Wilson
b38401ccef
Add codegen support for NEON vld3 intrinsics with 128-bit vectors.
...
llvm-svn: 83471
2009-10-07 17:24:55 +00:00
Bob Wilson
8cd1ea81c4
Add codegen support for NEON vld2 operations on quad registers.
...
llvm-svn: 83422
2009-10-06 22:01:59 +00:00
Bob Wilson
64ce6ef65a
Add a comment to describe letters used in multiclass name suffixes.
...
llvm-svn: 83257
2009-10-03 04:44:16 +00:00
Bob Wilson
be258e083a
Fix encoding problem for VMLS instruction.
...
Thanks to Johnny Chen for pointing this out!
llvm-svn: 83256
2009-10-03 04:41:21 +00:00
Evan Cheng
241092d89f
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
...
ld / st pairs, etc.
llvm-svn: 83197
2009-10-01 08:22:27 +00:00
David Goodwin
89f5854ddd
Finish scheduling itineraries for NEON.
...
llvm-svn: 82788
2009-09-25 18:38:29 +00:00
David Goodwin
1d72b88015
Checkpoint NEON scheduling itineraries.
...
llvm-svn: 82657
2009-09-23 21:38:08 +00:00
Anton Korobeynikov
267bd0c577
Add QPR_VFP2 regclass and add copy_to_regclass nodes, where needed to
...
constraint the register usage.
llvm-svn: 81635
2009-09-12 22:21:08 +00:00
Anton Korobeynikov
2b6ef7724e
Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's.
...
llvm-svn: 81262
2009-09-08 22:51:43 +00:00
Anton Korobeynikov
0b3a620d60
Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails and
...
makes the code faster.
llvm-svn: 81220
2009-09-08 15:22:32 +00:00
Anton Korobeynikov
7125d63acf
More missed vdup patterns
...
llvm-svn: 80838
2009-09-02 21:21:28 +00:00
Bob Wilson
6972a16bbc
Add support for generating code for vst{234}lane intrinsics.
...
llvm-svn: 80707
2009-09-01 18:51:56 +00:00
Bob Wilson
bebadd11e4
Generate code for vld{234}_lane intrinsics.
...
llvm-svn: 80656
2009-09-01 04:26:28 +00:00
Anton Korobeynikov
17529667db
Add missed pattern
...
llvm-svn: 80502
2009-08-30 19:06:39 +00:00
Anton Korobeynikov
9fd6082c10
Add missed extract_element pattern
...
llvm-svn: 80408
2009-08-28 23:41:26 +00:00
Anton Korobeynikov
3aec90b4d6
Forgot about actual change :)
...
llvm-svn: 80250
2009-08-27 16:10:17 +00:00
Anton Korobeynikov
33d151e85e
Transform float scalar_to_vector into subreg accesses.
...
No idea whether this is profitable or not.
llvm-svn: 80245
2009-08-27 14:38:44 +00:00
Bob Wilson
02f907f33e
Remove some unused SDNode definitions.
...
llvm-svn: 80015
2009-08-25 17:52:39 +00:00
Bob Wilson
d4fbf1f70a
Expose the instruction contraint string as an argument to the NLdSt class.
...
llvm-svn: 80011
2009-08-25 17:46:06 +00:00
Bob Wilson
9482015a0a
Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
...
several things other than Neon vector lane numbers. For inline assembly
operands with a "c" print code, check that they really are immediates.
llvm-svn: 79676
2009-08-21 21:58:55 +00:00
Anton Korobeynikov
20d832fa1b
Fix some typos and use type-based isel for VZIP/VUZP/VTRN
...
llvm-svn: 79625
2009-08-21 12:41:42 +00:00
Anton Korobeynikov
220512160d
Add nodes & dummy matchers for some v{zip,uzp,trn} instructions
...
llvm-svn: 79622
2009-08-21 12:40:50 +00:00
Anton Korobeynikov
f6657d5e02
Provide vext.{16,32}
...
llvm-svn: 79620
2009-08-21 12:40:21 +00:00
Bob Wilson
fae9057bf0
Add support for Neon VEXT (vector extract) shuffles.
...
This is derived from a patch by Anton Korzh. I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.
llvm-svn: 79428
2009-08-19 17:03:43 +00:00
Bob Wilson
d337cde6e5
Create a new ARM-specific DAG node, VDUP, to represent a splat from a
...
scalar_to_vector. Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.
llvm-svn: 78994
2009-08-14 05:13:08 +00:00
Bob Wilson
7a311914ab
During legalization, change Neon vdup_lane operations from shuffles to
...
target-specific VDUPLANE nodes. This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.
llvm-svn: 78993
2009-08-14 05:08:32 +00:00
Bob Wilson
8cb7da85e3
Revert r78852 for now. I want to do this differently, but I don't have time
...
to fix it tonight.
llvm-svn: 78896
2009-08-13 05:58:56 +00:00
Bob Wilson
b089d07a1f
Recognize Neon VDUP shuffles during legalization instead of selection.
...
llvm-svn: 78852
2009-08-12 22:54:19 +00:00
Bob Wilson
d8b7ca4c28
Recognize Neon VREV shuffles during legalization instead of selection.
...
llvm-svn: 78850
2009-08-12 22:31:50 +00:00
Bob Wilson
0cf2be2466
Generate Neon VTBL and VTBX instructions from the corresponding intrinsics.
...
llvm-svn: 78835
2009-08-12 20:51:55 +00:00
Bob Wilson
61f35e39cf
Fix TableGen warnings. This partly reverts my previous change to this file,
...
leaving the mayLoad and mayStore settings around only the load/store
instructions where those can't be inferred from the patterns.
llvm-svn: 78815
2009-08-12 17:04:56 +00:00
Bob Wilson
00d605d359
Add missing chain operands for VLD* and VST* instructions.
...
Set "mayLoad" and "mayStore" on the load/store instructions.
llvm-svn: 78761
2009-08-12 00:49:01 +00:00
Owen Anderson
48f2f0ae72
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
...
the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
Bob Wilson
d64e304671
Use vAny type to get rid of Neon intrinsics that differed only in whether
...
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.
If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.
llvm-svn: 78646
2009-08-11 05:39:44 +00:00
Bob Wilson
1c75a23299
Use new EVT::vAny type to combine Neon intrinsics for VPADD.
...
llvm-svn: 78632
2009-08-11 01:15:26 +00:00
David Goodwin
8ca187462c
Fix bug in NEON convert for single-precision FP. This also fixes the tblgen warnings.
...
llvm-svn: 78629
2009-08-11 01:07:38 +00:00
Owen Anderson
b4bce99769
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
...
llvm-svn: 78610
2009-08-10 22:56:29 +00:00
David Goodwin
36a5b02e4f
Use NEON for single-precision int<->FP conversions.
...
llvm-svn: 78604
2009-08-10 22:17:39 +00:00
Anton Korobeynikov
44fa9f179c
Use subclassing to print lane-like immediates (w/o hash) eliminating
...
'no_hash' modifier. Hopefully this will make Daniel happy :)
llvm-svn: 78514
2009-08-08 23:10:41 +00:00
Anton Korobeynikov
f8256ecbb5
Add insert_elt / extract_elt patterns for v4f32 stuff.
...
Did anyone tests v4f32 ever?
llvm-svn: 78470
2009-08-08 14:06:07 +00:00
Anton Korobeynikov
0471ef8dd6
Lane number should be printed w/o hash
...
llvm-svn: 78469
2009-08-08 14:05:53 +00:00
Anton Korobeynikov
ae22c37afb
Use VLDM / VSTM to spill/reload 128-bit Neon registers
...
llvm-svn: 78468
2009-08-08 13:35:48 +00:00
Bob Wilson
88fafd84ea
Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,
...
so I generalized the class for VTRN in the .td file to handle all 3 of them.
llvm-svn: 78460
2009-08-08 06:13:25 +00:00
Bob Wilson
935ee0c122
Implement Neon VTRN instructions. For now, anyway, these are selected
...
directly from the intrinsics produced by the frontend. If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.
llvm-svn: 78459
2009-08-08 05:53:00 +00:00
Anton Korobeynikov
2dfb75ca36
Unbreak the stuff
...
llvm-svn: 78425
2009-08-07 22:51:13 +00:00
Anton Korobeynikov
9b52601704
2 more vdup.32 cases
...
llvm-svn: 78419
2009-08-07 22:36:50 +00:00
Evan Cheng
0dab4cc8a0
Fix support to use NEON for single precision fp math.
...
llvm-svn: 78397
2009-08-07 19:30:41 +00:00
Bob Wilson
bd7627b23e
Implement Neon VST[234] operations.
...
llvm-svn: 78330
2009-08-06 18:47:44 +00:00
David Goodwin
3aafcc1dd2
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
...
llvm-svn: 78321
2009-08-06 16:52:47 +00:00
Bob Wilson
905678ab37
Neon does not actually have VLD{234}.64 instructions.
...
These operations will have to be synthesized from other instructions.
llvm-svn: 78263
2009-08-06 00:24:27 +00:00
David Goodwin
6e4065d7c6
When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns.
...
llvm-svn: 78244
2009-08-05 21:02:22 +00:00
Evan Cheng
a27fac5075
80 col violations.
...
llvm-svn: 78175
2009-08-05 06:41:25 +00:00
Bob Wilson
1fe51064ba
Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.
...
Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions. The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.
llvm-svn: 78136
2009-08-05 00:49:09 +00:00
Bob Wilson
3607eeebfa
Replace dregsingle operand modifier with explicit escaped curly brackets.
...
For other VLDn and VSTn operations, we need to list the multiple registers
explicitly anyway, so there's no point in special-casing this one usage.
llvm-svn: 78109
2009-08-04 21:39:33 +00:00
David Goodwin
648590849c
Add NEON single-precision FP support for fabs and fneg.
...
llvm-svn: 78101
2009-08-04 20:39:05 +00:00
David Goodwin
5efde448fa
Match common pattern for FNMAC. Add NEON SP support.
...
llvm-svn: 78085
2009-08-04 18:44:29 +00:00
David Goodwin
99adffe5f2
Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.
...
llvm-svn: 78081
2009-08-04 17:53:06 +00:00
Bob Wilson
fe37bdfdd8
Lower Neon VLD* intrinsics to custom DAG nodes, and manually allocate the
...
results to fixed registers.
llvm-svn: 78025
2009-08-04 00:36:16 +00:00
Bob Wilson
355e0b70e0
Change Neon VLDn intrinsics to return multiple values instead of really
...
wide vectors. Likewise, change VSTn intrinsics to take separate arguments
for each vector in a multi-vector struct. Adjust tests accordingly.
llvm-svn: 77468
2009-07-29 16:39:22 +00:00
Bob Wilson
ec256c8938
Add support for ARM Neon VREV instructions.
...
Patch by Anton Korzh, with some modifications from me.
llvm-svn: 77101
2009-07-26 00:39:34 +00:00
Evan Cheng
991f885915
- Add some NEON ld / st instruction static encoding.
...
- Make bits 25-27 for ldrh, etc. explicitly zero. Previously only the JIT uses the encoding information and it's assuming anything not specified to be zero. Making them explicit so the disassembler is happy.
Patch by Sean Callanan.
llvm-svn: 75065
2009-07-08 22:51:32 +00:00
Bob Wilson
8d4a8b9370
Implement NEON vst1 instruction.
...
llvm-svn: 75037
2009-07-08 20:32:02 +00:00
Bob Wilson
3809b333de
Implement NEON vld1 instructions.
...
llvm-svn: 75019
2009-07-08 18:11:30 +00:00
Bob Wilson
6db76aaf10
Add support for ARM's Advanced SIMD (NEON) instruction set.
...
This is still a work in progress but most of the NEON instruction set
is supported.
llvm-svn: 73919
2009-06-22 23:27:02 +00:00