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957 Commits

Author SHA1 Message Date
Krzysztof Parzyszek
9be33ff87e [Hexagon] Use pseudo-instructions for true/false predicate values 
llvm-svn: 232657
 2015-03-18 19:07:53 +00:00
Krzysztof Parzyszek
a91c8c87e8 Revert "[Hexagon] Use pseudo-instructions for true/false predicate values" 
This reverts r232650.

Missed a piece of code in the previous commit.

llvm-svn: 232656
 2015-03-18 18:50:06 +00:00
Krzysztof Parzyszek
7223140027 [Hexagon] Use pseudo-instructions for true/false predicate values 
llvm-svn: 232650
 2015-03-18 17:20:51 +00:00
Krzysztof Parzyszek
74e58441b5 [Hexagon] Intrinsics for circular and bit-reversed loads and stores 
llvm-svn: 232645
 2015-03-18 16:23:44 +00:00
Krzysztof Parzyszek
7c0a6d7439 [Hexagon] Handle ENDLOOP0 in InsertBranch and RemoveBranch 
llvm-svn: 232643
 2015-03-18 15:56:43 +00:00
Krzysztof Parzyszek
38780401a1 Generate bit manipulation instructions on Hexagon 
llvm-svn: 232577
 2015-03-18 00:43:46 +00:00
Krzysztof Parzyszek
c3fdfcb9f4 Remove unneeded selection functions from HexagonISelDAGToDAG 
- SelectSelect, and
- SelectTruncate

llvm-svn: 232569
 2015-03-17 23:54:48 +00:00
Krzysztof Parzyszek
c80a27f90f Selection DAG preprocessing on Hexagon 
Simplify: (or (select c x 0) z)  ->  (select c (or x z) z)
          (or (select c 0 y) z)  ->  (select c z (or y z))
llvm-svn: 232553
 2015-03-17 21:47:16 +00:00
Daniel Sanders
36d688e2fd Re-commit: [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly memory constraints. 
Summary:
But still handle them the same way since I don't know how they differ on
this target.

No functional change intended.

Reviewers: kparzysz, adasgupt

Reviewed By: kparzysz, adasgupt

Subscribers: colinl, llvm-commits

Differential Revision: http://reviews.llvm.org/D8204

Like for the PowerPC target, I've had to add 'i' to the constraint mappings in
order to pass 2007-12-17-InvokeAsm.ll. It's not clear why 'i' has historically
been treated as a memory constraint.

llvm-svn: 232480
 2015-03-17 14:37:39 +00:00
Rafael Espindola
f2d8674c1f Pass in a "const Triple &T" instead of a raw StringRef. 
llvm-svn: 232429
 2015-03-16 22:29:29 +00:00
Rafael Espindola
9b8b42c6d0 Remove unused argument. NFC. 
llvm-svn: 232428
 2015-03-16 22:06:15 +00:00
Daniel Sanders
5301c4f2c1 Revert r232374: [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly memory constraints. 
2007-12-17-InvokeAsm.ll fails on the buildbot but not on my own system. Will investigate.

llvm-svn: 232376
 2015-03-16 14:21:22 +00:00
Daniel Sanders
5e28709fa3 [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly memory constraints. 
Summary:
But still handle them the same way since I don't know how they differ on
this target.

No functional change intended.

Reviewers: kparzysz, adasgupt

Reviewed By: kparzysz, adasgupt

Subscribers: colinl, llvm-commits

Differential Revision: http://reviews.llvm.org/D8204

llvm-svn: 232374
 2015-03-16 13:54:19 +00:00
Daniel Sanders
6dc30f40bf Make each target map all inline assembly memory constraints to InlineAsm::Constraint_m. NFC. 
Summary:
This is instead of doing this in target independent code and is the last
non-functional change before targets begin to distinguish between
different memory constraints when selecting code for the ISD::INLINEASM
node.

Next, each target will individually move away from the idea that all
memory constraints behave like 'm'.

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D8173

llvm-svn: 232373
 2015-03-16 13:13:41 +00:00
Daniel Sanders
b2b69459a8 Recommit r232027 with PR22883 fixed: Add infrastructure for support of multiple memory constraints. 
The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the operand kind is Kind_Mem. This constraint
ID is a numeric equivalent to the constraint code string and is converted
with a target specific hook in TargetLowering.

This patch maps all memory constraints to InlineAsm::Constraint_m so there
is no functional change at this point. It just proves that using these
previously unused bits in the encoding of the flag word doesn't break
anything.

The next patch will make each target preserve the current mapping of
everything to Constraint_m for itself while changing the target independent
implementation of the hook to return Constraint_Unknown appropriately. Each
target will then be adapted in separate patches to use appropriate
Constraint_* values.

PR22883 was caused the matching operands copying the whole of the operand flags
for the matched operand. This included the constraint id which needed to be
replaced with the operand number. This has been fixed with a conversion
function. Following on from this, matching operands also used the operand
number as the constraint id. This has been fixed by looking up the matched
operand and taking it from there. 

llvm-svn: 232165
 2015-03-13 12:45:09 +00:00
Hal Finkel
dc4180d54f Revert "r232027 - Add infrastructure for support of multiple memory constraints" 
This (r232027) has caused PR22883; so it seems those bits might be used by
something else after all. Reverting until we can figure out what else to do.

Original commit message:

The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the operand kind is Kind_Mem. This constraint
ID is a numeric equivalent to the constraint code string and is converted
with a target specific hook in TargetLowering.

This patch maps all memory constraints to InlineAsm::Constraint_m so there
is no functional change at this point. It just proves that using these
previously unused bits in the encoding of the flag word doesn't break anything.

The next patch will make each target preserve the current mapping of
everything to Constraint_m for itself while changing the target independent
implementation of the hook to return Constraint_Unknown appropriately. Each
target will then be adapted in separate patches to use appropriate Constraint_*
values.

llvm-svn: 232093
 2015-03-12 20:09:39 +00:00
Krzysztof Parzyszek
49d1e29261 Remove unused complex patterns for addressing modes on Hexagon. 
llvm-svn: 232057
 2015-03-12 16:44:50 +00:00
Daniel Sanders
4eee6f840d Add infrastructure for support of multiple memory constraints. 
Summary:
The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the operand kind is Kind_Mem. This constraint
ID is a numeric equivalent to the constraint code string and is converted
with a target specific hook in TargetLowering.

This patch maps all memory constraints to InlineAsm::Constraint_m so there
is no functional change at this point. It just proves that using these
previously unused bits in the encoding of the flag word doesn't break anything.

The next patch will make each target preserve the current mapping of
everything to Constraint_m for itself while changing the target independent
implementation of the hook to return Constraint_Unknown appropriately. Each
target will then be adapted in separate patches to use appropriate Constraint_*
values.

Reviewers: hfinkel

Reviewed By: hfinkel

Subscribers: hfinkel, jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D8171

llvm-svn: 232027
 2015-03-12 11:00:48 +00:00
Eric Christopher
84c7b275d4 Remove some unnecessary forward declarations and put a couple more 
where they're supposed to reside.

llvm-svn: 232014
 2015-03-12 06:07:16 +00:00
Krzysztof Parzyszek
445e825bfd Fix build break introduced in r231992 
llvm-svn: 231996
 2015-03-12 00:49:13 +00:00
Krzysztof Parzyszek
62f208b598 Eliminate constant-extender profitability checks from Hexagon isel 
llvm-svn: 231992
 2015-03-12 00:19:59 +00:00
Mehdi Amini
94c8770ed5 Move the DataLayout to the generic TargetMachine, making it mandatory. 
Summary:
I don't know why every singled backend had to redeclare its own DataLayout.
There was a virtual getDataLayout() on the common base TargetMachine, the
default implementation returned nullptr. It was not clear from this that
we could assume at call site that a DataLayout will be available with
each Target.

Now getDataLayout() is no longer virtual and return a pointer to the
DataLayout member of the common base TargetMachine. I plan to turn it into
a reference in a future patch.

The only backend that didn't have a DataLayout previsouly was the CPPBackend.
It now initializes the default DataLayout. This commit is NFC for all the
other backends.

Test Plan: clang+llvm ninja check-all

Reviewers: echristo

Subscribers: jfb, jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D8243

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 231987
 2015-03-12 00:07:24 +00:00
Eric Christopher
b5d16a61c0 Remove useMachineScheduler and replace it with subtarget options 
that control, individually, all of the disparate things it was
controlling.

At the same time move a FIXME in the Hexagon port to a new
subtarget function that will enable a user of the machine
scheduler to avoid using the source scheduler for pre-RA-scheduling.
The FIXME would have this removed, but involves either testcase
changes or adding -pre-RA-sched=source to a few testcases.

llvm-svn: 231980
 2015-03-11 22:56:10 +00:00
Eric Christopher
32ae945f51 Have getCalleeSavedRegs take a non-null MachineFunction all the 
time. The target independent code was passing in one all the
time and targets weren't checking validity before using. Update
a few calls to pass in a MachineFunction where necessary.

llvm-svn: 231970
 2015-03-11 21:41:28 +00:00
Eric Christopher
430437ec76 Remove subtarget dependence from HexagonRegisterInfo. 
llvm-svn: 231887
 2015-03-10 23:45:55 +00:00
Eric Christopher
db29a2f01c Remove the use of the subtarget in MCCodeEmitter creation and 
update all ports accordingly. Required a couple of small rewrites
in handling subtarget features during creation in PPC.

llvm-svn: 231861
 2015-03-10 22:03:14 +00:00
Colin LeMahieu
e90f8c6eac [Hexagon] Adding frame index + add load/store patterns. 
llvm-svn: 231850
 2015-03-10 21:24:13 +00:00
Colin LeMahieu
be732782a1 [Hexagon] Simplifying deallocret definitions. 
llvm-svn: 231847
 2015-03-10 21:12:32 +00:00
Colin LeMahieu
6e54f9236b [Hexagon] Separating InstHexagon from OpcodeHexagon. 
llvm-svn: 231844
 2015-03-10 20:56:22 +00:00
Colin LeMahieu
0b62318f64 [Hexagon] Adding nodes for PIC support. 
llvm-svn: 231829
 2015-03-10 20:04:44 +00:00
Colin LeMahieu
4fadccc929 [Hexagon] Adding DuplexInst instruction format and duplex class defs. 
llvm-svn: 231828
 2015-03-10 19:53:14 +00:00
Colin LeMahieu
e0c4dcc7b6 [Hexagon] Adding nodes for vector insert/extract lowering. 
llvm-svn: 231825
 2015-03-10 19:40:03 +00:00
Colin LeMahieu
aa7e3b58f5 [Hexagon] Renaming HexagonJT to JT and adding CP for constantpool. 
llvm-svn: 231824
 2015-03-10 19:29:53 +00:00
Benjamin Kramer
b12c209269 Hexagon: Remove unused InstrMapping. 
llvm-svn: 231809
 2015-03-10 18:19:16 +00:00
Benjamin Kramer
f65c49c935 Hexagon: Remove pass that does nothing at all 
llvm-svn: 231791
 2015-03-10 15:06:38 +00:00
Aaron Ballman
12f86c66e5 Removing dead code to silence warning C4060: switch statement contains no 'case' or 'default' labels; NFC. 
llvm-svn: 231785
 2015-03-10 13:56:28 +00:00
Colin LeMahieu
71ac12bc35 [Hexagon] Removing unused patterns. 
llvm-svn: 231723
 2015-03-09 23:08:46 +00:00
Colin LeMahieu
91da68b7ad [Hexagon] Use single tailcall pseudoinst and fix checking for label jumping versus tail calling. 
llvm-svn: 231713
 2015-03-09 22:05:21 +00:00
Colin LeMahieu
a4d567fa07 [Hexagon] Reapply r231699. Remove assumption that second operand is an immediate when checking if A2_tfrsi is combinable. 
llvm-svn: 231710
 2015-03-09 21:48:13 +00:00
Colin LeMahieu
9d1d946c75 [Hexagon] Reverting r231699 
llvm-svn: 231703
 2015-03-09 21:19:02 +00:00
Colin LeMahieu
08e0cb05d4 [Hexagon] Updating constant set to simpler versions. 
llvm-svn: 231699
 2015-03-09 20:33:12 +00:00
Benjamin Kramer
02fbb23c87 Remove the remaining uses of abs64 and nuke it. 
std::abs works just fine and we're already using it in many places. NFC intended.

llvm-svn: 231696
 2015-03-09 20:20:16 +00:00
Colin LeMahieu
91d2d63512 [Hexagon] Removing old halfword codegen instructions and updating const32/64 splitting. 
llvm-svn: 231695
 2015-03-09 20:11:02 +00:00
Colin LeMahieu
899cabf2eb [Hexagon] Eliminating immediate condition set. 
llvm-svn: 231693
 2015-03-09 19:57:18 +00:00
Colin LeMahieu
996edd9328 [Hexagon] Removing TFR_condset_ir/TFR_condset_ri modeling. 
llvm-svn: 231689
 2015-03-09 19:31:25 +00:00
Colin LeMahieu
6ed4dadb96 [Hexagon] Changing AddrFI back to ADDRri to address test issue. 
llvm-svn: 231687
 2015-03-09 18:57:33 +00:00
Colin LeMahieu
ea9e0a1b68 [Hexagon] Adding PackHL nodes and some missing modeling instructions and patterns 
llvm-svn: 231678
 2015-03-09 18:34:05 +00:00
Benjamin Kramer
411a71a68d ArrayRefize memory operand folding. NFC. 
llvm-svn: 230846
 2015-02-28 12:04:00 +00:00
Eric Christopher
454cbc40f6 getRegForInlineAsmConstraint wants to use TargetRegisterInfo for 
a lookup, pass that in rather than use a naked call to getSubtargetImpl.
This involved passing down and around either a TargetMachine or
TargetRegisterInfo. Update all callers/definitions around the targets
and SelectionDAG.

llvm-svn: 230699
 2015-02-26 22:38:43 +00:00
Eric Christopher
2a41cb1089 Remove an argument-less call to getSubtargetImpl from TargetLoweringBase. 
This required plumbing a TargetRegisterInfo through computeRegisterProperties
and into findRepresentativeClass which uses it for register class
iteration. This required passing a subtarget into a few target specific
initializations of TargetLowering.

llvm-svn: 230583
 2015-02-26 00:00:24 +00:00
NAKAMURA Takumi
9728985228 Fix a warning on HexagonMCCodeEmitter::MCII. [-Wunused-private-field] 
llvm-svn: 230170
 2015-02-22 09:58:29 +00:00
Tim Northover
a640d920b4 CodeGen: convert CCState interface to using ArrayRefs 
Everyone except R600 was manually passing the length of a static array
at each callsite, calculated in a variety of interesting ways. Far
easier to let ArrayRef handle that.

There should be no functional change, but out of tree targets may have
to tweak their calls as with these examples.

llvm-svn: 230118
 2015-02-21 02:11:17 +00:00
Colin LeMahieu
2397babc56 [Hexagon] Moving remaining methods off of HexagonMCInst in to HexagonMCInstrInfo and eliminating HexagonMCInst class. 
llvm-svn: 229914
 2015-02-19 21:10:50 +00:00
Colin LeMahieu
a77fe00425 [Hexagon] Moving more functions off of HexagonMCInst and in to HexagonMCInstrInfo. 
llvm-svn: 229903
 2015-02-19 19:49:27 +00:00
Colin LeMahieu
d00cd8e1d1 [Hexagon] Creating HexagonMCInstrInfo namespace as landing zone for static functions detached from HexagonMCInst. 
llvm-svn: 229885
 2015-02-19 19:00:00 +00:00
Colin LeMahieu
08deae36a2 [Hexagon] Removing static variable holding MCInstrInfo. 
llvm-svn: 229872
 2015-02-19 17:38:39 +00:00
Aaron Ballman
0b45511a2e Removing LLVM_DELETED_FUNCTION, as MSVC 2012 was the last reason for requiring the macro. NFC; LLVM edition. 
llvm-svn: 229340
 2015-02-15 22:54:22 +00:00
Chandler Carruth
18e8c62883 [PM] Remove the old 'PassManager.h' header file at the top level of 
LLVM's include tree and the use of using declarations to hide the
'legacy' namespace for the old pass manager.

This undoes the primary modules-hostile change I made to keep
out-of-tree targets building. I sent an email inquiring about whether
this would be reasonable to do at this phase and people seemed fine with
it, so making it a reality. This should allow us to start bootstrapping
with modules to a certain extent along with making it easier to mix and
match headers in general.

The updates to any code for users of LLVM are very mechanical. Switch
from including "llvm/PassManager.h" to "llvm/IR/LegacyPassManager.h".
Qualify the types which now produce compile errors with "legacy::". The
most common ones are "PassManager", "PassManagerBase", and
"FunctionPassManager".

llvm-svn: 229094
 2015-02-13 10:01:29 +00:00
Benjamin Kramer
4b76aa3d46 MathExtras: Bring Count(Trailing|Leading)Ones and CountPopulation in line with countTrailingZeros 
Update all callers.

llvm-svn: 228930
 2015-02-12 15:35:40 +00:00
Colin LeMahieu
350f7188f4 [Hexagon] Adding vector load with post-increment instructions. Adding decoder function for 64bit control register class. 
llvm-svn: 228708
 2015-02-10 16:59:36 +00:00
David Blaikie
9259521220 Fix the clang -Werror build (-Wunused-variable) 
llvm-svn: 228635
 2015-02-10 00:16:36 +00:00
Colin LeMahieu
b510c4f45f [Hexagon] Adding missing load instructions and removing an unused multiclass parameter. 
llvm-svn: 228630
 2015-02-09 23:45:24 +00:00
Colin LeMahieu
8681a8bec5 [Hexagon] Factoring classes out of some load patterns and deleting some unused ones. 
llvm-svn: 228627
 2015-02-09 23:05:44 +00:00
Colin LeMahieu
6ba6e9c428 [Hexagon] Removing more V4 predicates since V4 is the required minimum. 
llvm-svn: 228614
 2015-02-09 21:56:37 +00:00
Colin LeMahieu
4b4e923d37 [Hexagon] Removing v2-4 flags. V4 is the minimum supported version. 
llvm-svn: 228605
 2015-02-09 21:07:35 +00:00
Colin LeMahieu
e3a71bb727 [Hexagon] Factoring classes out of store patterns. 
llvm-svn: 228602
 2015-02-09 20:33:46 +00:00
Colin LeMahieu
8be848654f [Hexagon] Formatting v5 TD file. Removing commented defs. 
llvm-svn: 228598
 2015-02-09 20:03:42 +00:00
Colin LeMahieu
8bf75e2b96 [Hexagon] Cleaning up definition formatting. 
llvm-svn: 228593
 2015-02-09 19:24:44 +00:00
Colin LeMahieu
4a4a7fcd0d [Hexagon] Renaming v4 compare-and-jump instructions. 
llvm-svn: 228349
 2015-02-05 22:03:32 +00:00
Colin LeMahieu
76508657b3 [Hexagon] Deleting unused patterns. 
llvm-svn: 228348
 2015-02-05 21:43:56 +00:00
Colin LeMahieu
77a7515601 [Hexagon] Simplifying and formatting several patterns. Changing a pattern multiply to be expanded. 
llvm-svn: 228347
 2015-02-05 21:13:25 +00:00
Colin LeMahieu
c801034ec8 [Hexagon] Factoring a class out of some store patterns, deleting unused definitions and reformatting some patterns. 
llvm-svn: 228345
 2015-02-05 20:38:58 +00:00
Colin LeMahieu
1b98c6df7b [Hexagon] Factoring out a class for immediate transfers and cleaning up formatting. 
llvm-svn: 228343
 2015-02-05 20:08:52 +00:00
Colin LeMahieu
3ca6d76c86 [Hexagon] Renaming Y2_barrier. Fixing issues where doubleword variants of instructions can't be newvalue producers. 
llvm-svn: 228330
 2015-02-05 18:56:28 +00:00
Colin LeMahieu
a65b414ebc [Hexagon] Renaming A2_subri, A2_andir, A2_orir. Fixing formatting. 
llvm-svn: 228326
 2015-02-05 18:38:08 +00:00
Colin LeMahieu
db2545bd9b [Hexagon] Renaming A2_addi and formatting. 
llvm-svn: 228318
 2015-02-05 17:49:13 +00:00
Colin LeMahieu
3bdebacdf5 [Hexagon] Since decoding conflicts have been resolved, isCodeGenOnly = 0 by default and remove explicitly setting it. 
llvm-svn: 228316
 2015-02-05 17:32:17 +00:00
Colin LeMahieu
59e60a7508 [Hexagon] Deleting unused instructions and adding isCodeGenOnly to some defs. 
llvm-svn: 228238
 2015-02-05 00:10:16 +00:00
Colin LeMahieu
a5cba70965 [Hexagon] Updating load extend to i64 patterns. 
llvm-svn: 228237
 2015-02-04 23:55:16 +00:00
Colin LeMahieu
b25dd0b3f6 [Hexagon] Cleaning up i1 load and extension patterns. 
llvm-svn: 228232
 2015-02-04 23:27:48 +00:00
Colin LeMahieu
a83c8f413e [Hexagon] Simplifying more load and store patterns and using new addressing patterns. 
llvm-svn: 228231
 2015-02-04 23:23:16 +00:00
Colin LeMahieu
1968c41c8d [Hexagon] Simplifying some load and store patterns. 
llvm-svn: 228227
 2015-02-04 23:10:21 +00:00
Colin LeMahieu
0d1a9ddbbe [Hexagon] Converting absolute-address load patterns to use AddrGP. 
llvm-svn: 228225
 2015-02-04 22:54:51 +00:00
Colin LeMahieu
528f1fe83c [Hexagon] Converting atomic store/load to use AddrGP addressing. 
llvm-svn: 228223
 2015-02-04 22:40:36 +00:00
Colin LeMahieu
90f37476de [Hexagon] Simplifying some store patterns. Adding AddrGP addressing forms. 
llvm-svn: 228220
 2015-02-04 22:36:28 +00:00
Colin LeMahieu
6a07b73882 [Hexagon] Adding selection for GlobalAddress and converting [z/i]ext load patterns to make use of them. 
llvm-svn: 228184
 2015-02-04 20:38:01 +00:00
Colin LeMahieu
7672352f54 [Hexagon] Replacing some load patterns with cleaner versions. 
llvm-svn: 228169
 2015-02-04 19:05:32 +00:00
Colin LeMahieu
a49ad7fb58 [Hexagon] Adding missing isCodeGenOnly = 0 
llvm-svn: 228160
 2015-02-04 18:11:32 +00:00
Colin LeMahieu
ac8c4238a0 [Hexagon] Adding encoding information for absolute-reg mode stores. Xfailing a test until constant extenders are correctly put in the same packet. 
llvm-svn: 228158
 2015-02-04 17:52:06 +00:00
Colin LeMahieu
5f7b883547 [Hexagon] Adding encoding information for absolute-set stores. 
llvm-svn: 228154
 2015-02-04 17:24:04 +00:00
Colin LeMahieu
06a21a79f1 [Hexagon] Adding encoding bits for indirect long load instructions. 
llvm-svn: 228152
 2015-02-04 16:56:46 +00:00
Colin LeMahieu
1666e591a9 [Hexagon] Revert change to isCodeGenOnly = 1 in r228080 
llvm-svn: 228082
 2015-02-04 00:09:23 +00:00
Colin LeMahieu
02270757b3 [Hexagon] Changing some isCodeGenOnly to isAsmParserOnly since we want them to asm parse but not cause decode conflicts. 
llvm-svn: 228080
 2015-02-04 00:07:26 +00:00
Colin LeMahieu
737967641b [Hexagon] Marking a bunch of non-encoded instructions with isCodeGenOnly = 1. 
llvm-svn: 228050
 2015-02-03 22:09:51 +00:00
Colin LeMahieu
3534179cf0 [Hexagon] Converting XTYPE/SHIFT intrinsics. Cleaning out old intrinsic patterns and updating tests. 
llvm-svn: 228026
 2015-02-03 20:40:52 +00:00
Colin LeMahieu
22fa1ee703 [Hexagon] Updating XTYPE/PRED intrinsics. 
llvm-svn: 228019
 2015-02-03 19:43:59 +00:00
Colin LeMahieu
dc6eea20d4 [Hexagon] Updating XTYPE/PERM intrinsics. 
llvm-svn: 228015
 2015-02-03 19:36:59 +00:00
Colin LeMahieu
59d3eac138 [Hexagon] Adding missing vector multiply instruction encodings. Converting multiply intrinsics and updating tests. 
llvm-svn: 228010
 2015-02-03 19:15:11 +00:00
Colin LeMahieu
530baa45f7 [Hexagon] Converting complex number intrinsics and adding tests. 
llvm-svn: 227995
 2015-02-03 18:16:28 +00:00
Colin LeMahieu
ed25cb4221 [Hexagon] Adding vector intrinsics for alu32/alu and xtype/alu. 
llvm-svn: 227993
 2015-02-03 18:01:45 +00:00
Eric Christopher
cc62f1ae1b Only access TLOF via the TargetMachine, not TargetLowering. 
llvm-svn: 227949
 2015-02-03 07:22:52 +00:00
Eric Christopher
a26193de86 Define a runOnMachineFunction for the Hexagon AsmPrinter and 
use it to initialize the subtarget.

llvm-svn: 227948
 2015-02-03 06:40:22 +00:00
Eric Christopher
feb4ffa8ee Use the cached subtarget on the MachineFunction. 
llvm-svn: 227885
 2015-02-02 22:40:56 +00:00
Eric Christopher
0224cb6674 Remove dead header. 
llvm-svn: 227884
 2015-02-02 22:40:54 +00:00
Eric Christopher
a3a294848d Remove dead code in the HexagonMCInst classes. This also fixes 
a layering violation in the port and removes calls to getSubtargetImpl.

llvm-svn: 227883
 2015-02-02 22:40:53 +00:00
Eric Christopher
bfcc1f0544 80-col fixup. 
llvm-svn: 227882
 2015-02-02 22:40:51 +00:00
Eric Christopher
da02fbafc4 Remove dead code in the HexagonMCInst classes. This also fixes 
a layering violation in the port and removes calls to getSubtargetImpl.

llvm-svn: 227880
 2015-02-02 22:28:48 +00:00
Eric Christopher
922293f3ca 80-col fixup. 
llvm-svn: 227879
 2015-02-02 22:28:46 +00:00
Eric Christopher
cddc0aa5d2 Remove unused class variables and update all callers/uses from 
the HexagonSplitTFRCondSet pass. Use the subtarget off the machine
function at the same time.

llvm-svn: 227878
 2015-02-02 22:28:44 +00:00
Eric Christopher
3e95522a4f Migrate the HexagonSplitConst32AndConst64 pass from TargetMachine 
based getSubtarget to the one cached on the MachineFunction.
Remove unused class variables and update all callers/uses.

llvm-svn: 227874
 2015-02-02 22:11:43 +00:00
Eric Christopher
9e0beab8b0 Remove #if'd code and update comment. 
llvm-svn: 227873
 2015-02-02 22:11:42 +00:00
Eric Christopher
3ccabc821b Move HexagonMachineScheduler to use the subtarget off of the 
MachineFunction and update all uses accordingly including
VLIWResourceModel.

llvm-svn: 227872
 2015-02-02 22:11:40 +00:00
Eric Christopher
3ce7338e3c Cache and use the subtarget that owns the target lowering. 
llvm-svn: 227871
 2015-02-02 22:11:36 +00:00
Eric Christopher
5cb620ce06 Migrate HexagonISelDAGToDAG to setting a subtarget pointer during 
runOnMachineFunction. Update all uses of the Subtarget accordingly.

llvm-svn: 227840
 2015-02-02 19:22:03 +00:00
Eric Christopher
eabd2452d1 Use the getSubtarget call off of the MachineFunction rather than 
the TargetMachine.

llvm-svn: 227839
 2015-02-02 19:22:01 +00:00
Eric Christopher
fa6d0be9d4 Remove unused class variables and update calls to get the subtarget 
off of the machine function.

llvm-svn: 227837
 2015-02-02 19:05:28 +00:00
Eric Christopher
1a48904da5 Sink queries into asserts since the variable is unused otherwise. 
llvm-svn: 227836
 2015-02-02 18:58:24 +00:00
Eric Christopher
5120f67861 Update CMake build for removed files. 
llvm-svn: 227834
 2015-02-02 18:52:49 +00:00
Eric Christopher
815e721ecd Get TargetRegisterInfo and TargetInstrInfo off of the MachineFunction 
and remove unnecessary class variables.

llvm-svn: 227832
 2015-02-02 18:46:31 +00:00
Eric Christopher
5e75c7a7c4 Use the function template getSubtarget to remove an explicit cast. 
llvm-svn: 227831
 2015-02-02 18:46:29 +00:00
Eric Christopher
201e4d3e21 Grab TargetInstrInfo off of the MachineFunction and remove 
unnecessary class variables.

llvm-svn: 227830
 2015-02-02 18:46:27 +00:00
Eric Christopher
ef475ed72a Remove unused files. 
llvm-svn: 227829
 2015-02-02 18:46:23 +00:00
Colin LeMahieu
e39bce1b3f [Hexagon] Adding vector shift instructions and tests. 
llvm-svn: 227619
 2015-01-30 21:58:46 +00:00
Colin LeMahieu
4316877029 [Hexagon] Adding vector predicate instructions. 
llvm-svn: 227613
 2015-01-30 21:24:06 +00:00
Colin LeMahieu
ee3ca03932 [Hexagon] Adding vector permutation instructions and tests. 
llvm-svn: 227612
 2015-01-30 21:14:00 +00:00
Colin LeMahieu
f8c65e69e9 [Hexagon] Adding vector multiplies. Cleaning up tests. 
llvm-svn: 227609
 2015-01-30 20:56:54 +00:00
Colin LeMahieu
113a9cf539 [Hexagon] Adding XTYPE/COMPLEX instructions and cleaning up tests. 
llvm-svn: 227607
 2015-01-30 20:08:37 +00:00
Colin LeMahieu
de5c154423 [Hexagon] Adding XTYPE/ALU vector instructions. Organizing test files. 
llvm-svn: 227598
 2015-01-30 19:13:26 +00:00
Colin LeMahieu
9b74e87575 [Hexagon] Adding a number of vector load variants and organizing tests. 
llvm-svn: 227588
 2015-01-30 18:09:44 +00:00
Colin LeMahieu
54b41eed7b [Hexagon] Organizing tests and adding a few missing jump instruction encodings. 
llvm-svn: 227498
 2015-01-29 21:47:15 +00:00
Colin LeMahieu
13519e2bd4 [Hexagon] Adding missing instruction encodings and tests. 
llvm-svn: 227495
 2015-01-29 21:30:22 +00:00
Colin LeMahieu
d1253ac69a [Hexagon] Adding alu vector instructions 
llvm-svn: 227493
 2015-01-29 21:09:30 +00:00
Rafael Espindola
16f3006ec0 Compute the ELF SectionKind from the flags. 
Any code creating an MCSectionELF knows ELF and already provides the flags.

SectionKind is an abstraction used by common code that uses a plain
MCSection.

Use the flags to compute the SectionKind. This removes a lot of
guessing and boilerplate from the MCSectionELF construction.

llvm-svn: 227476
 2015-01-29 17:33:21 +00:00
Colin LeMahieu
60586de39c [Hexagon] Deleting old variants of intrinsics and adding missing tests. 
llvm-svn: 227474
 2015-01-29 17:26:56 +00:00
Colin LeMahieu
f319d92955 [Hexagon] Adding CR intrinsic tests. 
llvm-svn: 227463
 2015-01-29 16:55:37 +00:00
Colin LeMahieu
28811bcf4c [Hexagon] Deleting unused classes. 
llvm-svn: 227460
 2015-01-29 16:35:38 +00:00
Colin LeMahieu
332a5243a2 [Hexagon] Adding XTYPE/PRED intrinsic tests. Converting predicate types to i32 instead of i1. 
llvm-svn: 227457
 2015-01-29 16:08:43 +00:00
Colin LeMahieu
f323a70677 [Hexagon] Updating several V5 intrinsics and adding FP tests. 
llvm-svn: 227379
 2015-01-28 22:08:16 +00:00
Colin LeMahieu
e461a384f0 [Hexagon] Updating many V4 intrinsic patterns. Adding missing instruction and deleting unused classes. 
llvm-svn: 227353
 2015-01-28 19:39:09 +00:00
Colin LeMahieu
629196ef3e [Hexagon] Adding XTYPE/MPY intrinsic tests and some missing multiply instructions. 
llvm-svn: 227347
 2015-01-28 19:16:17 +00:00
Colin LeMahieu
159f2e1618 [Hexagon] Deleting a lot of old variants of intrinsics and updating references. 
llvm-svn: 227338
 2015-01-28 18:29:11 +00:00
Colin LeMahieu
123b7d1e5a [Hexagon] Converting XTYPE/BIT intrinsic patterns and adding tests. 
llvm-svn: 227335
 2015-01-28 18:06:23 +00:00
Colin LeMahieu
13e9276fa8 [Hexagon] Replacing XTYPE/SHIFT intrinsic patternss. Adding tests and missing instructions with tests. 
llvm-svn: 227330
 2015-01-28 17:37:59 +00:00
Colin LeMahieu
d39a45731a [Hexagon] Replacing intrinsics for halfword adds and max/min word/dword. 
llvm-svn: 227322
 2015-01-28 17:06:40 +00:00
Chandler Carruth
2835bf79f7 [LPM] Stop using the string based preservation API. It is an 
abomination.

For starters, this API is incredibly slow. In order to lookup the name
of a pass it must take a memory fence to acquire a pointer to the
managed static pass registry, and then potentially acquire locks while
it consults this registry for information about what passes exist by
that name. This stops the world of LLVMs in your process no matter
how little they cared about the result.

To make this more joyful, you'll note that we are preserving many passes
which *do not exist* any more, or are not even analyses which one might
wish to have be preserved. This means we do all the work only to say
"nope" with no error to the user.

String-based APIs are a *bad idea*. String-based APIs that cannot
produce any meaningful error are an even worse idea. =/

I have a patch that simply removes this API completely, but I'm hesitant
to commit it as I don't really want to perniciously break out-of-tree
users of the old pass manager. I'd rather they just have to migrate to
the new one at some point. If others disagree and would like me to kill
it with fire, just say the word. =]

llvm-svn: 227294
 2015-01-28 04:57:56 +00:00
Eric Christopher
aacfef65cf Move DataLayout back to the TargetMachine from TargetSubtargetInfo 
derived classes.

Since global data alignment, layout, and mangling is often based on the
DataLayout, move it to the TargetMachine. This ensures that global
data is going to be layed out and mangled consistently if the subtarget
changes on a per function basis. Prior to this all targets(*) have
had subtarget dependent code moved out and onto the TargetMachine.

*One target hasn't been migrated as part of this change: R600. The
R600 port has, as a subtarget feature, the size of pointers and
this affects global data layout. I've currently hacked in a FIXME
to enable progress, but the port needs to be updated to either pass
the 64-bitness to the TargetMachine, or fix the DataLayout to
avoid subtarget dependent features.

llvm-svn: 227113
 2015-01-26 19:03:15 +00:00
Colin LeMahieu
eacab3ed87 [Hexagon] Converting multiply and accumulate with immediate intrinsics to patterns. 
llvm-svn: 226681
 2015-01-21 18:13:15 +00:00
Colin LeMahieu
b11b24f79e [Hexagon] Adding intrinsics for doubleword ALU operations. 
llvm-svn: 226606
 2015-01-20 20:45:05 +00:00
Colin LeMahieu
9cc2ac99d5 [Hexagon] Updating muxir/ri/ii intrinsics. Setting predicate registers as compatible with i32 rather than doing custom type conversion. 
llvm-svn: 226500
 2015-01-19 20:31:18 +00:00
Colin LeMahieu
89f087ffd8 [Hexagon] Converting intrinsics combine imm/imm, simple shifts and extends. 
llvm-svn: 226483
 2015-01-19 18:56:19 +00:00
Colin LeMahieu
c9d3d690e7 [Hexagon] Converting remaining ALU32/ALU intrinsics. 
llvm-svn: 226480
 2015-01-19 18:33:58 +00:00
Colin LeMahieu
dc770a4bae [Hexagon] Converting ALU32/ALU intrinsics to new patterns. 
llvm-svn: 226478
 2015-01-19 18:22:19 +00:00
Colin LeMahieu
9b7e71b043 [Hexagon] Converting halfword to double accumulating multiply intrinsics. 
llvm-svn: 226472
 2015-01-19 17:36:32 +00:00
David Blaikie
8839ae1559 std::unique_ptrify the MCStreamer argument to createAsmPrinter 
llvm-svn: 226414
 2015-01-18 20:29:04 +00:00
Colin LeMahieu
b0ae008450 [Hexagon] Converting halfword to doubleword multiply intrinsics. 
llvm-svn: 226326
 2015-01-16 21:41:57 +00:00
Colin LeMahieu
3f0206ff73 [Hexagon] Converting accumulating halfword multiply intrinsics to patterns. 
llvm-svn: 226324
 2015-01-16 21:36:34 +00:00
Colin LeMahieu
6559af4ce0 [Hexagon] Beginning converting intrinsics to patterns instead of duplicated definitions. Converting halfword multiply intrinsics. 
llvm-svn: 226318
 2015-01-16 20:38:54 +00:00
Colin LeMahieu
c4ad57bf83 [Hexagon] Fix 226309, replacement atomic store patterns didn't actually exist, added new versions. 
llvm-svn: 226315
 2015-01-16 20:16:14 +00:00
Colin LeMahieu
1a5115554a [Hexagon] Removing old duplicate atomic load/store patterns. 
llvm-svn: 226309
 2015-01-16 19:53:35 +00:00
Colin LeMahieu
33e84773e4 [Hexagon] Converting old patterns to new versions using classes. 
llvm-svn: 226304
 2015-01-16 19:29:59 +00:00
Colin LeMahieu
8abdb53b9d [Hexagon] Updating call/jump instruction patterns. 
llvm-svn: 226288
 2015-01-16 17:05:27 +00:00
Colin LeMahieu
ef6291ec41 [Hexagon] Adding new-value store and bit reverse instructions. 
llvm-svn: 226224
 2015-01-15 23:10:29 +00:00
Colin LeMahieu
d02bf117bc [Hexagon] Fix 226206 by uncommenting required pattern and changing patterns for simple load-extends. 
llvm-svn: 226210
 2015-01-15 21:35:49 +00:00
Colin LeMahieu
ad558c9627 [Hexagon] Updating indexed load-extend patterns and changing test to new expected output. 
llvm-svn: 226206
 2015-01-15 21:07:52 +00:00
Colin LeMahieu
14474ecfe7 [Hexagon] Removing old versions of vsplice, valign, cl0, ct0 and updating references to new versions. 
llvm-svn: 226194
 2015-01-15 19:28:32 +00:00
Colin LeMahieu
39bcb9a1e4 [Hexagon] Adding vmux instruction. Removing old transfer instructions and updating references. 
llvm-svn: 226184
 2015-01-15 18:16:00 +00:00
Colin LeMahieu
55264a56e6 [Hexagon] Deleting old float comparison instruction and updating references to new ones. 
llvm-svn: 226179
 2015-01-15 17:28:14 +00:00
Colin LeMahieu
6ce6625967 [Hexagon] Replacing old fadd/fsub instructions and updating references. 
llvm-svn: 226176
 2015-01-15 16:30:07 +00:00
Colin LeMahieu
0710e9b065 [Hexagon] Replacing old versions of stores and loads. 
llvm-svn: 226065
 2015-01-15 00:15:30 +00:00
Colin LeMahieu
255d98103d [Hexagon] Replacing old version of convert and load f64. 
llvm-svn: 226057
 2015-01-14 23:07:36 +00:00
Colin LeMahieu
fc143604e5 [Hexagon] Removing old, unused !tstbit instructions. 
llvm-svn: 226036
 2015-01-14 20:26:15 +00:00
Colin LeMahieu
b97153f51b [Hexagon] Removing old versions of cmph and updating references. 
llvm-svn: 226013
 2015-01-14 18:26:14 +00:00
Colin LeMahieu
5aaa1beaef [Hexagon] Removing old versions of cmpb and updating references. 
llvm-svn: 226006
 2015-01-14 18:05:44 +00:00
Colin LeMahieu
26ee1d374d [Hexagon] Deleting versions of compare-not that don't have encoding information. Updating references. 
llvm-svn: 226003
 2015-01-14 16:49:12 +00:00
Chandler Carruth
0b619fcc8e [cleanup] Re-sort all the #include lines in LLVM using 
utils/sort_includes.py.

I clearly haven't done this in a while, so more changed than usual. This
even uncovered a missing include from the InstrProf library that I've
added. No functionality changed here, just mechanical cleanup of the
include order.

llvm-svn: 225974
 2015-01-14 11:23:27 +00:00
Ahmed Bougacha
4150499cd1 [SelectionDAG] Allow targets to specify legality of extloads' result 
type (in addition to the memory type).

The *LoadExt* legalization handling used to only have one type, the
memory type.  This forced users to assume that as long as the extload
for the memory type was declared legal, and the result type was legal,
the whole extload was legal.

However, this isn't always the case.  For instance, on X86, with AVX,
this is legal:
    v4i32 load, zext from v4i8
but this isn't:
    v4i64 load, zext from v4i8
Whereas v4i64 is (arguably) legal, even without AVX2.

Note that the same thing was done a while ago for truncstores (r46140),
but I assume no one needed it yet for extloads, so here we go.

Calls to getLoadExtAction were changed to add the value type, found
manually in the surrounding code.

Calls to setLoadExtAction were mechanically changed, by wrapping the
call in a loop, to match previous behavior.  The loop iterates over
the MVT subrange corresponding to the memory type (FP vectors, etc...).
I also pulled neighboring setTruncStoreActions into some of the loops;
those shouldn't make a difference, as the additional types are illegal.
(e.g., i128->i1 truncstores on PPC.)

No functional change intended.

Differential Revision: http://reviews.llvm.org/D6532

llvm-svn: 225421
 2015-01-08 00:51:32 +00:00
Colin LeMahieu
3a3e6ac2f6 [Hexagon] Fix 225372 USR register is not fully complete. Removing Uses = [USR] maintains existing functionality to old instructions without encodings. 
llvm-svn: 225377
 2015-01-07 20:43:38 +00:00
Colin LeMahieu
113d011e38 [Hexagon] Adding floating point classification and creation. 
llvm-svn: 225374
 2015-01-07 20:28:57 +00:00
Colin LeMahieu
4e075604d7 [Hexagon] Adding encodings for v5 floating point instructions. 
llvm-svn: 225372
 2015-01-07 20:24:09 +00:00
Colin LeMahieu
bb38f7d496 [Hexagon] Adding encoding for popcount, fastcorner, dword asr with rounding. 
llvm-svn: 225371
 2015-01-07 20:07:28 +00:00
Colin LeMahieu
5dbfa1b1a1 [Hexagon] Adding compound jump encodings. 
llvm-svn: 225291
 2015-01-06 20:03:31 +00:00
Colin LeMahieu
e59b0ff43e [Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, dcfetch. 
llvm-svn: 225283
 2015-01-06 19:03:20 +00:00
Colin LeMahieu
769b0f293d [Hexagon] Adding encoding information for absolute address loads. 
llvm-svn: 225279
 2015-01-06 18:38:26 +00:00
Colin LeMahieu
6a3f537bb7 [Hexagon] Fix 225267. GP register is not yet fully implemented. Removing Uses [GP] maintains existing behavior. 
llvm-svn: 225270
 2015-01-06 16:52:38 +00:00
Colin LeMahieu
7c1bcabc22 [Hexagon] Adding dealloc_return encoding and absolute address stores. 
llvm-svn: 225267
 2015-01-06 16:15:15 +00:00
Colin LeMahieu
9f18605465 [Hexagon] Adding add/sub with carry, logical shift left by immediate and memop instructions. Removing old defs without bits and updating references. 
llvm-svn: 225210
 2015-01-05 21:36:38 +00:00
Colin LeMahieu
139c47f671 [Hexagon] Adding rounding reg/reg variants, accumulating multiplies, and accumulating shifts. 
llvm-svn: 225201
 2015-01-05 20:56:41 +00:00
Colin LeMahieu
9a85ae53a7 [Hexagon] Adding V4 bit manipulating instructions, removing ALU defs without encoding bits. 
llvm-svn: 225199
 2015-01-05 20:35:54 +00:00
Colin LeMahieu
ef8cb75b7d [Hexagon] Adding V4 logic-logic instructions and tests. 
llvm-svn: 225198
 2015-01-05 20:14:58 +00:00
Colin LeMahieu
e42756883b [Hexagon] Adding orand, bitsplit reg/reg, and modwrap instructions. 
llvm-svn: 225197
 2015-01-05 20:04:40 +00:00
Colin LeMahieu
caea68537b [Hexagon] Adding round reg/imm and bitsplit instructions. 
llvm-svn: 225188
 2015-01-05 18:08:21 +00:00
Craig Topper
03e518b16d Replace several 'assert(false' with 'llvm_unreachable' or fold a condition into the assert. 
llvm-svn: 225160
 2015-01-05 10:15:49 +00:00
Colin LeMahieu
f2dcb1dbfa Reverting 225045 and 225043 and XFAIL multiline.ll on hexagon 
llvm-svn: 225047
 2014-12-31 17:14:35 +00:00
Colin LeMahieu
ca60c4bd6c [Hexagon] Removing assertion to appease buildbot until I can reproduce the problem 
llvm-svn: 225045
 2014-12-31 16:20:00 +00:00
Colin LeMahieu
fe239ffbc6 [Hexagon] Changing an llvm_unreachable to an assertion and returning 0. Relocations aren't implemented yet but we don't need to abort for this in release builds. 
llvm-svn: 225043
 2014-12-31 15:57:38 +00:00
Colin LeMahieu
664727ddb9 [Hexagon] Adding accumulating add/sub, doubleword logic-not variants, doubleword bitfield extract, word parity, accumulating multiplies with saturation. 
llvm-svn: 225024
 2014-12-31 00:08:34 +00:00
Colin LeMahieu
ce5a9848a5 [Hexagon] Adding double-logic on predicate instructions. 
llvm-svn: 225018
 2014-12-30 23:22:39 +00:00
Colin LeMahieu
d9937c62e9 [Hexagon] Adding newvalue compare and jumps. 
llvm-svn: 225015
 2014-12-30 23:04:21 +00:00
Colin LeMahieu
4d12863d57 [Hexagon] Adding postincrement register newvalue stores. 
llvm-svn: 225010
 2014-12-30 22:34:08 +00:00
Colin LeMahieu
e11e421bc5 [Hexagon] Removing old newvalue store variants. Adding postincrement immediate newvalue stores. 
llvm-svn: 225009
 2014-12-30 22:28:31 +00:00
Colin LeMahieu
a76ddd9ae4 [Hexagon] Adding indexed store new-value variants. 
llvm-svn: 225007
 2014-12-30 22:00:26 +00:00
Colin LeMahieu
ef54aa0778 [Hexagon] Adding indexed store of immediates. 
llvm-svn: 225006
 2014-12-30 21:01:38 +00:00
Colin LeMahieu
4a47613bb1 [Hexagon] Adding indexed stores. 
llvm-svn: 225005
 2014-12-30 20:42:23 +00:00
Colin LeMahieu
be9ae58d93 [Hexagon] Adding reg-reg indexed load forms. 
llvm-svn: 224997
 2014-12-30 18:58:47 +00:00
Colin LeMahieu
0b193a8b1c [Hexagon] Dropping old combine instructions without encodings. 
llvm-svn: 224992
 2014-12-30 17:53:54 +00:00
Colin LeMahieu
c9924ffc90 [Hexagon] Adding compare byte/halfword reg-reg/reg-imm forms. Adding compare to general register reg-imm form. 
llvm-svn: 224991
 2014-12-30 17:39:24 +00:00
Colin LeMahieu
300c89d245 [Hexagon] Updating constant extender def, adding alu-not instructions, compare to general register, and inverted compares. 
llvm-svn: 224989
 2014-12-30 15:44:17 +00:00
Colin LeMahieu
51cfbc91d9 [Hexagon] Adding allocframe, post-increment circular immediate stores, post-increment circular register stores, and bit reversed post-increment stores. 
llvm-svn: 224957
 2014-12-29 21:33:45 +00:00
Colin LeMahieu
3e609e8430 [Hexagon] Fixing 224952 where an addressing mode update was missed. 
llvm-svn: 224955
 2014-12-29 21:18:02 +00:00
Colin LeMahieu
d8726fd59b [Hexagon] Adding post-increment register form stores and register-immediate form stores with tests. 
llvm-svn: 224952
 2014-12-29 20:44:51 +00:00
Colin LeMahieu
d92e961fd1 [Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits. 
llvm-svn: 224951
 2014-12-29 20:00:43 +00:00
Colin LeMahieu
bb631541eb [Hexagon] Renaming old multiclass for removal. Adding post-increment store classes and instruction defs. 
llvm-svn: 224949
 2014-12-29 19:42:14 +00:00
Colin LeMahieu
3c20022db5 [Hexagon] Adding auto-incrementing loads with and without byte reversal. 
llvm-svn: 224871
 2014-12-26 21:09:25 +00:00
Colin LeMahieu
9363870e8a [Hexagon] Adding locked loads. 
llvm-svn: 224870
 2014-12-26 20:42:27 +00:00
Colin LeMahieu
286196b24f [Hexagon] Adding deallocframe and circular addressing loads. 
llvm-svn: 224869
 2014-12-26 20:30:58 +00:00
Colin LeMahieu
80ca4bde69 [Hexagon] Adding remaining post-increment instruction variants. Removing unused classes. 
llvm-svn: 224868
 2014-12-26 19:31:46 +00:00
Colin LeMahieu
510942bba6 [Hexagon] Adding post-increment unsigned byte loads. 
llvm-svn: 224867
 2014-12-26 19:12:11 +00:00
Colin LeMahieu
e0aad91d5f [Hexagon] Adding post-increment signed byte loads with tests. 
llvm-svn: 224866
 2014-12-26 18:57:13 +00:00
Colin LeMahieu
6ce3a834b9 [Hexagon] Removing old classes. 
llvm-svn: 224795
 2014-12-24 00:43:00 +00:00
Colin LeMahieu
3a9d8a20be [Hexagon] Adding doubleword load. 
llvm-svn: 224787
 2014-12-23 20:44:59 +00:00
Colin LeMahieu
c8d82f0149 [Hexagon] Reapplying 224775 load words. 
llvm-svn: 224786
 2014-12-23 20:02:16 +00:00
Colin LeMahieu
240787f100 Reverting 224775 until mayLoad flag is addressed. 
llvm-svn: 224783
 2014-12-23 19:22:59 +00:00
Colin LeMahieu
9d1882c36f [Hexagon] Adding word loads. 
llvm-svn: 224775
 2014-12-23 18:06:56 +00:00
Colin LeMahieu
263816de1a [Hexagon] Adding signed halfword loads. 
llvm-svn: 224774
 2014-12-23 17:25:57 +00:00
Colin LeMahieu
df751494b1 [Hexagon] Adding unsigned halfword load. 
llvm-svn: 224772
 2014-12-23 16:42:57 +00:00
Colin LeMahieu
b1f14d473d [Hexagon] Adding memb instruction. Fixing whitespace in test from 224730. 
llvm-svn: 224735
 2014-12-22 21:40:43 +00:00
Colin LeMahieu
c88fff49c9 [Hexagon] Adding classes and load unsigned byte instruction, updating usages. 
llvm-svn: 224730
 2014-12-22 21:20:03 +00:00
Colin LeMahieu
4c325f2cef [Hexagon] Removing old variants of instructions and updating references. 
llvm-svn: 224612
 2014-12-19 20:29:29 +00:00
Colin LeMahieu
b1509fe128 [Hexagon] Adding bit extraction and table indexing instructions. 
llvm-svn: 224610
 2014-12-19 20:01:08 +00:00
Colin LeMahieu
7e0cce8462 [Hexagon] Adding bit insertion instructions. 
llvm-svn: 224609
 2014-12-19 19:54:38 +00:00
Colin LeMahieu
11b6034e2b [Hexagon] Adding more xtype shift instructions. 
llvm-svn: 224608
 2014-12-19 19:51:35 +00:00
Colin LeMahieu
b6c1e97753 [Hexagon] Adding xtype shift instructions. 
llvm-svn: 224604
 2014-12-19 19:34:50 +00:00
Colin LeMahieu
16013f08b8 [Hexagon] Adding transfers to and from control registers. 
llvm-svn: 224599
 2014-12-19 19:06:32 +00:00
Colin LeMahieu
1602e43331 [Hexagon] Adding doubleregs for control registers. Renaming control register class. 
llvm-svn: 224598
 2014-12-19 18:56:10 +00:00
Colin LeMahieu
ab28d2b2e6 [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions. 
llvm-svn: 224556
 2014-12-19 00:06:53 +00:00
Colin LeMahieu
069ff897d0 Reverting 224550, was not ready for commit. 
llvm-svn: 224552
 2014-12-18 23:36:15 +00:00
Colin LeMahieu
260ab2afbd [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions. 
llvm-svn: 224550
 2014-12-18 23:27:51 +00:00
Colin LeMahieu
4316fd4269 [Hexagon] Reconfiguring register alternate names. 
llvm-svn: 224455
 2014-12-17 20:35:11 +00:00
Colin LeMahieu
55e21b6e4f [Hexagon] Updating doubleword shift usages to new versions. 
llvm-svn: 224391
 2014-12-16 23:36:15 +00:00
Colin LeMahieu
7907ae05cd [Hexagon] Removing old XTYPE/BIT instructions and replacing usages. 
llvm-svn: 224381
 2014-12-16 22:17:09 +00:00
Colin LeMahieu
5cbdca29ae [Hexagon] Adding tstbit/bitclr/bitset instructions. 
llvm-svn: 224374
 2014-12-16 21:28:58 +00:00
Colin LeMahieu
bb5c698516 [Hexagon] Adding bit count and twiddling instructions. 
llvm-svn: 224367
 2014-12-16 20:57:56 +00:00
Colin LeMahieu
28f6e273c4 [Hexagon] Adding asr/lsr/asl reg/imm, asl with saturation, asr with rounding. Doubleword abs/neg/not. Interleave and deinterleave instructions. 
llvm-svn: 224365
 2014-12-16 20:40:23 +00:00
Colin LeMahieu
4932546e48 [Hexagon] Adding absolute value, and negate with saturation 
llvm-svn: 224346
 2014-12-16 17:44:49 +00:00
Colin LeMahieu
585f29d985 [Hexagon] Adding saturate and swizzle instructions. 
llvm-svn: 224343
 2014-12-16 16:27:17 +00:00
Colin LeMahieu
c1eb9c21e5 [Hexagon] Removing old multiply defs and updating references to new versions. 
llvm-svn: 224340
 2014-12-16 16:10:01 +00:00
Colin LeMahieu
4c0e2a35a6 [Hexagon] Adding doubleword multiplies with and without accumulation. 
llvm-svn: 224293
 2014-12-16 00:07:24 +00:00
Colin LeMahieu
0a4e0a7b23 [Hexagon] Adding halfword to doubleword multiplies. 
llvm-svn: 224289
 2014-12-15 23:29:37 +00:00
Colin LeMahieu
b56764d577 [Hexagon] Adding logical-logical accumulation instructions and tests. 
llvm-svn: 224288
 2014-12-15 23:19:07 +00:00
Colin LeMahieu
a6e921963f [Hexagon] Adding a number of additional multiply forms with tests. 
llvm-svn: 224282
 2014-12-15 22:10:37 +00:00