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367 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
a80b57e5fc Add AVX version of CLMUL instructions 
llvm-svn: 109248
 2010-07-23 18:41:12 +00:00
Bruno Cardoso Lopes
b9182e3051 Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual 
llvm-svn: 109204
 2010-07-23 00:54:35 +00:00
Bruno Cardoso Lopes
7722724eee Add remaining AVX instructions (most of them dealing with GR64 destinations. This complete the assembler support for the general AVX ISA. But we still miss instructions from FMA3 and CLMUL specific feature flags, which are now the next step 
llvm-svn: 109168
 2010-07-22 21:18:49 +00:00
Bruno Cardoso Lopes
5920e38cd2 Add more 256-bit forms for a bunch of regular AVX instructions 
Add 64-bit (GR64) versions of some instructions (which are not
described in their SSE forms, but are described in AVX)

llvm-svn: 109063
 2010-07-21 23:53:50 +00:00
Bruno Cardoso Lopes
eea3b7ed83 Add missing AVX convert instructions. Those instructions are not described in their SSE forms (although they exist), but add the AVX forms anyway, so the assembler can benefit from it 
llvm-svn: 109039
 2010-07-21 21:37:59 +00:00
Bruno Cardoso Lopes
d13d8c2562 Add AVX only vzeroall and vzeroupper instructions 
llvm-svn: 109002
 2010-07-21 08:56:24 +00:00
Bruno Cardoso Lopes
c4d93a5a34 Add new AVX vpermilps, vpermilpd and vperm2f128 instructions 
llvm-svn: 108984
 2010-07-21 03:07:42 +00:00
Bruno Cardoso Lopes
a7efb29695 Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it 
llvm-svn: 108983
 2010-07-21 02:46:58 +00:00
Bruno Cardoso Lopes
e0dce1c741 Add new AVX vextractf128 instructions 
llvm-svn: 108964
 2010-07-20 23:19:02 +00:00
Matt Fleming
1d96df2bf5 Include some tests for the recently committed ELF section directive 
handlers.

llvm-svn: 108938
 2010-07-20 21:37:30 +00:00
Bruno Cardoso Lopes
b677cbc9b2 Add new AVX instruction vinsertf128 
llvm-svn: 108892
 2010-07-20 19:44:51 +00:00
Bruno Cardoso Lopes
a4ef0f6f09 x86_32 tests for vbroadcast 
llvm-svn: 108789
 2010-07-20 00:11:50 +00:00
Bruno Cardoso Lopes
88869cb4db Add AVX vbroadcast new instruction 
llvm-svn: 108788
 2010-07-20 00:11:13 +00:00
Bruno Cardoso Lopes
4ca44dda21 Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions! 
llvm-svn: 108769
 2010-07-19 23:32:44 +00:00
Daniel Dunbar
1dd74c37c5 X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same 
instruction, we only want to allow the one for the current subtarget.
 - This also fixes suffix matching for jmp instructions, because it eliminates
   the ambiguity between 'jmpl' and 'jmpq'.

llvm-svn: 108746
 2010-07-19 20:44:16 +00:00
Daniel Dunbar
220bd809bf X86-64: Mark WINCALL and more tail call instructions as code gen only. 
llvm-svn: 108685
 2010-07-19 07:21:07 +00:00
Daniel Dunbar
3b0ff3bac3 MC/X86: We now match instructions like "incl %eax" correctly for the arch we are 
assembling; remove crufty custom cleanup code.

llvm-svn: 108681
 2010-07-19 06:14:54 +00:00
Daniel Dunbar
ab21dfced5 tests: Force another triple. 
llvm-svn: 108666
 2010-07-19 00:43:58 +00:00
Daniel Dunbar
9ee59ea685 tests: Force triples. 
llvm-svn: 108658
 2010-07-18 21:16:10 +00:00
Daniel Dunbar
79350dba6e MC/AsmParser: Fix .abort and .secure_log_unique to accept arbitrary token 
sequences, not just strings.

llvm-svn: 108655
 2010-07-18 20:15:59 +00:00
Daniel Dunbar
7d498fb3fc MC/AsmParser: Add macro argument substitution support. 
llvm-svn: 108654
 2010-07-18 19:00:10 +00:00
Daniel Dunbar
312b5e0d2b MC/AsmParser: Add basic support for macro instantiation. 
llvm-svn: 108653
 2010-07-18 18:54:11 +00:00
Daniel Dunbar
4ee82b993f MC/AsmParser: Add basic parsing support for .macro definitions. 
llvm-svn: 108652
 2010-07-18 18:47:21 +00:00
Daniel Dunbar
44cddadb54 MC/AsmParser: Add .macros_{off,on} support, not that makes sense since we don't 
support macros.

llvm-svn: 108649
 2010-07-18 18:38:02 +00:00
Eli Friedman
e31ee27cbe Test for ELF .size directive. 
llvm-svn: 108607
 2010-07-17 03:15:24 +00:00
Bruno Cardoso Lopes
0616a418b6 Add AVX 256-bit compare instructions and a bunch of testcases 
llvm-svn: 108286
 2010-07-13 22:06:38 +00:00
Bruno Cardoso Lopes
7bc71d2d0a AVX 256-bit conversion instructions 
Add the x86 VEX_L form to handle special cases where VEX_L must be set.

llvm-svn: 108274
 2010-07-13 21:07:28 +00:00
Bruno Cardoso Lopes
ae37153b05 Add AVX 256-bit packed logical forms 
llvm-svn: 108224
 2010-07-13 02:38:35 +00:00
Bruno Cardoso Lopes
495ae629bb Add AVX 256-bit unop arithmetic instructions 
llvm-svn: 108223
 2010-07-13 01:53:31 +00:00
Bruno Cardoso Lopes
852e3bf472 Add AVX 256 binary arithmetic instructions 
llvm-svn: 108207
 2010-07-12 23:04:15 +00:00
Bruno Cardoso Lopes
a4889e6f93 Add AVX 256-bit MOVMSK forms 
llvm-svn: 108184
 2010-07-12 20:06:32 +00:00
Daniel Dunbar
d1c2da9d0b MC/AsmParser: Move .tbss and .zerofill parsing to Darwin specific parser. 
llvm-svn: 108180
 2010-07-12 19:37:35 +00:00
Daniel Dunbar
a1e5852feb MC/AsmParser: Move .desc parsing to Darwin specific parser. 
llvm-svn: 108179
 2010-07-12 19:22:53 +00:00
Daniel Dunbar
50b931bbac MC/AsmParser: Move some misc. Darwin directive handling to DarwinAsmParser. 
llvm-svn: 108174
 2010-07-12 18:49:22 +00:00
Bruno Cardoso Lopes
f4180a9a7b Add AVX 256-bit packed MOVNT variants 
llvm-svn: 108021
 2010-07-09 21:42:42 +00:00
Bruno Cardoso Lopes
6ca8dc935c Add AVX 256-bit unpack and interleave 
llvm-svn: 108017
 2010-07-09 21:20:35 +00:00
Bruno Cardoso Lopes
3676e24b67 Start the support for AVX instructions with 256-bit %ymm registers. A couple of 
notes:
- The instructions are being added with dummy placeholder patterns using some 256
  specifiers, this is not meant to work now, but since there are some multiclasses
  generic enough to accept them,  when we go for codegen, the stuff will be already
  there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
  file.

llvm-svn: 107996
 2010-07-09 18:27:43 +00:00
Chris Lattner
012d7537ee Rework segment prefix emission code to handle segments 
in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax

This fixes rdar://8127102.  I have several cleanup patches coming
next.

llvm-svn: 107917
 2010-07-08 22:28:12 +00:00
Chris Lattner
6a5db9c9c9 Implement the major chunk of PR7195: support for 'callw' 
in the integrated assembler.  Still some discussion to be
done.

llvm-svn: 107825
 2010-07-07 22:27:31 +00:00
Bruno Cardoso Lopes
b92b51191e Add more assembly opcodes for SSE compare instructions 
llvm-svn: 107823
 2010-07-07 22:24:03 +00:00
Bruno Cardoso Lopes
8d350872d4 Add AVX AES instructions 
llvm-svn: 107798
 2010-07-07 18:24:20 +00:00
Bruno Cardoso Lopes
6222076cd1 Add AVX SSE4.2 instructions 
llvm-svn: 107752
 2010-07-07 03:39:29 +00:00
Bruno Cardoso Lopes
675ebe2dc0 Add AVX SSE4.1 insertps, ptest and movntdqa instructions 
llvm-svn: 107747
 2010-07-07 01:14:56 +00:00
Bruno Cardoso Lopes
fa10461265 Add AVX SSE4.1 extractps and pinsr instructions 
llvm-svn: 107746
 2010-07-07 01:01:13 +00:00
Bruno Cardoso Lopes
54c2f858b3 Add AVX SSE4.1 Extract Integer instructions 
llvm-svn: 107740
 2010-07-07 00:07:24 +00:00
Bruno Cardoso Lopes
b9e1c33054 Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions 
llvm-svn: 107723
 2010-07-06 23:15:17 +00:00
Bruno Cardoso Lopes
0c6ec0b068 Add part of AVX SSE4.1 packed move with sign/zero extend instructions 
llvm-svn: 107720
 2010-07-06 23:01:41 +00:00
Bruno Cardoso Lopes
a0b37e839c Add AVX vblendvpd, vblendvps and vpblendvb instructions 
Update VEX encoding to support those new instructions

llvm-svn: 107715
 2010-07-06 22:36:24 +00:00
Bruno Cardoso Lopes
dc16024895 Add AVX SSE4.1 blend, mpsadbw and vdp 
llvm-svn: 107560
 2010-07-03 01:37:03 +00:00
Bruno Cardoso Lopes
9cbb625579 Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions 
llvm-svn: 107558
 2010-07-03 01:15:47 +00:00
Bruno Cardoso Lopes
df02d037e4 Add AVX SSE4.1 Horizontal Minimum and Position instruction 
llvm-svn: 107552
 2010-07-03 00:49:21 +00:00
Bruno Cardoso Lopes
e6b70efcb0 Add AVX SSE4.1 round instructions 
llvm-svn: 107549
 2010-07-03 00:37:44 +00:00
Bruno Cardoso Lopes
4931e183b5 - Add support for the rest of AVX SSE3 instructions 
- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode

llvm-svn: 107523
 2010-07-02 22:06:54 +00:00
Bruno Cardoso Lopes
511e5f47de Move SSE3 Move patterns to a more appropriate section 
Add AVX SSE3 packed horizontal and & sub instructions

llvm-svn: 107405
 2010-07-01 17:35:02 +00:00
Bruno Cardoso Lopes
0a3048e8b9 Add AVX SSE3 packed addsub instructions 
llvm-svn: 107404
 2010-07-01 17:08:18 +00:00
Bruno Cardoso Lopes
c1abe91367 Add AVX SSE3 replicate and convert instructions 
llvm-svn: 107375
 2010-07-01 02:33:39 +00:00
Bruno Cardoso Lopes
956316a3d7 - Add AVX SSE2 Move doubleword and quadword instructions. 
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
  in the .td file now have a AVX encoded form already working.

llvm-svn: 107365
 2010-07-01 01:20:06 +00:00
Bruno Cardoso Lopes
f8855c22be Add AVX SSE2 mask creation and conditional store instructions 
llvm-svn: 107306
 2010-06-30 18:38:10 +00:00
Bruno Cardoso Lopes
3c02702830 Add AVX SSE2 packed integer extract/insert instructions 
llvm-svn: 107293
 2010-06-30 17:03:03 +00:00
Bruno Cardoso Lopes
39594cc5d0 Add AVX SSE2 integer unpack instructions 
llvm-svn: 107246
 2010-06-30 04:06:39 +00:00
Bruno Cardoso Lopes
419f8f29c3 Add AVX SSE2 packed integer shuffle instructions 
llvm-svn: 107245
 2010-06-30 03:47:56 +00:00
Bruno Cardoso Lopes
d9acb34aa2 Add AVX SSE2 pack with saturation integer instructions 
llvm-svn: 107241
 2010-06-30 02:30:25 +00:00
Bruno Cardoso Lopes
c470ba9937 Add AVX SSE2 integer packed compare instructions 
llvm-svn: 107240
 2010-06-30 02:21:09 +00:00
Bruno Cardoso Lopes
cfbebb3921 - Add AVX form of all SSE2 logical instructions 
- Add VEX encoding bits to x86 MRM0r-MRM7r

llvm-svn: 107238
 2010-06-30 01:58:37 +00:00
Bruno Cardoso Lopes
2439877e05 Add *several* AVX integer packed binop instructions 
llvm-svn: 107225
 2010-06-29 23:47:49 +00:00
Bruno Cardoso Lopes
e1b05180de Add AVX ld/st XCSR register. 
Add VEX encoding bits for MRMXm x86 form

llvm-svn: 107204
 2010-06-29 20:35:48 +00:00
Bruno Cardoso Lopes
e60533aa42 Add AVX non-temporal stores 
llvm-svn: 107178
 2010-06-29 18:22:01 +00:00
Bruno Cardoso Lopes
2dca1dd168 Add sqrt, rsqrt and rcp AVX instructions 
llvm-svn: 107166
 2010-06-29 17:26:30 +00:00
Bruno Cardoso Lopes
e4809f15bf Described the missing AVX forms of SSE2 convert instructions 
llvm-svn: 107108
 2010-06-29 00:36:02 +00:00
Bruno Cardoso Lopes
277fcdf1c1 Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions 
llvm-svn: 106917
 2010-06-25 23:47:23 +00:00
Bruno Cardoso Lopes
45109dd6c1 Reapply r106896: 
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg

llvm-svn: 106912
 2010-06-25 23:33:42 +00:00
Bruno Cardoso Lopes
cc4c01f859 revert this now, it's using avx instead of sse :) 
llvm-svn: 106906
 2010-06-25 23:04:29 +00:00
Bruno Cardoso Lopes
04ac570a8d Add several AVX MOV flavors 
Support VEX encoding for MRMDestReg

llvm-svn: 106896
 2010-06-25 22:27:51 +00:00
Bruno Cardoso Lopes
bde2881855 Add some AVX convert instructions 
llvm-svn: 106815
 2010-06-25 00:39:30 +00:00
Bruno Cardoso Lopes
11a236d970 - Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}. 
- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.

llvm-svn: 106787
 2010-06-24 20:48:23 +00:00
Chris Lattner
606dc0529b Teach the x86 mc assembler that %dr6 = %db6, this implements 
rdar://8013734

llvm-svn: 106725
 2010-06-24 07:29:18 +00:00
Bruno Cardoso Lopes
633f345ba9 Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases 
llvm-svn: 106705
 2010-06-24 00:32:06 +00:00
Bruno Cardoso Lopes
b1bfbacead Add AVX MOVMSK{PS,PD}rr instructions 
llvm-svn: 106683
 2010-06-23 21:30:27 +00:00
Bruno Cardoso Lopes
c6ac26123d Add tests for different AVX cmp opcodes, also teach the x86 asm parser to understand the vcmp instruction 
llvm-svn: 106678
 2010-06-23 21:10:57 +00:00
Bruno Cardoso Lopes
8cfdcf7691 Add AVX SHUF{PS,PD}{rr,rm} instructions 
llvm-svn: 106672
 2010-06-23 20:07:15 +00:00
Nico Weber
04606293a5 Add support for the x86 instructions "pusha" and "popa". 
llvm-svn: 106671
 2010-06-23 20:00:58 +00:00
Bruno Cardoso Lopes
db9027d95d Add AVX compare packed instructions 
llvm-svn: 106600
 2010-06-22 23:37:59 +00:00
Bruno Cardoso Lopes
424b206ad4 Reapply support for AVX unpack and interleave instructions, with 
testcases this time.

llvm-svn: 106593
 2010-06-22 23:02:38 +00:00
Bruno Cardoso Lopes
93ec8dcd01 Add AVX MOV{SS,SD}{rr,rm} instructions 
llvm-svn: 106588
 2010-06-22 22:38:56 +00:00
Eric Christopher
48c062d65b Move a 64-bit test to the 64-bit file. Fixes an llvm-mc assertion 
during test runs.

llvm-svn: 106577
 2010-06-22 21:11:51 +00:00
Bruno Cardoso Lopes
c41dfa7cad Refactor aliased packed logical instructions, also add 
AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.

llvm-svn: 106374
 2010-06-19 02:44:01 +00:00
Bruno Cardoso Lopes
d6d12f37c6 Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions 
llvm-svn: 106366
 2010-06-19 00:37:31 +00:00
Chris Lattner
ed5a217085 fix rdar://7873482 by teaching the instruction encoder to emit 
segment prefixes.  Daniel wrote most of this patch.

llvm-svn: 106364
 2010-06-19 00:34:00 +00:00
Bruno Cardoso Lopes
ea44492375 Add {mix,max}{ss,sd}{rr,rm} AVX forms. 
llvm-svn: 106264
 2010-06-18 01:12:56 +00:00
Bruno Cardoso Lopes
7e28e6925c More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rm 
llvm-svn: 105870
 2010-06-12 01:53:48 +00:00
Bruno Cardoso Lopes
df3435eb33 More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rr 
Handle OpSize TSFlag for AVX

llvm-svn: 105869
 2010-06-12 01:23:26 +00:00
Bruno Cardoso Lopes
69141fd639 More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm) 
Introduce the VEX_X field

llvm-svn: 105859
 2010-06-11 23:50:47 +00:00
Bruno Cardoso Lopes
255fda615d Reapply r105521, this time appending "LLU" to 64 bit 
immediates to avoid breaking the build.

llvm-svn: 105652
 2010-06-08 22:51:23 +00:00
Chris Lattner
33d0622cdc revert r105521, which is breaking the buildbots with stuff like this: 
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type

llvm-svn: 105524
 2010-06-05 04:17:30 +00:00
Bruno Cardoso Lopes
b05131d907 Initial AVX support for some instructions. No patterns matched 
yet, only assembly encoding support.

llvm-svn: 105521
 2010-06-05 03:53:24 +00:00
Kevin Enderby
fbd982b12f MC/X86: Add alias for movzx. 
llvm-svn: 105005
 2010-05-28 21:20:21 +00:00
Kevin Enderby
922954fe32 MC/X86: Add alias for fwait. 
llvm-svn: 105001
 2010-05-28 20:59:10 +00:00
Kevin Enderby
3db5d4603e Fix the use of x86 control and debug registers so that the assertion failure in 
getX86RegNum() does not happen.  Patch by Shantonu Sen!

llvm-svn: 104994
 2010-05-28 19:01:27 +00:00
Kevin Enderby
7eae1aeb51 Fix the x86 move to/from segment register instructions. 
llvm-svn: 104731
 2010-05-26 20:10:45 +00:00
Kevin Enderby
392dd2b35f Changed the encoding of X86 floating point stack operations where both operands 
are st(0).  These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0.  To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used.  To do this the same logical trick is use from the darwin assembler
in converting things like this:

fmul %st(0), %st

into this:

fmul %st(0)

by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand.  This also has the add
benefit to allow things like:

fmul %st(1), %st

that llvm-mc did not assemble.

llvm-svn: 104634
 2010-05-25 20:52:34 +00:00
Daniel Dunbar
15b9844a05 MC/X86: Add a hack to allow recognizing 'cmpltps' and friends. 
llvm-svn: 104626
 2010-05-25 19:49:32 +00:00
Daniel Dunbar
28018eed17 MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}. 
llvm-svn: 104622
 2010-05-25 18:40:53 +00:00
Kevin Enderby
e336aaa32b The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required 
for the 64-bit version of the Bit Test instruction.

llvm-svn: 104621
 2010-05-25 18:16:58 +00:00
Eric Christopher
627e887b3d Make sure aeskeygenassist uses an unsigned immediate field. 
Fixes rdar://8017638

llvm-svn: 104617
 2010-05-25 17:33:22 +00:00
Dan Gohman
824858ebb0 Fix an mmx movd encoding. 
llvm-svn: 104552
 2010-05-24 20:51:08 +00:00
Kevin Enderby
a911679139 MC/X86: Add aliases for CMOVcc variants. 
llvm-svn: 104549
 2010-05-24 20:32:23 +00:00
Daniel Dunbar
50265dbaf0 MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: 
addw $0xFFFF, %ax
should match the same as
  addw $-1, %ax
but we used to match it to the longer encoding.

llvm-svn: 104453
 2010-05-22 21:02:33 +00:00
Daniel Dunbar
7c60f7caa2 MC/X86: Add alias for setz, setnz, jz, jnz. 
llvm-svn: 104435
 2010-05-22 06:37:33 +00:00
Kevin Enderby
1e4a4f5899 Added retl for 32-bit x86 and added retq for 64-bit x86. 
llvm-svn: 104394
 2010-05-21 23:01:38 +00:00
Daniel Dunbar
3a0c98ca87 MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq. 
llvm-svn: 104275
 2010-05-20 20:36:29 +00:00
Dan Gohman
c8b4555a94 Fix assembly parsing and encoding of the pushf and popf family of 
instructions.

llvm-svn: 104231
 2010-05-20 16:16:00 +00:00
Dan Gohman
52dcd5fb9a Define the x86 pause instruction. 
llvm-svn: 104204
 2010-05-20 01:35:50 +00:00
Dan Gohman
00b8752500 Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it 
doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.

llvm-svn: 104203
 2010-05-20 01:23:41 +00:00
Chris Lattner
aedd148163 fix rdar://7986634 - match instruction opcodes case insensitively. 
llvm-svn: 104183
 2010-05-19 23:34:33 +00:00
Eric Christopher
6ea9cf8425 More data/parsing support for tls directives. Add a few more testcases 
and cleanup comments as well.

llvm-svn: 103985
 2010-05-17 22:53:55 +00:00
Daniel Dunbar
8f5da3624f llvm-mc: Support reassignment of variables in one special case, when the 
variable has not yet been used in an expression. This allows us to support a few
cases that show up in real code (mostly because gcc generates it for Objective-C
on Darwin), without giving up a reasonable semantic model for assignment.

llvm-svn: 103950
 2010-05-17 17:46:23 +00:00
Eric Christopher
950f0d7892 Assume that we'll handle mangling the symbols earlier and just put the 
symbol to the file as we have it.  Simplifies out tbss handling.

llvm-svn: 103928
 2010-05-17 02:13:02 +00:00
Kevin Enderby
dc13d89540 Fix so "int3" is correctly accepted, added "into" and fixed "int" with an 
argument, like "int $4", to not get an Assertion error.

llvm-svn: 103791
 2010-05-14 19:16:02 +00:00
Eric Christopher
ebea91f168 Add AsmParser support for darwin tbss directive. 
Nothing uses this yet.

llvm-svn: 103757
 2010-05-14 01:50:28 +00:00
Chris Lattner
ca57d80f83 fix rdar://7965971 and a fixme: use ParseIdentifier in 
ParseDirectiveDarwinZerofill instead of hard coding the
check for identifier. This allows quoted symbol names to
be used.

llvm-svn: 103682
 2010-05-13 00:10:34 +00:00
Chris Lattner
887e8f9f53 reapply r103668 with a fix. Never make "minor syntax changes" 
after testing before committing.

llvm-svn: 103681
 2010-05-13 00:02:47 +00:00
Chris Lattner
361c115f23 revert r103668 for now, it is apparently breaking things. 
llvm-svn: 103677
 2010-05-12 23:40:59 +00:00
Chris Lattner
91a836a9c7 moffset forms of moves are x86-32 only, make the parser 
lower them to the correct x86-64 instructions since we 
don't have a clean way to handle this in td files yet.
rdar://7947184

llvm-svn: 103668
 2010-05-12 23:13:36 +00:00
Chris Lattner
1960255123 fix the encoding of the obscure "moffset" forms of moves, i386 
part first.  rdar://7947184

llvm-svn: 103660
 2010-05-12 22:48:24 +00:00
Daniel Dunbar
469dddef0e MC/X86: Extend suffix matching hack to match 'q' suffix. 
llvm-svn: 103535
 2010-05-12 00:54:20 +00:00
Daniel Dunbar
45589cd853 MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand. 
- This fixes "leal 0, %eax", for example.

llvm-svn: 103205
 2010-05-06 22:39:14 +00:00
Chris Lattner
c788971da7 fix rdar://7947167 - llvm-mc doesn't match movsq 
llvm-svn: 103199
 2010-05-06 21:48:14 +00:00
Daniel Dunbar
a3731b17c0 Revert r103137, fix for $ in labels. It looks like we can't actually handle this 
at the token level. Consider the following horrible test case:

  a = 1
  .globl $a
  movl ($a), %eax
  movl $a, %eax
  movl $$a, %eax

llvm-svn: 103178
 2010-05-06 14:46:38 +00:00
Chris Lattner
ca80f41a4d fix rdar://7946934 - in some limited cases, the assembler should 
allow $ at the start of a symbol name.

llvm-svn: 103137
 2010-05-05 23:51:28 +00:00
Daniel Dunbar
e335a71a56 MC/X86: Chris pointed that 'as' isn't consistent in accepting the long form of 
instructions which have no direct register usage.

Darwin 'as' accepts:
  add $0, (%rax)
but rejects
  mov $0, (%rax)
for example.

Given that, only accept suffix matches which match exactly one form. We still
need to emit nice diagnostics for failures...

llvm-svn: 103015
 2010-05-04 17:31:02 +00:00
Daniel Dunbar
648d1ae783 MC/X86: Add "support" for matching ATT style mnemonic prefixes. 
- The idea is that when a match fails, we just try to match each of +'b', +'w',
   +'l'. If exactly one matches, we assume this is a mnemonic prefix and accept
   it. If all match, we assume it is width generic, and take the 'l' form.

 - This would be a horrible hack, if it weren't so simple. Therefore it is an
   elegant solution! Chris gets the credit for this particular elegant
   solution. :)

 - Next step to making this more robust is to have the X86 matcher generate the
   mnemonic prefix information. Ideally we would also compute up-front exactly
   which mnemonic to attempt to match, but this may require more custom code in
   the matcher than is really worth it.

llvm-svn: 103012
 2010-05-04 16:12:42 +00:00
Kevin Enderby
ce7a24a57f Changed llvm-mc to use the same suffixes with floating point compare 
instructions as the Mac OS X darwin assembler.  Some of which like 'fcoml'
assembled to different opcodes.  While some of the suffixes were just different.

llvm-svn: 102958
 2010-05-03 21:31:40 +00:00
Kevin Enderby
be2804f752 Fixed the encoding of two of the X86 movq instuctions. The Move quadword from 
mm to mm/m64 and the Move quadword from xmm2/mem64 to xmm1 had the incorrect
encodings.

llvm-svn: 102952
 2010-05-03 21:03:31 +00:00
Kevin Enderby
c1eeb061e7 Fixed the encoding of the x86 push instructions. Using a 32-bit immediate value 
caused the a pushl instruction to be incorrectly encoding using only two bytes
of immediate, causing the following 2 instruction bytes to be part of the 32-bit
immediate value.  Also fixed the one byte form of push to be used when the
immediate would fit in a signed extended byte.  Lastly changed the names to not
include the 32 of PUSH32 since they actually push the size of the stack pointer.

llvm-svn: 102951
 2010-05-03 20:45:05 +00:00
Kevin Enderby
58bed5a913 Fixed the word sized Bit Scan Forward/Reverse instructions, they needed the 
Operand size override prefix to be part of their records.

llvm-svn: 102556
 2010-04-28 23:20:40 +00:00
Chris Lattner
65d1e40895 teach the x86 asm parser how to handle segment prefixes 
in memory operands.  rdar://7874844

llvm-svn: 101661
 2010-04-17 18:56:34 +00:00
Chris Lattner
42337931b2 a bunch of ssse3 instructions are misencoded to think they have an 
i8 field when they really do not.  This fixes rdar://7840289

llvm-svn: 101629
 2010-04-17 07:38:24 +00:00
Chris Lattner
124dc743bc implement mc asmparser support for '.', which gets the 
current PC.  rdar://7834775

We now produce an identical .o file compared to the cctools
assembler for something like this:

_f0:
L0:
        jmp L1
        .long . - L0
L1:
        jmp A
        .long . - L1

        .zerofill __DATA,_bss,A,0

llvm-svn: 101227
 2010-04-14 04:40:28 +00:00
Bob Wilson
04e9ff15cb Reapply Kevin's change 94440, now that Chris has fixed the limitation on 
opcode values fitting in one byte (svn r99494).

llvm-svn: 99514
 2010-03-25 16:36:14 +00:00
Bob Wilson
d5673d9f1f Speculatively revert this to see if it fixes buildbot failures. 
--- Reverse-merging r99440 into '.':
U    test/MC/AsmParser/X86/x86_32-bit_cat.s
U    test/MC/AsmParser/X86/x86_32-encoding.s
U    include/llvm/IntrinsicsX86.td
U    include/llvm/CodeGen/SelectionDAGNodes.h
U    lib/Target/X86/X86InstrSSE.td
U    lib/Target/X86/X86ISelLowering.h

llvm-svn: 99450
 2010-03-24 23:26:29 +00:00
Kevin Enderby
9cab7fdb12 Added the Advanced Encryption Standard (AES) Instructions. 
llvm-svn: 99440
 2010-03-24 22:33:33 +00:00
Kevin Enderby
8d8cb5c491 Fixed the SS42AI template for the SSE 4.2 instructions with TA prefix so it does 
not get an "Unknown immediate size" assert failure when used.  All instructions 
of this form have an 8-bit immediate.  Also added a test case of an example
instruction that is of this form.

llvm-svn: 99435
 2010-03-24 22:28:42 +00:00
Kevin Enderby
766909ae3b Fixed the encoding problems of the crc32 instructions. All had the Operand size 
override prefix and only the r/m16 forms should have had that.  Also for variant
one, the AT&T syntax, added suffixes to all forms.  Also added the missing
64-bit form for 'CRC32 r64, r/m8'.  Plus added test cases for all forms and
tweaked one test case to add the needed suffixes.

llvm-svn: 98980
 2010-03-19 20:04:42 +00:00
Daniel Dunbar
f803121396 MC/X86: Rename alternate spellings of {ADD64,CMP64} and mark as "code gen only" so they don't get selected by the asm matcher. 
llvm-svn: 98972
 2010-03-19 18:07:48 +00:00
Daniel Dunbar
3ef39d497f X86: Fix encoding for TEST64rr. 
llvm-svn: 98919
 2010-03-19 01:15:03 +00:00
Daniel Dunbar
1a50b05aff X86MCCodeEmitter: Fix two minor issues with reloc_riprel_4byte_movq_load, we 
were missing it on some movq instructions and were not including the appropriate
PCrel bias.

llvm-svn: 98880
 2010-03-18 21:53:54 +00:00
Daniel Dunbar
ab14df376a MC/X86/AsmMatcher: Use the new instruction cleanup routine to implement a 
temporary workaround for matching inc/dec on x86_64 to the correct instruction.
 - This hack will eventually be replaced with a robust mechanism for handling
   matching instructions based on the available target features.

llvm-svn: 98858
 2010-03-18 20:06:02 +00:00
Chris Lattner
bf3e096258 fix an x86-64 encoding bug Daniel found. 
llvm-svn: 98855
 2010-03-18 20:04:36 +00:00
Chris Lattner
45ab55ccec add a special relocation type for movq loads for object 
files that produce special relocation types where the 
linker changes movq's into lea's.

llvm-svn: 98839
 2010-03-18 18:10:56 +00:00
Chris Lattner
3e251f1db0 xfail these tests temporarily to get teh buildbots back to happy land. 
llvm-svn: 98476
 2010-03-14 07:32:48 +00:00