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20815 Commits

Author SHA1 Message Date
James Molloy
85be8f7f88 Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage. 
llvm-svn: 150169
 2012-02-09 10:56:31 +00:00
Craig Topper
c20605c287 More tweaks to get the size of the X86 disassembler tables down. 
llvm-svn: 150167
 2012-02-09 08:58:07 +00:00
Craig Topper
82b0ee4558 Flatten some of the arrays in the X86 disassembler tables to reduce space needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953. 
llvm-svn: 150161
 2012-02-09 07:45:30 +00:00
Jakob Stoklund Olesen
27f005d12d Handle register masks when searching for EFLAGS clobbers. 
Calls clobber the flags, but when using register masks there is no
EFLAGS<imp-def> operand.

llvm-svn: 150117
 2012-02-09 00:17:22 +00:00
Andrew Trick
b9d2e9e81d Codegen pass definition cleanup. No functionality. 
Moving toward a uniform style of pass definition to allow easier target configuration.
Globally declare Pass ID.
Globally declare pass initializer.
Use INITIALIZE_PASS consistently.
Add a call to the initializer from CodeGen.cpp.
Remove redundant "createPass" functions and "getPassName" methods.

While cleaning up declarations, cleaned up comments (sorry for large diff).

llvm-svn: 150100
 2012-02-08 21:23:13 +00:00
Andrew Trick
c210c552ee Move pass configuration out of pass constructors: StackSlotColoring. 
llvm-svn: 150097
 2012-02-08 21:22:57 +00:00
Andrew Trick
a6dea8798a Move pass configuration out of pass constructors: PostRAScheduler. 
llvm-svn: 150096
 2012-02-08 21:22:53 +00:00
Andrew Trick
9da1cc8ddd Move pass configuration out of pass constructors: BranchFolderPass 
llvm-svn: 150095
 2012-02-08 21:22:48 +00:00
Andrew Trick
fb24596a02 Added TargetPassConfig::setOpt 
llvm-svn: 150093
 2012-02-08 21:22:39 +00:00
Andrew Trick
e696d2f01f Move pass configuration out of pass constructors: TailDuplicate::PreRegAlloc 
llvm-svn: 150091
 2012-02-08 21:22:30 +00:00
Brendon Cahoon
39fcf7dc1b Use TSFlag bit to describe instruction properties. 
Creating the isPredicated TSFlag enables the code
to use the property defined in the instruction format
instead of using a large switch statement.

llvm-svn: 150078
 2012-02-08 18:25:47 +00:00
Elena Demikhovsky
87a6e08d3a Fixed a bug in printing "cmp" pseudo ops. 
> This IR code
> %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 14)
> fails with assertion:
>
> llc: X86ATTInstPrinter.cpp:62: void llvm::X86ATTInstPrinter::printSSECC(const llvm::MCInst*, unsigned int, llvm::raw_ostream&): Assertion `0 && "Invalid ssecc argument!"' failed.
> 0  llc             0x0000000001355803
> 1  llc             0x0000000001355dc9
> 2  libpthread.so.0 0x00007f79a30575d0
> 3  libc.so.6       0x00007f79a23a1945 gsignal + 53
> 4  libc.so.6       0x00007f79a23a2f21 abort + 385
> 5  libc.so.6       0x00007f79a239a810 __assert_fail + 240
> 6  llc             0x00000000011858d5 llvm::X86ATTInstPrinter::printSSECC(llvm::MCInst const*, unsigned int, llvm::raw_ostream&) + 119

I added the full testing for all possible pseudo-ops of cmp.
I extended X86AsmPrinter.cpp and X86IntelInstPrinter.cpp.

You'l also see lines alignments (unrelated to this fix) in X86IselLowering.cpp from my previous check-in.

llvm-svn: 150068
 2012-02-08 08:37:26 +00:00
Craig Topper
f19c739d2d Remove a couple unneeded intrinsic patterns 
llvm-svn: 150067
 2012-02-08 08:29:30 +00:00
Craig Topper
6dbd5e534c Remove GCC builtins for vpermilp* intrinsics as clang no longer needs them. Custom lower the intrinsics to the vpermilp target specific node and remove intrinsic patterns. 
llvm-svn: 150060
 2012-02-08 06:36:57 +00:00
Chad Rosier
b70d1dfae6 [fast-isel] Add support for SUBs with non-legal types. 
llvm-svn: 150047
 2012-02-08 02:45:44 +00:00
Chad Rosier
1ef78d6989 [fast-isel] Add support for ORs with non-legal types. 
llvm-svn: 150045
 2012-02-08 02:29:21 +00:00
Chad Rosier
26610906f0 [fast-isel] Add support for indirect branches. 
llvm-svn: 150014
 2012-02-07 23:56:08 +00:00
Evan Cheng
ab4ad855cc Use LEA to adjust stack ptr for Atom. Patch by Andy Zhang. 
llvm-svn: 150008
 2012-02-07 22:50:41 +00:00
Evan Cheng
653966d99b Do not fold ADD / SUB into load / store (to form pre-indexed, post-indexed 
load / store) if the ADD / SUB has a live definition of CPSR.

Bug reported by David Meyer. Alas, no test case.

llvm-svn: 149970
 2012-02-07 07:09:28 +00:00
Craig Topper
a8a69356e1 Add instruction selection for 256-bit VPSHUFD and 128-bit VPERMILPS/VPERMILPD. 
llvm-svn: 149968
 2012-02-07 06:28:42 +00:00
Craig Topper
11bcb12b5e Convert assert(0) to llvm_unreachable 
llvm-svn: 149961
 2012-02-07 02:50:20 +00:00
Chad Rosier
945ab43c4f [fast-isel] Add support for ADDs with non-legal types. 
llvm-svn: 149934
 2012-02-06 23:50:07 +00:00
Andrew Trick
4f5b6f7f93 Add TargetPassConfig to the PassManager for use inside passes 
llvm-svn: 149926
 2012-02-06 22:51:15 +00:00
Derek Schuff
f522835510 Enable streaming of bitcode 
This CL delays reading of function bodies from initial parse until
materialization, allowing overlap of compilation with bitcode download.

llvm-svn: 149918
 2012-02-06 22:30:29 +00:00
Chris Lattner
7a6bd0185e Remove some dead code and tidy things up now that vectors use ConstantDataVector 
instead of always using ConstantVector.

llvm-svn: 149912
 2012-02-06 21:56:39 +00:00
Bill Wendling
4e92f798ff [unwind removal] We no longer have 'unwind' instructions being generated, so 
remove the code that handles them.

llvm-svn: 149901
 2012-02-06 21:16:41 +00:00
Benjamin Kramer
3443a8294a X86: Don't call malloc for 4 bits. No functionality change. 
llvm-svn: 149866
 2012-02-06 12:06:18 +00:00
Benjamin Kramer
db46bec410 Hexagon: Remove forbidden iostream includes (it introduces static initializers) 
Reorder includes while at it.

llvm-svn: 149863
 2012-02-06 10:19:29 +00:00
Craig Topper
74416bcd0e Add shuffle decoding support for 256-bit pshufd. Merge vpermilp* and pshufd decoding. 
llvm-svn: 149859
 2012-02-06 07:17:51 +00:00
Evan Cheng
f5efaef65b DefinesPredicate should only look for def operands. Patch by Ludwig Meier. 
llvm-svn: 149846
 2012-02-05 19:55:04 +00:00
Duncan Sands
13ce9d000a Remove dead test: this was already checked and handled a few lines 
above.

llvm-svn: 149841
 2012-02-05 19:30:06 +00:00
Duncan Sands
cc472eec96 Persuade GCC that there is nothing worth warning about here (there isn't). 
llvm-svn: 149834
 2012-02-05 14:20:11 +00:00
Duncan Sands
c1b9cbec06 Don't initialize CV in terms of itself! Spotted by GCC. 
llvm-svn: 149833
 2012-02-05 14:16:09 +00:00
Chandler Carruth
9db1b1bb0a Begin fleshing out more convenience predicates in llvm::Triple and 
convert at least one client over to use them. Subsequent patches both to
LLVM and Clang will try to convert more people over to a common set of
predicates.

This round of predicates is focused on OS-categorization predicates.

llvm-svn: 149815
 2012-02-05 08:26:40 +00:00
Craig Topper
dfa8617ab9 Convert assert(0) to llvm_unreachable 
llvm-svn: 149814
 2012-02-05 07:21:30 +00:00
Craig Topper
fe4a950689 Convert assert(0) to llvm_unreachable in X86 Target directory. 
llvm-svn: 149809
 2012-02-05 05:38:58 +00:00
Craig Topper
7b7867bbaa Convert some assert(0) in default of switch statements to llvm_unreachable. 
llvm-svn: 149808
 2012-02-05 03:43:23 +00:00
Craig Topper
07b9d056fa Add target specific node for PMULUDQ. Change patterns to use it and custom lower intrinsics to it. Use it instead of intrinsic to handle 64-bit vector multiplies. 
llvm-svn: 149807
 2012-02-05 03:14:49 +00:00
Chris Lattner
9782adedd7 reapply the patches reverted in r149470 that reenable ConstantDataArray, 
but with a critical fix to the SelectionDAG code that optimizes copies
from strings into immediate stores: the previous code was stopping reading
string data at the first nul.  Address this by adding a new argument to
llvm::getConstantStringInfo, preserving the behavior before the patch.

llvm-svn: 149800
 2012-02-05 02:29:43 +00:00
Craig Topper
c289726019 Remove most of the intrinsics for XOP VPCMOV instruction. They all aliased to the same instruction with different types. This would be better accomplished with casts in the not yet created xopintrin.h header file. 
llvm-svn: 149795
 2012-02-05 00:55:56 +00:00
Andrew Trick
fb574d1c19 TargetPassConfig: confine the MC configuration to TargetMachine. 
Passes prior to instructon selection are now split into separate configurable stages.
Header dependencies are simplified.
The bulk of this diff is simply removal of the silly DisableVerify flags.

Sorry for the target header churn. Attempting to stabilize them.

llvm-svn: 149754
 2012-02-04 02:56:59 +00:00
Chad Rosier
a6e543e80b [fast-isel] Add support for URem. 
llvm-svn: 149716
 2012-02-03 21:23:45 +00:00
Chad Rosier
6de31d433d [fast-isel] Rename isZExt to isSigned. No functional change intended. 
llvm-svn: 149714
 2012-02-03 21:14:11 +00:00
Chad Rosier
fc667757e8 [fast-isel] Add support for UDIV. 
llvm-svn: 149712
 2012-02-03 21:07:27 +00:00
Chad Rosier
cff3c98417 [fast-isel] Add support for FPToUI. Also add test cases for FPToSI. 
llvm-svn: 149706
 2012-02-03 20:27:51 +00:00
Chad Rosier
40b3e74387 [fast-isel] Add support for selecting UIToFP. 
llvm-svn: 149704
 2012-02-03 19:42:52 +00:00
Craig Topper
dee5f41723 Remove getShuffleVPERMILPImmediate function, getShuffleSHUFImmediate performs the same calculation. 
llvm-svn: 149683
 2012-02-03 06:52:33 +00:00
Craig Topper
afb89fb5f9 Remove unnecessary qualification on 256-bit vector handling in LowerBUILD_VECTOR. Condition was already guaranteed by earlier code. 
llvm-svn: 149680
 2012-02-03 06:32:21 +00:00
Andrew Trick
da0c52e742 Added TargetPassConfig. The first little step toward configuring codegen passes. 
Allows command line overrides to be centralized in LLVMTargetMachine.cpp.
LLVMTargetMachine can intercept common passes and give precedence to command line overrides.
Allows adding "internal" target configuration options without touching TargetOptions.
Encapsulates the PassManager.
Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs.
Allows modifying the target configuration hooks without rebuilding the world.

llvm-svn: 149672
 2012-02-03 05:12:41 +00:00
Andrew Trick
0838f6788a whitespace 
llvm-svn: 149671
 2012-02-03 05:12:30 +00:00
Akira Hatanaka
874523adc5 Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is 
needed to emit a 64-bit gp-relative relocation entry. Make changes necessary
for emitting jump tables which have entries with directive .gpdword. This patch
does not implement the parts needed for direct object emission or JIT.

llvm-svn: 149668
 2012-02-03 04:33:00 +00:00
Lang Hames
311e44bd42 Incorporate suggestions Chad, Jakob and Evan's suggestions on r149957. 
llvm-svn: 149655
 2012-02-03 01:13:49 +00:00
Jakob Stoklund Olesen
b84880cf78 Require non-NULL register masks. 
It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.

llvm-svn: 149646
 2012-02-02 23:52:57 +00:00
Jakob Stoklund Olesen
5c71bf1b0e Add pseudo-registers for pairs, triples, and quads of D registers. 
NEON loads and stores accept single and double spaced pairs, triples,
and quads of D registers.  This patch adds new register classes to
accurately model those constraints:

  Dn, Dn+1    Dn, Dn+2
  ----------------------
  DPair       DPairSpc
  DTriple     DTripleSpc
  DQuad       DQuadSpc

Also extend the existing QQ and QQQQ register classes to contains all Q
pairs and quads instead of just the aligned ones.

These new register classes will make it possible to accurately model
constraints on NEON loads and stores, and we can get rid of all the NEON
pseudo-instructions.  The late scheduler will be able to accurately
model instruction dependencies from the explicit operands.

This more than doubles the number of ARM registers, but the backend
passes are quite good at handling this. The llc -O0 compile time only
regresses by 1.5%.  Future work on register mask operands will recover
this regression.

llvm-svn: 149640
 2012-02-02 22:45:32 +00:00
Elena Demikhovsky
00f62e0e9f Minor change in signature of the getZeroVector() 
llvm-svn: 149601
 2012-02-02 09:20:18 +00:00
Elena Demikhovsky
7ca11b6e3f Optimization for SIGN_EXTEND operation on AVX. 
Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32
extensions.

llvm-svn: 149600
 2012-02-02 09:10:43 +00:00
Francois Pichet
0f41b565e8 Unbreak the MSVC build. 
llvm-svn: 149599
 2012-02-02 08:36:09 +00:00
Lang Hames
004f627ed6 Set EFLAGS correctly in EmitLoweredSelect on X86. 
llvm-svn: 149597
 2012-02-02 07:48:37 +00:00
Akira Hatanaka
54552b8fa7 Set the correct stack pointer register. 
llvm-svn: 149585
 2012-02-02 03:17:04 +00:00
Akira Hatanaka
4319eaf8b7 Expand EHSELECTION and EHSELECTION nodes. Set the correct exception pointer and 
selector registers.
 

llvm-svn: 149584
 2012-02-02 03:13:40 +00:00
Akira Hatanaka
88e74ead4b Add DWARF numbers of 64-bit registers. 
llvm-svn: 149583
 2012-02-02 02:56:14 +00:00
Rafael Espindola
a223881c4a Fix the cmake build 
llvm-svn: 149561
 2012-02-01 23:40:51 +00:00
Andrew Trick
d09b64fc25 Instruction scheduling itinerary for Intel Atom. 
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.

Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.

Adds a test to verify that the scheduler is working.

Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.

Patch by Preston Gurd!

llvm-svn: 149558
 2012-02-01 23:20:51 +00:00
Jakob Stoklund Olesen
1410489492 Move ARM subreg index compositions to the SubRegIndex itself. 
llvm-svn: 149557
 2012-02-01 23:16:43 +00:00
Mon P Wang
7313ffe333 Avoid creating an extract element to an illegal type after LegalizeTypes has run. 
llvm-svn: 149548
 2012-02-01 22:15:20 +00:00
Andrew Trick
b4963dd8da VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA). 
This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling.

Patch by Sergei Larin!

llvm-svn: 149547
 2012-02-01 22:13:57 +00:00
Chad Rosier
9c3c30332f Tidy up. 
llvm-svn: 149521
 2012-02-01 18:45:51 +00:00
Elena Demikhovsky
455db87d41 Passing AVX 256-bit structures in Win64 was wrong. 
Fixed Win64 calling conventions.

llvm-svn: 149494
 2012-02-01 10:46:14 +00:00
Elena Demikhovsky
f63bfb1b5d Shortened code in shuffle masks 
llvm-svn: 149493
 2012-02-01 10:33:05 +00:00
Elena Demikhovsky
da37eb48d8 Optimization for "truncate" operation on AVX. 
Truncating v4i64 -> v4i32 and v8i32 -> v8i16 may be done with set of shuffles.

llvm-svn: 149485
 2012-02-01 07:56:44 +00:00
Stepan Dyatkovskiy
856ca370cc SwitchInst refactoring. 
The purpose of refactoring is to hide operand roles from SwitchInst user (programmer). If you want to play with operands directly, probably you will need lower level methods than SwitchInst ones (TerminatorInst or may be User). After this patch we can reorganize SwitchInst operands and successors as we want.

What was done:

1. Changed semantics of index inside the getCaseValue method:
getCaseValue(0) means "get first case", not a condition. Use getCondition() if you want to resolve the condition. I propose don't mix SwitchInst case indexing with low level indexing (TI successors indexing, User's operands indexing), since it may be dangerous.
2. By the same reason findCaseValue(ConstantInt*) returns actual number of case value. 0 means first case, not default. If there is no case with given value, ErrorIndex will returned.
3. Added getCaseSuccessor method. I propose to avoid usage of TerminatorInst::getSuccessor if you want to resolve case successor BB. Use getCaseSuccessor instead, since internal SwitchInst organization of operands/successors is hidden and may be changed in any moment.
4. Added resolveSuccessorIndex and resolveCaseIndex. The main purpose of these methods is to see how case successors are really mapped in TerminatorInst.
4.1 "resolveSuccessorIndex" was created if you need to level down from SwitchInst to TerminatorInst. It returns TerminatorInst's successor index for given case successor.
4.2 "resolveCaseIndex" converts low level successors index to case index that curresponds to the given successor.

Note: There are also related compatability fix patches for dragonegg, klee, llvm-gcc-4.0, llvm-gcc-4.2, safecode, clang.
llvm-svn: 149481
 2012-02-01 07:49:51 +00:00
Craig Topper
79859da905 Don't create VBROADCAST nodes if any nodes use the chain result from the load. Fixes PR11900. 
llvm-svn: 149478
 2012-02-01 06:51:58 +00:00
Argyrios Kyrtzidis
492f34016f Revert Chris' commits up to r149348 that started causing VMCoreTests unit test to fail. 
These are:

r149348
r149351
r149352
r149354
r149356
r149357
r149361
r149362
r149364
r149365

llvm-svn: 149470
 2012-02-01 04:51:17 +00:00
Jim Grosbach
b4cc72d103 Tidy up. One more return type mismatch fix. 
llvm-svn: 149452
 2012-01-31 23:51:09 +00:00
Jim Grosbach
2f211187f7 Refactor loop for better readability. 
Excellent suggestion from Ben Kramer.

llvm-svn: 149417
 2012-01-31 20:56:55 +00:00
Jim Grosbach
5a7c34d3ef Add explanatory comment. 
llvm-svn: 149416
 2012-01-31 20:34:53 +00:00
Devang Patel
b8688eac99 Add assembler dialect attribute in asm parser which lets target specific asm parser change dialect on the fly. 
llvm-svn: 149396
 2012-01-31 18:14:05 +00:00
Craig Topper
2b764de6ab Remove pcmpgt/pcmpeq intrinsics as clang is not using them. 
llvm-svn: 149367
 2012-01-31 06:52:44 +00:00
Chris Lattner
06407b2f81 with recent changes, ConstantArray is never a "string". Remove the associated 
methods and constant fold the clients to false.

llvm-svn: 149362
 2012-01-31 06:05:00 +00:00
Chris Lattner
8f102298a0 use the right accessor for ConstantDataArray. 
llvm-svn: 149342
 2012-01-31 03:16:39 +00:00
Evan Cheng
111c0844d5 PR11834: Use macros which are defined on Windows. Patch by Marina Yatsina. 
llvm-svn: 149294
 2012-01-30 23:10:32 +00:00
Devang Patel
be1817e3e0 Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax. 
llvm-svn: 149291
 2012-01-30 22:47:12 +00:00
Devang Patel
a5bfdedb9f Intel syntax. Support .intel_syntax directive. 
llvm-svn: 149270
 2012-01-30 20:02:42 +00:00
Benjamin Kramer
0a88f2966a Fix refacto. 
llvm-svn: 149269
 2012-01-30 20:01:35 +00:00
Douglas Gregor
9deae777e2 Eliminate narrowing conversion in initializer list, to make C++11 happy 
llvm-svn: 149254
 2012-01-30 16:57:18 +00:00
Benjamin Kramer
af9ce50196 X86: Simplify shuffle mask generation code. 
llvm-svn: 149248
 2012-01-30 15:16:21 +00:00
Craig Topper
9a8c6c1633 Fix pattern for memory form of PSHUFD for use with FP vectors to remove bitcast to an integer vector that normal code wouldn't have. Also remove bitcasts from code that turns splat vector loads into a shuffle as it was making the broken pattern necessary. 
llvm-svn: 149232
 2012-01-30 07:50:31 +00:00
Craig Topper
9aabdda961 Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic patterns with custom lowering to a target specific nodes. 
llvm-svn: 149216
 2012-01-30 01:10:15 +00:00
Anton Korobeynikov
8610339991 Cleanups for EABI standard functions 
llvm-svn: 149195
 2012-01-29 09:11:50 +00:00
Anton Korobeynikov
37494ab91a Use base AAPCS for varargs functions even for AAPCS-VFP CC 
llvm-svn: 149194
 2012-01-29 09:06:09 +00:00
Bob Wilson
157561c941 Add a note about a potential optimization for clz/ctz patterns for ARM 
(and other targets).

llvm-svn: 149182
 2012-01-28 18:30:07 +00:00
James Molloy
b586b7c9c7 Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends. 
Fixes PR11877

llvm-svn: 149180
 2012-01-28 15:58:32 +00:00
Devang Patel
e4725ba181 Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320] 
llvm-svn: 149142
 2012-01-27 19:48:28 +00:00
Craig Topper
9259da4826 Move some patterns back near their instructions and use AddedComplexity to fix priority. Merge some patterns into their instruction definition. 
llvm-svn: 149122
 2012-01-27 07:09:40 +00:00
Jim Grosbach
e6ac20aadf Keep source location information for X86 MCFixup's. 
llvm-svn: 149106
 2012-01-27 00:51:27 +00:00
Jim Grosbach
ef5d3dc085 Better user diagnostics for more ARM MachO relocation errors. 
llvm-svn: 149102
 2012-01-27 00:37:12 +00:00
Jim Grosbach
6280a1137f Better diagnostic for malformed .org assembly directive. 
Provide source line number information.

llvm-svn: 149101
 2012-01-27 00:37:08 +00:00
Jim Grosbach
44913df963 Keep source information, if available, around for ARM Fixups. 
Adjust an example MachObjectWriter diagnostic to use the information
to issue a better message.

Before:
LLVM ERROR: unknown ARM fixup kind!

After:
x.s:6:5: error: unsupported relocation on symbol
    beq bar
    ^

rdar://9800182

llvm-svn: 149093
 2012-01-26 23:20:15 +00:00
Jakob Stoklund Olesen
c63a45ebe6 Handle call-clobbered ymm registers on Win64. 
The Win64 calling convention has xmm6-15 as callee-saved while still
clobbering all ymm registers.

Add a YMM_HI_6_15 pseudo-register that aliases the clobbered part of the
ymm registers, and mark that as call-clobbered.  This allows live xmm
registers across calls.

This hack wouldn't be necessary with RegisterMask operands representing
the call clobbers, but they are not quite operational yet.

llvm-svn: 149088
 2012-01-26 22:59:28 +00:00
Jim Grosbach
45722b499a Tidy up. Fix mismatched return types for error handling. 
llvm-svn: 149062
 2012-01-26 15:56:45 +00:00
James Molloy
402abeda73 Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors. 
This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.

llvm-svn: 149057
 2012-01-26 09:25:43 +00:00
Victor Umansky
bf35274368 Fix for the following bug in AVX codegen for double-to-int conversions: 
.	"fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode.
.	Currently for AVX mode for <4xdouble> and <8xdouble>  the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for .fp_to_sint. DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode.
.	Consequently, the conversion produces incorrect numbers.
 
The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode. 
As .fp_to_sint. DAG node operation is used only for lowering of  "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn.t have an impact on other LLVM flows.
 
The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec). 

llvm-svn: 149056
 2012-01-26 08:51:39 +00:00
Craig Topper
8f8e428400 Add HasXOP predicate check covering a bunch of XOP intrinsic patterns. 
llvm-svn: 149054
 2012-01-26 07:51:55 +00:00
Craig Topper
814a037ac6 Fix AVX vs SSE patterns ordering issue for VPCMPESTRM and VPCMPISTRM. 
llvm-svn: 149053
 2012-01-26 07:31:30 +00:00
Craig Topper
7ed643d290 Remove some more patterns by custom lowering intrinsics to target specific nodes. 
llvm-svn: 149052
 2012-01-26 07:18:03 +00:00
Anton Korobeynikov
682b2821ce Properly emit ctors / dtors with priorities into desired sections 
and let linker handle the rest.

This finally fixes PR5329

llvm-svn: 148990
 2012-01-25 22:24:19 +00:00
Jim Grosbach
20a6580dff ARM assemly parsing and validation of IT instruction. 
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."

PR11853

llvm-svn: 148969
 2012-01-25 19:52:01 +00:00
Chris Lattner
a6642a918d fix a bug I introduced in r148929, this is not a splat! 
Thanks to Eli for noticing.

llvm-svn: 148947
 2012-01-25 09:56:22 +00:00
Craig Topper
c2b030401c Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns. 
llvm-svn: 148933
 2012-01-25 06:43:11 +00:00
Chris Lattner
473bdbaabc use ConstantVector::getSplat in a few places. 
llvm-svn: 148929
 2012-01-25 06:02:56 +00:00
Craig Topper
9edaa5c15a Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary. 
llvm-svn: 148927
 2012-01-25 05:37:32 +00:00
Craig Topper
c968a4ccc9 Remove AVX 256-bit unaligned load intrinsics. 128-bit versions had been removed a while ago. 
llvm-svn: 148922
 2012-01-25 04:42:03 +00:00
Akira Hatanaka
d4dbda9412 Mark 64-bit register RA_64 unused too. 
llvm-svn: 148918
 2012-01-25 04:19:22 +00:00
Akira Hatanaka
175341c860 Modify MipsFrameLowering::emitPrologue and emitEpilogue. 
- Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit.
- Change the types of variables so that they are sufficiently large to handle
  64-bit pointers.
- Emit instructions to set register $28 in a function prologue after
  instructions which store callee-saved registers have been emitted. 
 

llvm-svn: 148917
 2012-01-25 04:12:04 +00:00
Akira Hatanaka
9a829c1762 Modify MipsRegisterInfo::eliminateFrameIndex to use MipsAnalyzeImmediate to 
expand offsets that do not fit in the 16-bit immediate field of load and store
instructions. Also change the types of variables so that they are sufficiently
large to handle 64-bit pointers.

llvm-svn: 148916
 2012-01-25 03:55:10 +00:00
Craig Topper
f4166abe42 Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction definitions. Matches non-AVX version of same instructions. 
llvm-svn: 148914
 2012-01-25 03:52:09 +00:00
NAKAMURA Takumi
9c48741bbe MipsAnalyzeImmediate.h: Fix to add DataTypes.h for msvc. 
inttypes.h is not supplied in msvc.

llvm-svn: 148912
 2012-01-25 03:34:41 +00:00
NAKAMURA Takumi
77cf8a4b29 Target/Mips: Unbreak CMake build. 
llvm-svn: 148909
 2012-01-25 03:15:46 +00:00
Akira Hatanaka
6880302ac2 Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added. 
Add a test case to show fewer instructions are needed to load an immediate
with the new way of loading immediates.

llvm-svn: 148908
 2012-01-25 03:01:35 +00:00
Akira Hatanaka
f8475c3fa9 Add class MipsAnalyzeImmediate which comes up with an instruction sequence to 
load an immediate. 

llvm-svn: 148900
 2012-01-25 01:43:36 +00:00
Jim Grosbach
e8095f3b49 NEON VLD4(all lanes) assembly parsing and encoding. 
llvm-svn: 148884
 2012-01-25 00:01:08 +00:00
Jim Grosbach
9c21d45c29 Tidy up. Rename VLD4DUP patterns for consistency. 
llvm-svn: 148883
 2012-01-24 23:47:07 +00:00
Jim Grosbach
f478b2a706 NEON VLD3(all lanes) assembly parsing and encoding. 
llvm-svn: 148882
 2012-01-24 23:47:04 +00:00
Akira Hatanaka
0d04fc2918 Sign-extend 32-bit integer arguments when they are passed in 64-bit registers, 
which is what N32/64 does.

llvm-svn: 148875
 2012-01-24 23:18:43 +00:00
Akira Hatanaka
00e3847fc8 Pass CCState by reference. 
llvm-svn: 148871
 2012-01-24 22:07:36 +00:00
Akira Hatanaka
12cdcf3bc6 Pattern for f32 to i64 conversion. 
llvm-svn: 148869
 2012-01-24 22:05:25 +00:00
Devang Patel
0da753c9e6 Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax. 
llvm-svn: 148864
 2012-01-24 21:43:36 +00:00
Akira Hatanaka
7b1d08124d 64-bit sign extension in register instructions. 
llvm-svn: 148862
 2012-01-24 21:41:09 +00:00
Jim Grosbach
e151b15949 NEON VST4(one lane) assembly parsing and encoding. 
llvm-svn: 148836
 2012-01-24 18:53:13 +00:00
Owen Anderson
7492e4ff85 Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand. 
llvm-svn: 148833
 2012-01-24 18:37:29 +00:00
Jim Grosbach
a78348fcda NEON VLD4(one lane) assembly parsing and encoding. 
llvm-svn: 148832
 2012-01-24 18:37:25 +00:00
Jim Grosbach
f3607eac5d NEON Two-operand assembly aliases for VSRA. 
llvm-svn: 148821
 2012-01-24 17:55:36 +00:00
Jim Grosbach
630dd380c7 NEON Two-operand assembly aliases for VSLI. 
llvm-svn: 148819
 2012-01-24 17:49:15 +00:00
Jim Grosbach
42c0f99aa0 NEON Two-operand assembly aliases for VSRI. 
llvm-svn: 148818
 2012-01-24 17:46:58 +00:00
Jim Grosbach
e00b69bf5b NEON add correct predicates for some asm aliases. 
llvm-svn: 148815
 2012-01-24 17:23:29 +00:00
Chris Lattner
c67dced045 C++, CBE, and TLOF support for ConstantDataSequential 
llvm-svn: 148805
 2012-01-24 14:17:05 +00:00
Elena Demikhovsky
ee8c87b433 ZERO_EXTEND operation is optimized for AVX. 
v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions.

llvm-svn: 148803
 2012-01-24 13:54:13 +00:00
Anton Korobeynikov
16e0f2bde3 Use correct register class for am2offset register operands. 
This pacifies machine verifier

llvm-svn: 148782
 2012-01-24 04:58:56 +00:00
Craig Topper
7311a89449 Add comments near load pattern fragments indicating that all integer vector loads are promoted to v2i64 or v4i64 so that no one tries to reintroduce pattern fragments for other types. 
llvm-svn: 148771
 2012-01-24 03:03:17 +00:00
Jim Grosbach
3be662b372 NEON VST4(multiple 4 element structures) assembly parsing. 
llvm-svn: 148764
 2012-01-24 00:58:13 +00:00
Jim Grosbach
ca32a49eb5 NEON VLD4(multiple 4 element structures) assembly parsing. 
llvm-svn: 148762
 2012-01-24 00:43:17 +00:00
Jim Grosbach
345c1df4df Tidy up. Remove some vertical space for readability. 
llvm-svn: 148761
 2012-01-24 00:43:12 +00:00
Chandler Carruth
55876621c9 Revert r148686 (and r148694, a fix to it) due to a serious layering 
violation -- MC cannot depend on CodeGen.

Specifically, the MCTargetDesc component of each target is actually
a subcomponent of the MC library. As such, it cannot depend on the
target-independent code generator, because MC itself cannot depend on
the target-independent code generator. This change moved a flag from the
ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in
ARMException.cpp, leaving behind an 'extern' to refer back to it. That
layering order isn't viable givin the constraints outlined above.
Commandline flags are designed to be static specifically to avoid these
types of bugs.

Fixing this is likely going to require some non-trivial refactoring.

llvm-svn: 148759
 2012-01-24 00:30:17 +00:00
Jim Grosbach
522c9aefea Fix typo. 
llvm-svn: 148757
 2012-01-24 00:12:39 +00:00
Jim Grosbach
a4687dcf5a NEON VST3(single element from one lane) assembly parsing. 
llvm-svn: 148755
 2012-01-24 00:07:41 +00:00
Devang Patel
48ee4a8277 Fix typo. 
llvm-svn: 148751
 2012-01-23 23:56:33 +00:00
Jim Grosbach
048162ddf9 NEON VST3(multiple 3-element structures) assembly parsing. 
llvm-svn: 148748
 2012-01-23 23:45:44 +00:00
Jim Grosbach
8035fac461 NEON VLD3(multiple 3-element structures) assembly parsing. 
llvm-svn: 148745
 2012-01-23 23:20:46 +00:00
Anton Korobeynikov
62624b5220 Add missed mayStore flag to STREXD / t2STREXD 
llvm-svn: 148742
 2012-01-23 22:57:52 +00:00
Devang Patel
327773a25b Intel syntax: Robustify parsing of memory operand's displacement experssion. 
llvm-svn: 148737
 2012-01-23 22:35:25 +00:00
Jim Grosbach
dd667a11d3 NEON VLD3 lane-indexed assembly parsing and encoding. 
llvm-svn: 148734
 2012-01-23 21:53:26 +00:00
Devang Patel
3c6289f43a Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI] 
llvm-svn: 148721
 2012-01-23 20:20:06 +00:00
Jim Grosbach
0eeacbfe2e Simplify some NEON assembly pseudo definitions. 
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.

llvm-svn: 148718
 2012-01-23 19:39:08 +00:00
Devang Patel
9698de5bf3 Intel syntax: Parse segment registers. 
llvm-svn: 148712
 2012-01-23 18:31:58 +00:00
NAKAMURA Takumi
7a14d1dab9 ARMAsmPrinter.cpp: Try to fix up r148686. EnableARMEHABI was also here. 
llvm-svn: 148694
 2012-01-23 09:14:42 +00:00
Craig Topper
606872615f Custom lower PCMPEQ/PCMPGT intrinsics to target specific nodes and remove the intrinsic patterns. 
llvm-svn: 148687
 2012-01-23 08:18:28 +00:00
Evgeniy Stepanov
bffa428d01 An option to selectively enable parts of ARM EHABI support. 
This change adds an new value to the --arm-enable-ehabi option that
disables emitting unwinding descriptors. This mode gives a working
backtrace() without the (currently broken) exception support.

llvm-svn: 148686
 2012-01-23 07:57:39 +00:00
Craig Topper
9a78ce373d Update more places to use target specific nodes for vector shifts instead of intrinsics. 
llvm-svn: 148685
 2012-01-23 06:46:22 +00:00
Craig Topper
360c9f28cf Custom lower vector shift intrinsics to target specific nodes and remove the patterns that are no longer needed. 
llvm-svn: 148684
 2012-01-23 06:16:53 +00:00
Craig Topper
03b49e88a2 Remove pattern fragments for v32i8, v16i16, v8i32, v16i8, v8i16, and v4i32 loads. All integer vector loads are promoted to v2i64 or v4i64 so these pattern fragments can never match. Fix or remove patterns that used these fragments. 
llvm-svn: 148672
 2012-01-23 00:06:44 +00:00
Craig Topper
b80bb890b6 Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching. 
llvm-svn: 148670
 2012-01-22 23:36:02 +00:00
Craig Topper
558395cb4e Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching. 
llvm-svn: 148667
 2012-01-22 22:42:16 +00:00
Nicolas Geoffray
dedf43387d Use Attributes::None instead of 0 after r148553 change on Attributes from unsigned to their own class. 
llvm-svn: 148665
 2012-01-22 20:05:26 +00:00
Craig Topper
2b6951f7c4 Add target specific ISD node types for SSE/AVX vector shuffle instructions and change all the code that used to create intrinsic nodes to create the new nodes instead. 
llvm-svn: 148664
 2012-01-22 19:15:14 +00:00
Anton Korobeynikov
76b0745f6c Add fused multiple+add instructions from VFPv4. 
Patch by Ana Pazos!

llvm-svn: 148658
 2012-01-22 12:07:33 +00:00
Craig Topper
5e9b6de71f Make code a little less verbose. 
llvm-svn: 148651
 2012-01-22 03:07:48 +00:00
Craig Topper
eaca0c20ea Remove unused X86 ISD node type defines. 
llvm-svn: 148644
 2012-01-22 01:15:56 +00:00
Craig Topper
bb07c0da2d Move some vector shift patterns into their instruction definitions. 
llvm-svn: 148643
 2012-01-22 00:41:20 +00:00
Craig Topper
63c59673a3 Add memory patterns for some of the fp<->integer conversion instructions. Fold some patterns into instruction definitions. 
llvm-svn: 148641
 2012-01-21 18:37:15 +00:00
Benjamin Kramer
bdd152e9cf Remove unused variables. 
llvm-svn: 148635
 2012-01-21 10:42:44 +00:00
Craig Topper
d493ca92c4 Fix PR11819 introduced by r148537. I'd commit the test case, but the generated code is terrible as it gets fully scalarized. Expect a future commit to fix that. 
llvm-svn: 148632
 2012-01-21 08:49:33 +00:00
Jim Grosbach
5100c10a17 Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction. 
llvm-svn: 148601
 2012-01-21 00:07:56 +00:00
Devang Patel
0ecda3fc14 Intel syntax: Robustify register parsing. 
llvm-svn: 148591
 2012-01-20 22:32:05 +00:00
David Blaikie
06ecc99a56 More dead code removal (using -Wunreachable-code) 
llvm-svn: 148578
 2012-01-20 21:51:11 +00:00
Devang Patel
0638a44a24 Intel syntax: Parse ... PTR [-8] 
llvm-svn: 148570
 2012-01-20 21:21:01 +00:00
Devang Patel
e836c95860 Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax. 
llvm-svn: 148569
 2012-01-20 21:14:06 +00:00
Bob Wilson
793fa215cb ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651> 
We have patterns for vector sext and zext operations but were missing
anyext.  Without those patterns, codegen will fail when the selection DAG
has any_extend nodes.

llvm-svn: 148568
 2012-01-20 20:59:56 +00:00
Jim Grosbach
b6e177bd4e VST2 four-register w/ update pseudos for fixed/register update. 
rdar://10724489

llvm-svn: 148560
 2012-01-20 19:16:00 +00:00
Jim Grosbach
4579f05f36 NEON use vmov.i32 to splat some f32 values into vectors. 
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.

rdar://10616677

llvm-svn: 148556
 2012-01-20 18:09:51 +00:00
Benjamin Kramer
fe9eb0e6e8 Remove a bunch of unused variable assignments. 
Found by the clang static analyzer.

llvm-svn: 148541
 2012-01-20 14:42:32 +00:00
Craig Topper
7b50829b7f Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. As long as only a single lane of the source is used in the lane in the destination. This makes the splitting match much closer to what happens with 256-bit shuffles when AVX is disabled and only 128-bit XMM is allowed. 
llvm-svn: 148537
 2012-01-20 09:29:03 +00:00
Craig Topper
e2d3f3060d Add support for selecting 256-bit PALIGNR. 
llvm-svn: 148532
 2012-01-20 05:53:00 +00:00
Eli Friedman
ffa3b8b5f1 Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff. 
llvm-svn: 148513
 2012-01-20 00:05:46 +00:00
Benjamin Kramer
b3479ef519 Silence warnings about mixing enums. 
llvm-svn: 148495
 2012-01-19 21:11:13 +00:00
Devang Patel
b42cea31aa Post process 'and', 'sub' instructions and select better encoding, if available. 
llvm-svn: 148489
 2012-01-19 18:40:55 +00:00
Devang Patel
27ef211648 Intel syntax: There is no need to create unary expr for simple negative displacement. 
llvm-svn: 148486
 2012-01-19 18:15:51 +00:00
Devang Patel
999eaa4b85 Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available. 
llvm-svn: 148485
 2012-01-19 17:53:25 +00:00
Evgeniy Stepanov
f329e9ee4d Emit ARM EHABI unwinding instructions for 3 more Thumb instructions. 
llvm-svn: 148473
 2012-01-19 12:53:06 +00:00
Craig Topper
cee7bd6b73 Folding table additions and fixes for AVX. 
llvm-svn: 148467
 2012-01-19 08:50:38 +00:00
Craig Topper
3d928aa51b Merge 128-bit and 256-bit SHUFPS/SHUFPD handling. 
llvm-svn: 148466
 2012-01-19 08:19:12 +00:00
Jim Grosbach
8a63389253 ARM assembly diagnostic caret in better position for FPImm. 
llvm-svn: 148459
 2012-01-19 02:47:30 +00:00
Jim Grosbach
87e683580c Thumb2 relaxation for tADR to t2ADR. 
llvm-svn: 148456
 2012-01-19 02:09:38 +00:00
Jim Grosbach
ad42e2fc2a Add comment and fix range check in condition. 
llvm-svn: 148455
 2012-01-19 01:50:30 +00:00
Evan Cheng
86ca08f633 - Slight change to finalizeBundle() interface. LastMI is not exclusive (pointing 
to instruction right after the last instruction in the bundle.
- Add a finalizeBundle() variant that doesn't specify LastMI. Instead, the code
  will find the last instruction in the bundle by following the 'InsideBundle'
  marker. This is useful in case bundles are formed early (i.e. during MI
  scheduling) but finalized later (i.e. after register allocator has finished
  rewriting virtual registers with physical registers).

llvm-svn: 148444
 2012-01-19 00:46:06 +00:00
Nick Lewycky
c1e7e2eaf6 Add a TargetOption for disabling tail calls. 
llvm-svn: 148442
 2012-01-19 00:34:10 +00:00
Evan Cheng
cfc7639cc7 Rename Finalizebundle to finalizeBundle to conform to coding guideline. 
llvm-svn: 148440
 2012-01-19 00:06:10 +00:00
Jakob Stoklund Olesen
498e016c87 Add experimental -x86-use-regmask command line option. 
It adds register mask operands to x86 call instructions.  Once all the
backend passes support register mask operands, this will be permanently
enabled.

llvm-svn: 148438
 2012-01-18 23:52:22 +00:00
Jakob Stoklund Olesen
85ef53eb8d Ignore register mask operands when lowering instructions to MC. 
This is similar to implicit register operands.  MC doesn't understand
register liveness and call clobbers.

llvm-svn: 148437
 2012-01-18 23:52:19 +00:00
Jim Grosbach
b7ab9edb4e Thumb2 alternate syntax for LDR(literal) and friends. 
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".

rdar://10250964

llvm-svn: 148432
 2012-01-18 22:46:46 +00:00
Devang Patel
ee49d825b1 Process instructions after match to select alternative encoding which may be more desirable. 
llvm-svn: 148431
 2012-01-18 22:42:29 +00:00