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Commit Graph

3309 Commits

Author SHA1 Message Date
Kalle Raiskila
392de86bb5 Fix SPU to cope with vector insertelement to an undef position.
We default to inserting to lane 0.

llvm-svn: 105722
2010-06-09 09:58:17 +00:00
Kalle Raiskila
b547a95a7b Handle loading from/storing to undef pointers on SPU by inserting a
random load/store, rather than crashing llc.

llvm-svn: 105710
2010-06-09 08:29:41 +00:00
Dan Gohman
1865db1b89 LSR needs to remember inserted instructions even in postinc mode, because
there could be multiple subexpressions within a single expansion which
require insert point adjustment. This fixes PR7306.

llvm-svn: 105510
2010-06-05 00:33:07 +00:00
Evan Cheng
0fb8a935a5 Re-apply 105308 with fix.
llvm-svn: 105502
2010-06-04 23:28:13 +00:00
Dale Johannesen
fc3c949f68 More tail call removal.
llvm-svn: 105485
2010-06-04 21:14:24 +00:00
Dan Gohman
332b06bd4f Fix normalization and de-normalization of non-affine SCEVs.
llvm-svn: 105480
2010-06-04 19:16:34 +00:00
Mon P Wang
f83cdf3d18 Fixed a bug during widening where we would avoid legalizing a node. When we
replace an OpA with a widened OpB, it is possible to get new uses of OpA due to CSE
when recursively updating nodes.  Since OpA has been processed, the new uses are
not examined again.  The patch checks if this occurred and it it did, updates the
new uses of OpA to use OpB.

llvm-svn: 105453
2010-06-04 01:20:10 +00:00
Dale Johannesen
f03ef32e4e Remove more tail calls.
llvm-svn: 105450
2010-06-04 01:01:24 +00:00
Dale Johannesen
0c967c579f Remove a tail call, and move some CHECKs to the
functions where they belong.

llvm-svn: 105449
2010-06-04 01:01:04 +00:00
Dan Gohman
bbd309edaa This test doesn't need the ssp attribute.
llvm-svn: 105440
2010-06-04 00:14:48 +00:00
Dale Johannesen
3492389308 Remove tail call. A tail call version will follow.
llvm-svn: 105438
2010-06-04 00:03:37 +00:00
Dale Johannesen
f80ca136ca Remove tail call to preserve this test. A tail
call version will follow.

llvm-svn: 105422
2010-06-03 21:57:48 +00:00
Dale Johannesen
f49af36017 Make this test not use tail calls. A tail call
version will follow.

llvm-svn: 105419
2010-06-03 21:53:01 +00:00
Dan Gohman
ab8153cf58 Fix SimplifyDemandedBits' AssertZext logic to demand all the bits. It
needs to demand the high bits because it's asserting that they're zero.

llvm-svn: 105406
2010-06-03 20:21:33 +00:00
Bob Wilson
15a21b6b97 Revert 105308.
llvm-svn: 105399
2010-06-03 18:28:31 +00:00
Bill Wendling
077afde4bf Machine sink could potentially sink instructions into a block where the physical
registers it defines then interfere with an existing preg live range.

For instance, if we had something like these machine instructions:

BB#0
  ... = imul ... EFLAGS<imp-def,dead>
  test ..., EFLAGS<imp-def>
  jcc BB#2 EFLAGS<imp-use>

BB#1
  ... ; fallthrough to BB#2

BB#2
  ... ; No code that defines EFLAGS
  jcc ... EFLAGS<imp-use>

Machine sink will come along, see that imul implicitly defines EFLAGS, but
because it's "dead", it assumes that it can move imul into BB#2. But when it
does, imul's "dead" imp-def of EFLAGS is raised from the dead (a zombie) and
messes up the condition code for the jump (and pretty much anything else which
relies upon it being correct).

The solution is to know which pregs are live going into a basic block. However,
that information isn't calculated at this point. Nor does the LiveVariables pass
take into account non-allocatable physical registers. In lieu of this, we do a
*very* conservative pass through the basic block to determine if a preg is live
coming out of it.

llvm-svn: 105387
2010-06-03 07:54:20 +00:00
Eric Christopher
00f399e90a One underscore, not two.
llvm-svn: 105379
2010-06-03 04:02:59 +00:00
Eli Friedman
60c8122bb0 Implement expansion in type legalization for add/sub with overflow. The
expansion is the same as that used by LegalizeDAG.

The resulting code sucks in terms of performance/codesize on x86-32 for a
64-bit operation; I haven't looked into whether different expansions might be
better in general.

llvm-svn: 105378
2010-06-03 03:49:50 +00:00
Evan Cheng
b137439a0a Enable machine cse of instructions which define physical registers.
llvm-svn: 105308
2010-06-02 01:08:27 +00:00
Dan Gohman
3a3a65dadc Fill in missing support for ISD::FEXP, ISD::FPOWI, and friends.
llvm-svn: 105283
2010-06-01 18:35:14 +00:00
Kalle Raiskila
ed7364d3e1 Fix handling of 'load' nodes.
llvm-svn: 105269
2010-06-01 13:34:47 +00:00
Chris Lattner
14bf35ae45 fix PR6623: when optimizing for size, don't inline memcpy/memsets
that are too large.  This causes the freebsd bootloader to be too
large apparently.

It's unclear if this should be an -Os or -Oz thing.  Thoughts welcome.

llvm-svn: 105228
2010-05-31 17:30:14 +00:00
Chris Lattner
e8b65c0352 upgrade and filecheckize this test.
llvm-svn: 105227
2010-05-31 17:27:17 +00:00
Evan Cheng
fd971f18cb Remove schedule-livein-copies. It's not being used.
llvm-svn: 105095
2010-05-29 02:23:39 +00:00
Evan Cheng
96bdf3e6f1 Fix PR7193: if sibling call address can take a register, make sure there are enough registers available by counting inreg arguments.
llvm-svn: 105092
2010-05-29 01:35:22 +00:00
Evan Cheng
849bca1ab6 Fix some latency computation bugs: if the use is not a machine opcode do not just return zero.
llvm-svn: 105061
2010-05-28 23:26:21 +00:00
Jakob Stoklund Olesen
f58cd7c838 Fix more tests that depended on the default register allocator choice.
llvm-svn: 104961
2010-05-28 17:06:30 +00:00
Dan Gohman
bcee12027f Eliminate the restriction that the array size in an alloca must be i32.
This will help reduce the amount of casting required on 64-bit targets.

llvm-svn: 104911
2010-05-28 01:14:11 +00:00
Jakob Stoklund Olesen
d76041cf58 Add a -regalloc=default option that chooses a register allocator based on the -O
optimization level.

This only really affects llc for now because both the llvm-gcc and clang front
ends override the default register allocator. I intend to remove that code later.

llvm-svn: 104904
2010-05-27 23:57:25 +00:00
Evan Cheng
68be5ab54e llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.
llvm-svn: 104891
2010-05-27 22:08:38 +00:00
Devang Patel
bdda547db4 Simplify. Eliminate unneeded debug_loc entry.
llvm-svn: 104785
2010-05-26 23:55:23 +00:00
Devang Patel
2ea3f77515 Update debug info when live-in reg is copied into a vreg.
llvm-svn: 104732
2010-05-26 20:18:50 +00:00
Dale Johannesen
81afa3569a Testcase for 104624/104619/PR7191/8023512.
Reduced from one provided by Duncan Sands, thanks!

llvm-svn: 104710
2010-05-26 17:55:45 +00:00
Dale Johannesen
9d2f1f2b16 Removing test; Chris thinks it's better to have the
bug go untested than have a testcase this large.  So be it.

llvm-svn: 104632
2010-05-25 20:40:10 +00:00
Dale Johannesen
8fd73c1910 Fix another variant of PR 7191. Also add a testcase
Mon Ping provided; unfortunately bugpoint failed to
reduce it, but I think it's important to have a test for
this in the suite.  8023512.

llvm-svn: 104624
2010-05-25 18:47:23 +00:00
Bob Wilson
c71b7c8c61 Thumb2 RSBS instructions were being printed without the 'S' suffix.
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.

llvm-svn: 104531
2010-05-24 18:44:06 +00:00
Evan Cheng
9b011e343c LR is in GPR, not tGPR even in Thumb1 mode.
llvm-svn: 104518
2010-05-24 18:00:18 +00:00
Evan Cheng
241d2c434e Implement @llvm.returnaddress. rdar://8015977.
llvm-svn: 104421
2010-05-22 01:47:14 +00:00
Eric Christopher
189eca1291 This test is darwin only. Make it so(tm).
llvm-svn: 104418
2010-05-22 00:55:55 +00:00
Bob Wilson
b8ebb375b6 Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
copying VFP subregs.  This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.

llvm-svn: 104415
2010-05-22 00:23:12 +00:00
Eric Christopher
165bcdf8a8 Add full bss data support for darwin tls variables.
llvm-svn: 104414
2010-05-22 00:10:22 +00:00
Bob Wilson
586811b244 Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements
so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.

llvm-svn: 104380
2010-05-21 21:05:32 +00:00
Chris Lattner
4c14d2c4a4 now that fp reg kill insertion stuff happens as a separate
pass after isel instead of being interlaced with it, we can
trust that all the code for a function has been isel'd before
it is run.

The practical impact of this is that we can scan for machine
instr phis instead of doing a fuzzy match on the LLVM BB for
phi nodes.  Doing the fuzzy match required knowing when isel
would produce an fp reg stack phi which was gross.  It was
also wrong in cases where select got lowered to a branch
tree because cmovs aren't available (PR6828).

Just do the scan on machine phis which is simpler, faster
and more correct.  This fixes PR6828.

llvm-svn: 104333
2010-05-21 18:17:54 +00:00
Jakob Stoklund Olesen
924b84cf0f Teach VirtRegRewriter to handle spilling in instructions that have multiple
definitions of the virtual register.

This happens when spilling the registers produced by REG_SEQUENCE:

%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0

The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.

llvm-svn: 104321
2010-05-21 16:36:13 +00:00
Dale Johannesen
d0a5fdb32f Fix i64->f64 conversion, x86-64, -no-sse. A bit
tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.

llvm-svn: 104308
2010-05-21 00:52:33 +00:00
Evan Cheng
6397a77e16 Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
llvm-svn: 104307
2010-05-21 00:43:17 +00:00
Dan Gohman
89f64e13fe When canonicalizing icmp operand order to put the loop invariant
operand on the left, the interesting operand is on the right. This
fixes a bug where LSR was failing to recognize ICmpZero uses,
which led it to be unable to reverse the induction variable in the
attached testcase.

Delete test/CodeGen/X86/stack-color-with-reg-2.ll, because its test
is extremely fragile and hard to meaningfully update.

llvm-svn: 104262
2010-05-20 19:26:52 +00:00
Bob Wilson
11aebf39f1 Handle Neon v2f64 and v2i64 vector shuffles as register copies.
This fixes the remaining issue with pr7167.

llvm-svn: 104257
2010-05-20 18:39:53 +00:00
Dan Gohman
772b731ca5 Teach LSR how to cope better with unrolled loops on targets where
the addressing modes don't make this trivially easy. This allows
it to avoid falling into the less precise heuristics in more
cases.

llvm-svn: 104186
2010-05-19 23:43:12 +00:00
Jakob Stoklund Olesen
6a2bfde3c8 TwoAddressInstructionPass doesn't really know how to merge live intervals when
lowering REG_SEQUENCE instructions.

Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes.

llvm-svn: 104146
2010-05-19 20:08:00 +00:00
Bob Wilson
e5f623ac22 Testcase to go with 104141.
llvm-svn: 104142
2010-05-19 18:58:37 +00:00
Evan Cheng
6f52107b12 t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
llvm-svn: 104115
2010-05-19 07:28:01 +00:00
Evan Cheng
632cb17357 Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.
The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.

Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.

llvm-svn: 104094
2010-05-19 01:08:17 +00:00
Jakob Stoklund Olesen
f3114dbb3a Remember to update VirtRegLastUse when spilling without killing before a call.
llvm-svn: 104074
2010-05-18 22:20:09 +00:00
Dan Gohman
eaa3ee65bd When converting a test to a cmp to fold a load, use the cmp that has an
8-bit immediate field rather than one with a wider immediate field.

llvm-svn: 104064
2010-05-18 21:42:03 +00:00
Evan Cheng
e2980af336 Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
llvm-svn: 104060
2010-05-18 21:31:17 +00:00
Evan Cheng
9fc34e676d Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE.
llvm-svn: 104050
2010-05-18 20:03:28 +00:00
Daniel Dunbar
8c20c162fe MC/X86: Implement custom lowering to make sure we match things like
X86::ADC32ri $0, %eax
to
  X86::ADC32i32 $0

llvm-svn: 104030
2010-05-18 17:22:24 +00:00
Evan Cheng
39b5115e93 FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)).
llvm-svn: 104004
2010-05-18 00:03:40 +00:00
Evan Cheng
8aa900cf16 Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG_SEQUENCE instructions.
llvm-svn: 103994
2010-05-17 23:24:12 +00:00
Evan Cheng
378d6c5d76 Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace it with an IMPLICIT_DEF rather than deleting it or else it would be left without a def.
llvm-svn: 103984
2010-05-17 22:09:49 +00:00
Evan Cheng
bb0a4fbe13 Careful with reg_sequence coalescing to not to overwrite sub-register indices.
llvm-svn: 103971
2010-05-17 20:57:12 +00:00
Evan Cheng
3bce87c79f Turn on -neon-reg-sequence by default.
Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!

llvm-svn: 103960
2010-05-17 19:51:20 +00:00
Jakob Stoklund Olesen
c07fd51d56 Avoid allocating the same physreg to multiple virtregs in one instruction.
While that approach works wonders for register pressure, it tends to break
everything.

This should unbreak the arm-linux builder and fix a number of miscompilations.

llvm-svn: 103946
2010-05-17 17:18:59 +00:00
Jakob Stoklund Olesen
40545bf117 Only use clairvoyance when defining a register, and then only if it has one use.
This makes allocation independent on the ordering of use-def chains.

llvm-svn: 103935
2010-05-17 04:50:57 +00:00
Dale Johannesen
b71d6a4150 Removing as part of previous reversion.
llvm-svn: 103915
2010-05-16 20:19:40 +00:00
Dale Johannesen
cf2d4b9f91 Revert 103911; it broke a test that expects bitconvert
<1xi64> -> i64 to work in MMX registers on hosts where -no-sse
is the default (not mine).  The right thing is
to accept this and make i64->f64 conversions go through memory,
but I don't have time right now.

llvm-svn: 103914
2010-05-16 20:19:04 +00:00
Dale Johannesen
15dce10b5a Make x86-64 64-bit bitconvert work when SSE is not available.
(This worked as of about 6 months ago and I didn't track down
exactly what broke it; I think this fix is appropriate.)

llvm-svn: 103911
2010-05-16 18:22:38 +00:00
Anton Korobeynikov
925a32ae37 Add support for thiscall calling convention.
Patch by Charles Davis and Steven Watanabe!

llvm-svn: 103902
2010-05-16 09:08:45 +00:00
Anton Korobeynikov
314ccc5501 Some cheap DAG combine goodness for multiplication with a particular constant.
This can be extended later on to handle more "complex" constants.

llvm-svn: 103881
2010-05-15 18:16:59 +00:00
Evan Cheng
85497bd415 Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.

llvm-svn: 103854
2010-05-15 02:18:07 +00:00
Bill Wendling
5fde821884 SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead and
replace the check with the appropriate predicate. Modify the testcase to reflect
the correct code. (It should be saving callee-saved registers on the stack
allocated by the calling fuction.)

llvm-svn: 103829
2010-05-14 22:17:42 +00:00
Jakob Stoklund Olesen
3eac02b22f Simplify the handling of physreg defs and uses in RegAllocFast.
This adds extra security against using clobbered physregs, and it adds kill
markers to physreg uses.

llvm-svn: 103784
2010-05-14 18:03:25 +00:00
Jakob Stoklund Olesen
d99818256c Take allocation hints from copy instructions to/from physregs.
This causes way more identity copies to be generated, ripe for coalescing.

llvm-svn: 103686
2010-05-13 00:19:43 +00:00
Jakob Stoklund Olesen
7d1323d9a5 Make sure to add kill flags to the last use of a virtreg when it is redefined.
The X86 floating point stack pass and others depend on good kill flags.

llvm-svn: 103635
2010-05-12 18:46:03 +00:00
Jakob Stoklund Olesen
6976c543cd Enable a bunch more -regalloc=fast tests
llvm-svn: 103531
2010-05-12 00:11:24 +00:00
Jakob Stoklund Olesen
063844f706 Keep track of the last place a live virtreg was used.
This allows us to add accurate kill markers, something the scavenger likes.
Add some more tests from ARM that needed this.

llvm-svn: 103521
2010-05-11 23:24:45 +00:00
Jakob Stoklund Olesen
99d5d74fb0 One more -regalloc=fast test
llvm-svn: 103509
2010-05-11 20:51:07 +00:00
Jakob Stoklund Olesen
e27902ac68 Simplify the tracking of used physregs to a bulk bitor followed by a transitive
closure after allocating all blocks.

Add a few more test cases for -regalloc=fast.

llvm-svn: 103500
2010-05-11 20:30:28 +00:00
Jakob Stoklund Olesen
442e38c4de Mostly rewrite RegAllocFast.
Sorry for the big change. The path leading up to this patch had some TableGen
changes that I didn't want to commit before I knew they were useful. They
weren't, and this version does not need them.

The fast register allocator now does no liveness calculations. Instead it relies
on kill flags provided by isel. (Currently those kill flags are also ignored due
to isel bugs). The allocation algorithm is supposed to work with any subset of
valid kill flags. More kill flags simply means fewer spills inserted.

Registers are allocated from a working set that contains no aliases. That means
most allocations can be done directly without expensive alias checks. When the
working set runs out of registers we do the full alias check to find new free
registers.

llvm-svn: 103488
2010-05-11 18:54:45 +00:00
Kalle Raiskila
e302300b51 Make SPU backend not assert on jump tables.
llvm-svn: 103466
2010-05-11 11:00:02 +00:00
Evan Cheng
11130a0a22 Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.
llvm-svn: 103459
2010-05-11 07:26:32 +00:00
Evan Cheng
df350445c6 Be careful with operand promotion. For a binary operation, the source operands may be the same. PR7018. rdar://7939869.
llvm-svn: 103419
2010-05-10 19:03:57 +00:00
Kalle Raiskila
61289abcda Fix encoding of 'sf' and 'sfh' instructions.
llvm-svn: 103399
2010-05-10 08:13:49 +00:00
Bill Wendling
787de8fe38 Readd testcase.
llvm-svn: 103335
2010-05-08 04:47:54 +00:00
Dan Gohman
4ca74b9c6c When pruning candidate formulae out of an LSRUse, update the
LSRUse's Regs set after all pruning is done, rather than trying
to do it on the fly, which can produce an incomplete result.

This fixes a case where heuristic pruning was stripping all
formulae from a use, which led the solver to enter an infinite
loop.

Also, add a few asserts to diagnose this kind of situation.

llvm-svn: 103328
2010-05-07 23:36:59 +00:00
Bill Wendling
4241941b52 Remove. Don't XFAIL.
llvm-svn: 103321
2010-05-07 23:09:17 +00:00
Bill Wendling
3846ec7889 Temorarily revert r101984.
llvm-svn: 103314
2010-05-07 22:45:36 +00:00
Dan Gohman
95040c18f4 SDDbgValues are apparently not being legalized. Fix a symptom of the problem,
and not the real problem itself, by dropping debug info for i128 values.
rdar://7958162.

llvm-svn: 103310
2010-05-07 22:19:08 +00:00
Dale Johannesen
1ee37ac5d4 Fix PR 7087, and probably other things, by extending
getConstantFP to accept the two supported long double
target types.  This was not the original intent, but
there are other places that assume this works and it's
easy enough to do.

llvm-svn: 103299
2010-05-07 21:35:53 +00:00
Jim Grosbach
2db1618b44 Clean up the conditional for handling of sign_extend_inreg based on
whether the extract instructions are available.

rdar://7956878

llvm-svn: 103277
2010-05-07 18:34:55 +00:00
Duncan Sands
ed2ef5a987 Correct some bogus target triples.
llvm-svn: 103265
2010-05-07 17:03:48 +00:00
Nick Lewycky
3e5720a898 Revert r103133 and add testcase from PR7066.
llvm-svn: 103233
2010-05-07 01:45:38 +00:00
Dan Gohman
f863ad3dc5 Disable the new unknown-location code for now. It causes a major
increase in the debug line info section, and it's causing
regressions in a gdb testsuite.

llvm-svn: 103226
2010-05-07 01:08:53 +00:00
Dan Gohman
497e752655 Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.

llvm-svn: 103194
2010-05-06 20:33:48 +00:00
Dan Gohman
3190e5c292 Add a testcase for r103135, explicitly representing unknown
locations in debug line info.

llvm-svn: 103189
2010-05-06 17:49:17 +00:00
Chris Lattner
014a954e3d Fix PR7054 - Assertion `Symbol->isUndefined() && "Cannot define a symbol twice!"' failed.
Users can write broken code that emits the same label twice with asm renaming,
detect this and emit a fatal backend error instead of aborting.

llvm-svn: 103140
2010-05-06 00:05:37 +00:00
Jim Grosbach
e04cc6cb43 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
instructions to subtarget features and update tests to reflect.
PR5717.

llvm-svn: 103136
2010-05-05 23:44:43 +00:00
Jakob Stoklund Olesen
2e5d12acfa Fix PR6520. An earlyclobber physreg must not be allocated to anything else.
llvm-svn: 103133
2010-05-05 23:07:41 +00:00
Jim Grosbach
7eb0b4d646 fix copy/paste oops.
llvm-svn: 103122
2010-05-05 21:07:46 +00:00