Evan Cheng
aa16fd02ad
Do not model all INLINEASM instructions as having unmodelled side effects.
...
Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check
the operand when the instruction is an INLINEASM.
This allows memory instructions to be moved around INLINEASM instructions.
llvm-svn: 123044
2011-01-07 23:50:32 +00:00
Bob Wilson
eb4521fbcb
Add an explanatory message for an assertion.
...
llvm-svn: 123042
2011-01-07 23:40:46 +00:00
Matt Beaumont-Gay
68a61cf6dd
Eliminate variable only used in debug builds.
...
llvm-svn: 123040
2011-01-07 22:34:58 +00:00
Bob Wilson
c485ff3ced
Lower some BUILD_VECTORS using VEXT+shuffle.
...
Patch by Tim Northover.
llvm-svn: 123035
2011-01-07 21:37:30 +00:00
Bob Wilson
22f18a7e94
Add ARM patterns to match EXTRACT_SUBVECTOR nodes.
...
Also fix an off-by-one in SelectionDAGBuilder that was preventing shuffle
vectors from being translated to EXTRACT_SUBVECTOR.
Patch by Tim Northover.
The test changes are needed to keep those spill-q tests from testing aligned
spills and restores. If the only aligned stack objects are spill slots, we
no longer realign the stack frame. Prior to this patch, an EXTRACT_SUBVECTOR
was legalized by loading from the stack, which created an aligned frame index.
Now, however, there is nothing except the spill slot in the stack frame, so
I added an aligned alloca.
llvm-svn: 122995
2011-01-07 04:59:04 +00:00
Bob Wilson
461eb28678
PR8921: LDM/POP do not support interworking prior to v5t.
...
llvm-svn: 122970
2011-01-06 19:24:41 +00:00
Bob Wilson
f4a821c3d3
Remove extra whitespace.
...
llvm-svn: 122969
2011-01-06 19:24:36 +00:00
Bob Wilson
42b8976610
Fix comment typo.
...
llvm-svn: 122968
2011-01-06 19:24:32 +00:00
Evan Cheng
cb39cc2164
Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpy
...
etc. takes an option OptSize. If OptSize is true, it would return
the inline limit for functions with attribute OptSize.
llvm-svn: 122952
2011-01-06 06:52:41 +00:00
Chris Lattner
d419fe1dfe
fix some -Wself-assign warnings.
...
llvm-svn: 122893
2011-01-05 18:41:05 +00:00
Andrew Trick
3637733170
Fix the ARM IIC_iCMPsi itinerary and add an important assert.
...
llvm-svn: 122794
2011-01-04 00:32:57 +00:00
Bill Wendling
b402d3881e
Formatting changes. No functionality change.
...
llvm-svn: 122789
2011-01-03 23:59:05 +00:00
Anton Korobeynikov
d37cb4cd1c
Model operand restrictions of mul-like instructions on ARMv5 via
...
earlyclobber stuff. This should fix PRs 2313 and 8157.
Unfortunately, no testcase, since it'd be dependent on register
assignments.
llvm-svn: 122663
2011-01-01 20:38:38 +00:00
NAKAMURA Takumi
2160b3953b
CMake: Add disabling optimization on MSVC8 and MSVC10 as workaround for some files in Target/ARM and Target/X86.
...
llvm-svn: 122623
2010-12-29 03:59:27 +00:00
Andrew Trick
134b2a5907
Various bits of framework needed for precise machine-level selection
...
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
2010-12-24 05:03:26 +00:00
Andrew Trick
53f4556c64
whitespace
...
llvm-svn: 122539
2010-12-24 04:28:06 +00:00
Jim Grosbach
7fc4f99084
Use a StringSwitch<> instead of a manually constructed string matcher.
...
llvm-svn: 122530
2010-12-24 00:03:39 +00:00
Jim Grosbach
03a39130cb
Remove dead patterns.
...
llvm-svn: 122524
2010-12-23 23:20:13 +00:00
Jim Grosbach
14f46d80df
Recognize a few more documented register name aliases for ARM in the asm lexer.
...
llvm-svn: 122523
2010-12-23 23:19:54 +00:00
Bob Wilson
85dbc89f44
Radar 8803471: Fix expansion of ARM BCCi64 pseudo instructions.
...
If the basic block containing the BCCi64 (or BCCZi64) instruction ends with
an unconditional branch, that branch needs to be deleted before appending
the expansion of the BCCi64 to the end of the block.
llvm-svn: 122521
2010-12-23 22:45:49 +00:00
Chris Lattner
01e8c46349
Flag -> Glue, the ongoing saga
...
llvm-svn: 122513
2010-12-23 18:28:41 +00:00
Jim Grosbach
b0e9926c33
Trailing whitespace.
...
llvm-svn: 122456
2010-12-22 23:26:02 +00:00
Bob Wilson
01593c55a2
Add ARM-specific DAG combining to cast i64 vector element load/stores to f64.
...
Type legalization splits up i64 values into pairs of i32 values, which leads
to poor quality code when inserting or extracting i64 vector elements.
If the vector element is loaded or stored, it can be treated as an f64 value
and loaded or stored directly from a VPR register. Use the pre-legalization
DAG combiner to cast those vector elements to f64 types so that the type
legalizer won't mess them up. Radar 8755338.
llvm-svn: 122319
2010-12-21 06:43:19 +00:00
Eric Christopher
72ceef0a74
Arm and thumb call instructions are also in different orders.
...
Fixes rdar://8782223
llvm-svn: 122313
2010-12-21 03:50:43 +00:00
Chris Lattner
65c5243bd6
rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
...
something that just glues two nodes together, even if it is
sometimes used for flags.
llvm-svn: 122310
2010-12-21 02:38:05 +00:00
Eric Christopher
81ae56b33c
If we're not using reg+reg offset we're using reg+imm, set the opcode
...
to be the one we want to use. bugpoint reduced testcase is a little large,
I'll see if I can simplify it down more.
Fixes part of rdar://8782207
llvm-svn: 122307
2010-12-21 02:12:07 +00:00
Bill Wendling
856080c8a1
Fix a copy-pasto. When the tBR_JTr instruction was converted to using the
...
tPseudoInst class, its size was changed from "special" to "2 bytes". This is
incorrect because the jump table will no longer be taken into account when
calculating branch offsets.
<rdar://problem/8782216>
llvm-svn: 122303
2010-12-21 01:57:15 +00:00
Bill Wendling
8c7f90099b
Comment cleanups.
...
llvm-svn: 122302
2010-12-21 01:54:40 +00:00
Rafael Espindola
7f9be9e112
Remove the MCObjectFormat class.
...
llvm-svn: 122147
2010-12-18 05:37:28 +00:00
Rafael Espindola
9a4bfd7755
Move some data to the TargetWriter.
...
llvm-svn: 122134
2010-12-18 03:27:34 +00:00
Bill Wendling
9b2ef1c9be
r120333 changed the opcode for the Thumb1 stuff from ARM::tMOVr to
...
ARM::tMOVgpr2gpr. But this check didn't change. As a result, we were getting
misaligned references to the jump table from an ADR instruction.
There is a test case, but unfortunately it's sensitive to random code changes.
<rdar://problem/8782223>
llvm-svn: 122131
2010-12-18 02:13:59 +00:00
Bill Wendling
2dde4e38c9
RemoveUnusedCPEntries can change things. Track it.
...
llvm-svn: 122129
2010-12-18 01:53:06 +00:00
Bob Wilson
5f9e78fe20
Rearrange some Neon multiclasses. No functional changes.
...
llvm-svn: 122119
2010-12-18 00:42:58 +00:00
Bob Wilson
776d3f73eb
Fix result type of Neon floating-point comparisons against zero.
...
The result vector elements are always integers. Radar 8782191.
llvm-svn: 122112
2010-12-18 00:04:33 +00:00
Bob Wilson
c000db3584
Add some missing entries in ARMTargetLowering::getTargetNodeName.
...
llvm-svn: 122111
2010-12-18 00:04:26 +00:00
Bill Wendling
c16f9b1ccc
During local stack slot allocation, the materializeFrameBaseRegister function
...
may be called. If the entry block is empty, the insertion point iterator will be
the "end()" value. Calling ->getParent() on it (among others) causes problems.
Modify materializeFrameBaseRegister to take the machine basic block and insert
the frame base register at the beginning of that block. (It's very similar to
what the code does all ready. The only difference is that it will always insert
at the beginning of the entry block instead of after a previous materialization
of the frame base register. I doubt that that matters here.)
<rdar://problem/8782198>
llvm-svn: 122104
2010-12-17 23:09:14 +00:00
Bob Wilson
12f2b81599
Avoid report_fatal_error in ARM's PrintAsmOperand method.
...
The standard error handling in AsmPrinter::EmitInlineAsm handles this much
better, so just use it.
llvm-svn: 122100
2010-12-17 23:06:42 +00:00
Jim Grosbach
7ca8ed3d5d
If The ARM WriteNopData() gets an unaligned byte count to pad out, fill in with
...
a partial value. rdar://8782954
llvm-svn: 122078
2010-12-17 19:03:02 +00:00
Jim Grosbach
9017f2d179
Add bits 31-28 to the Thumb2 encoding of TBB/TBH.
...
llvm-svn: 122076
2010-12-17 18:42:56 +00:00
Jim Grosbach
e0f65aaf8d
Handle 2 and 4 byte data blob fixup values for ARM.
...
llvm-svn: 122075
2010-12-17 18:39:10 +00:00
Rafael Espindola
b9ca29bc1c
Stub out explicit MCELFObjectTargetWriter interface.
...
llvm-svn: 122067
2010-12-17 17:45:22 +00:00
Rafael Espindola
38e6fdfd1d
Move createELFObjectWriter to its own header.
...
llvm-svn: 122064
2010-12-17 16:59:53 +00:00
Daniel Dunbar
eea7fd1c3e
MC/ARM: Use aggressive symbol folding (important for jump tables, for example).
...
llvm-svn: 122044
2010-12-17 06:00:24 +00:00
Daniel Dunbar
6d4a3e98f3
MC/Target: Remove HasScatteredSymbols target hook variable, which has been
...
superceded and was effectively dead.
llvm-svn: 122024
2010-12-17 02:06:08 +00:00
Bob Wilson
125f1a26e0
Use PairDRegs to implement ConcatVectors. No functionality change.
...
llvm-svn: 122017
2010-12-17 01:21:08 +00:00
Jim Grosbach
ce773319e4
Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974
...
llvm-svn: 121990
2010-12-16 19:11:16 +00:00
Daniel Dunbar
2277f06687
MC/Mach-O: Lift some MachObjectWriter arguments into the target specific
...
interface.
llvm-svn: 121981
2010-12-16 17:21:02 +00:00
Daniel Dunbar
5fee4f6862
MC/Mach-O: Stub out explicit MCMachObjectTargetWriter interface.
...
llvm-svn: 121973
2010-12-16 16:09:19 +00:00
Daniel Dunbar
636e690f58
MC/Mach-O: Move createMachObjectWriter into MCMachObjectWriter.h.
...
llvm-svn: 121971
2010-12-16 16:08:33 +00:00
Daniel Dunbar
fc14f1e5f6
MC: Move target specific fixup info descriptors to TargetAsmBackend instead of
...
the MCCodeEmitter, which seems like a better organization.
- Also, cleaned up some magic constants while in the area.
llvm-svn: 121953
2010-12-16 03:20:06 +00:00
Matt Beaumont-Gay
9b5939da47
Delete an extra "Imm5 = ", caught by GCC's -Wsequence-point but not by Clang
...
(see PR4579).
llvm-svn: 121939
2010-12-16 01:34:26 +00:00
Bill Wendling
c22ad4d7ae
Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff for
...
it. I.e., it was always an immediate value.
llvm-svn: 121932
2010-12-16 00:50:33 +00:00
Bill Wendling
6ce0807502
Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRi
...
respectively.
It may be a bug that these opcodes are getting this far into machine code
generation.
llvm-svn: 121931
2010-12-16 00:49:54 +00:00
Bill Wendling
448cd7f1bb
Add encodings for Thumb1 Spill and Restore pseudos.
...
llvm-svn: 121929
2010-12-16 00:38:41 +00:00
Jim Grosbach
84c2b29b58
Thumb1 had two patterns for the same load-from-constant-pool instruction.
...
Canonicalize on tLDRpci and remove tLDRcp.
llvm-svn: 121920
2010-12-15 23:52:36 +00:00
Eric Christopher
339499f8f3
Don't handle -arm-long-calls in fast isel for now.
...
llvm-svn: 121919
2010-12-15 23:47:29 +00:00
Bill Wendling
63ebdf4786
If we're changing the frame register to a physical register other than SP, we
...
need to use tLDRi and tSTRi instead of tLDRspi and tSTRspi respectively.
llvm-svn: 121915
2010-12-15 23:32:27 +00:00
Bill Wendling
ed6c88ead9
Whitespace cleanups.
...
llvm-svn: 121914
2010-12-15 23:31:24 +00:00
Bob Wilson
438a9a1367
Add Neon VCVT instructions for f32 <-> f16 conversions.
...
Clang is now providing intrinsics for these and so we need to support them
in the backend. Radar 8068427.
llvm-svn: 121902
2010-12-15 22:14:12 +00:00
Jim Grosbach
30e7f0d09e
Tweak a few pseudo-inst pattern base classes.
...
llvm-svn: 121878
2010-12-15 19:03:16 +00:00
Jim Grosbach
8278d5692a
The new t2LEApcrel* pseudo instructions need the size specified.
...
rdar://8768390
llvm-svn: 121876
2010-12-15 18:48:45 +00:00
Owen Anderson
202d654195
Implement cleanups suggested by Daniel.
...
llvm-svn: 121875
2010-12-15 18:48:27 +00:00
Bill Wendling
ab9df10ee5
Add fixups for Thumb LDR/STR instructions.
...
llvm-svn: 121858
2010-12-15 08:51:02 +00:00
Bill Wendling
258739db7e
Reapply r121808 now that the missing patterns have been supplied.
...
llvm-svn: 121820
2010-12-15 01:03:19 +00:00
Bill Wendling
2764f25c78
Add some missing patterns now that tLDRB and tLDRH are split into reg and
...
immediate versions.
llvm-svn: 121819
2010-12-15 00:58:57 +00:00
Bill Wendling
ad13b53237
Revert r121808 until I can fix the build.
...
llvm-svn: 121815
2010-12-15 00:04:00 +00:00
Jim Grosbach
386d8fc22c
thumb adr fixup needs alignment just like the t2 version.
...
llvm-svn: 121812
2010-12-14 23:47:35 +00:00
Bill Wendling
ab3d22ba7f
Comments and cleaning.
...
llvm-svn: 121809
2010-12-14 23:42:48 +00:00
Bill Wendling
2883bbb8c0
Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. In
...
particular, we want
ldr r2, [r3]
to be equivalent to
ldr r2, [r3, #0 ]
and not
ldr r2, [r3, r0]
llvm-svn: 121808
2010-12-14 23:40:49 +00:00
Jim Grosbach
1e943cc60d
Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
...
llvm-svn: 121798
2010-12-14 22:28:03 +00:00
Bill Wendling
213a3d080d
Fix comment.
...
llvm-svn: 121797
2010-12-14 22:26:49 +00:00
Bill Wendling
7e589d4753
Multiclassify the LDR/STR encoding patterns. The only functionality difference
...
is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.
llvm-svn: 121794
2010-12-14 22:10:49 +00:00
Jim Grosbach
70721628b4
trailing whitespace
...
llvm-svn: 121792
2010-12-14 21:28:29 +00:00
Jim Grosbach
e84e95e6d2
Refactor a bit for legibility.
...
llvm-svn: 121790
2010-12-14 21:10:47 +00:00
Jim Grosbach
ef58d5968e
trailing whitespace.
...
llvm-svn: 121789
2010-12-14 20:46:39 +00:00
Jim Grosbach
13d82ea2b1
Make sure to propagate the predicate operands for LEApcrel to ADR.
...
llvm-svn: 121788
2010-12-14 20:45:47 +00:00
Owen Anderson
4ce4ce2f60
Fix a small bug (typo?) in the fixup for Thumb1 CBZ/CBNZ instructions.
...
llvm-svn: 121784
2010-12-14 19:42:53 +00:00
Daniel Dunbar
3f9b9dc852
MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup.
...
llvm-svn: 121772
2010-12-14 17:37:16 +00:00
Jim Grosbach
88727a93a8
Trailing whitespace
...
llvm-svn: 121769
2010-12-14 16:25:15 +00:00
Bill Wendling
4fe39bae17
Use the integer scheduling intrinsic for integer loads and stores.
...
llvm-svn: 121765
2010-12-14 12:33:05 +00:00
Bill Wendling
61720b79f9
The tLDR et al instructions were emitting either a reg/reg or reg/imm
...
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
llvm-svn: 121747
2010-12-14 03:36:38 +00:00
Evan Cheng
6a2bed92f5
bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663
...
llvm-svn: 121746
2010-12-14 03:22:07 +00:00
Owen Anderson
c84f8c23b3
Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire
...
process cleaner.
llvm-svn: 121735
2010-12-14 00:36:49 +00:00
Bob Wilson
33e5e902b0
Remove the rest of the *_sfp Neon instruction patterns.
...
Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now. It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior. Since that isn't obviously wrong, I've just
changed the test file. This completes the work for Radar 8711675.
llvm-svn: 121730
2010-12-13 23:02:37 +00:00
Bob Wilson
b189b77d9b
Simplify N2VSPat, removing some unnecessary type arguments.
...
llvm-svn: 121729
2010-12-13 23:02:31 +00:00
Owen Anderson
af1dde2673
Revert r121721, which broke buildbots.
...
llvm-svn: 121726
2010-12-13 22:51:08 +00:00
Owen Anderson
c298c8ed4d
Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provide correct fixups for Thumb2 ADR,
...
which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.
llvm-svn: 121721
2010-12-13 22:29:52 +00:00
Bob Wilson
203303291f
Delete a line that I forgot to revert previously.
...
llvm-svn: 121719
2010-12-13 22:05:55 +00:00
Bob Wilson
074095ddf2
Use COPY_TO_REGCLASS instead of pseudo instructions for Neon FP patterns.
...
Jakob Olesen suggested that we can avoid the need for separate pseudo
instructions here by using COPY_TO_REGCLASS in the patterns. The pattern
gets pretty ugly but it seems to work well. Partial fix for Radar 8711675.
llvm-svn: 121718
2010-12-13 21:58:05 +00:00
Bob Wilson
56b41f8b81
Use pseudo instructions for 2-register Neon instructions for scalar FP.
...
Partial fix for Radar 8711675.
llvm-svn: 121716
2010-12-13 21:05:52 +00:00
Bob Wilson
9a6d75a499
Remove unused instruction class arguments.
...
llvm-svn: 121715
2010-12-13 21:05:44 +00:00
Evan Cheng
c90b20fb74
Generalize BFI isel lowering a bit.
...
llvm-svn: 121714
2010-12-13 20:32:54 +00:00
Owen Anderson
4ec912b842
In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or
...
as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.
llvm-svn: 121710
2010-12-13 19:31:11 +00:00
Jim Grosbach
9a282f2202
Use 32-bit types for 32-bit values.
...
llvm-svn: 121709
2010-12-13 19:25:46 +00:00
Jim Grosbach
ad058bd082
Trailing whitespace.
...
llvm-svn: 121708
2010-12-13 19:18:13 +00:00
Evan Cheng
b6773d7e1f
(or (and (shl A, #shamt), mask), B) => ARMbfi B, A, ~mask where lsb(mask) == #shamt. rdar://8752056
...
llvm-svn: 121606
2010-12-11 04:11:38 +00:00
Jim Grosbach
98dcdf10c2
Add FIXME
...
llvm-svn: 121598
2010-12-10 23:41:10 +00:00
Owen Anderson
47a78db79b
Attempt to get Thumb2 branch fixups working properly.
...
llvm-svn: 121593
2010-12-10 23:02:28 +00:00
Owen Anderson
8424ab65e2
Fix merge error in my last fix to Thumb2 vldr fixups.
...
llvm-svn: 121588
2010-12-10 22:53:48 +00:00
Owen Anderson
f310c92333
Fixups for Thumb2 vldr's need to have the effective PC aligned as well.
...
llvm-svn: 121587
2010-12-10 22:46:47 +00:00
Bill Wendling
7f1cea7009
The MCFixupKindInfo table needs to be in the order that the enums were
...
declared. Add a note specifying this and spruce up the list a bit.
llvm-svn: 121586
2010-12-10 22:37:19 +00:00
Owen Anderson
e85fabac75
Provide the necessary post-encoder hook for Thumb2 encodings of VMOV and friends.
...
llvm-svn: 121585
2010-12-10 22:32:08 +00:00
Bob Wilson
d30768fe3e
Add float patterns for Neon vld1-lane/dup and vst1-lane operations.
...
llvm-svn: 121583
2010-12-10 22:13:32 +00:00
Bob Wilson
ae683e722f
Remove unused arguments.
...
llvm-svn: 121582
2010-12-10 22:13:24 +00:00
Owen Anderson
aaf97da84b
Fix encoding of Thumb1 LDRB and STRB.
...
llvm-svn: 121581
2010-12-10 22:11:13 +00:00
Jim Grosbach
d7f424dec3
Trailing whitespace.
...
llvm-svn: 121580
2010-12-10 21:57:34 +00:00
Owen Anderson
44ad90c850
Fix Thumb2 encodings of STREX and LDREX.
...
llvm-svn: 121579
2010-12-10 21:52:38 +00:00
Jim Grosbach
82dd80c956
Correct encoding of rotation immediate for Thumb2 instructions. rdar://8755999
...
llvm-svn: 121525
2010-12-10 21:24:18 +00:00
Jim Grosbach
63853d61e1
Fix encoding of 'U' bit for Thumb2 STRD/LDRD instructions. rdar://8755726
...
llvm-svn: 121524
2010-12-10 21:05:07 +00:00
Jim Grosbach
467e860805
More trivial cleanup. No need to define the EncoderMethod property type. Can
...
just assign to it.
llvm-svn: 121523
2010-12-10 20:53:44 +00:00
Jim Grosbach
5696d964ca
Tidy up.
...
llvm-svn: 121522
2010-12-10 20:51:35 +00:00
Jim Grosbach
401391235f
Trailing whitespace.
...
llvm-svn: 121521
2010-12-10 20:47:29 +00:00
Bob Wilson
5ff13f9d5c
Fix some invalid alignments for Neon vld-dup and vld/st-lane instructions.
...
Alignments smaller than the total size of the memory being loaded or stored,
unless the alignment is 8 bytes, are not allowed. Add tests for this, too.
llvm-svn: 121506
2010-12-10 19:37:42 +00:00
Jim Grosbach
4a414e1973
Teach isCSRestore() that ARM/Thumb2 functions will use post-modify LDR
...
instructions to restore a single register rather than an LDM instruction.
rdar://8754999
llvm-svn: 121498
2010-12-10 18:41:15 +00:00
Jim Grosbach
a378c43eae
Thumb unconditional branch binary encoding. rdar://8754994
...
llvm-svn: 121496
2010-12-10 18:21:33 +00:00
Jim Grosbach
905301a7d8
Thumb conditional branch binary encodings. rdar://8745367
...
llvm-svn: 121493
2010-12-10 17:13:40 +00:00
Kevin Enderby
a2efb1ad4e
Fix the leak from r121401 of the Operands erased in the list but not deleted.
...
llvm-svn: 121450
2010-12-10 01:41:56 +00:00
Bill Wendling
f8eaf8a243
Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of the
...
t_addrmode_s# address modes is used for ASM printing, not for encoding.
<rdar://problem/8745375>
llvm-svn: 121417
2010-12-09 21:49:07 +00:00
Owen Anderson
4be3b6db5c
Use the new IsAligned fixup flag to improve fixup encodings for Thumb2 branches. This is still not perfect,
...
but it gets many more of them correct than it did previously.
llvm-svn: 121414
2010-12-09 21:34:47 +00:00
Owen Anderson
a8ac35b468
Fix an issue in some Thumb fixups, where the effective PC address needs to be 4-byte aligned when calculating
...
the offset. Add a new fixup flag to represent this, and use it for the one fixups that I have a testcase for needing
this. It's quite likely that the other Thumb fixups will need this too, and to have their fixup encoding logic
adjusted accordingly.
llvm-svn: 121408
2010-12-09 20:27:52 +00:00
Jim Grosbach
61fe7b9ee5
Rename CB/CBZ specific fixup accordingly.
...
llvm-svn: 121404
2010-12-09 19:50:12 +00:00
Kevin Enderby
55cb19813e
Add support for parsing ARM arithmetic instructions that update or don't update
...
the condition codes. Where the ones that do have an 's' suffix and the ones
that don't don't have the suffix. The trick is if MatchInstructionImpl() fails
we try again after adding a CCOut operand with the correct value and removing
the 's' if present. Four simple test cases added for now, lots more to come.
llvm-svn: 121401
2010-12-09 19:19:43 +00:00
Jim Grosbach
9b3730fc77
Rename the encoder method for t_cbtarget to match.
...
llvm-svn: 121399
2010-12-09 19:04:53 +00:00
Jim Grosbach
57d420438a
Thumb needs a few different encoding schemes for branch targets. Rename
...
t_brtarget to be more specific.
llvm-svn: 121398
2010-12-09 19:01:46 +00:00
Jim Grosbach
8bc33cc6e5
ARM stm/ldm instructions require more than one register in the register list.
...
Otherwise, a plain str/ldr should be used instead. Make sure we account for
that in prologue/epilogue code generation.
rdar://8745460
llvm-svn: 121391
2010-12-09 18:31:13 +00:00
Jim Grosbach
4ad6abd006
tidy up.
...
llvm-svn: 121371
2010-12-09 16:15:41 +00:00
Jim Grosbach
9adf657f1a
80 columns.
...
llvm-svn: 121370
2010-12-09 16:14:46 +00:00
Owen Anderson
96545f21b9
Fix encoding of the immediate operands on post-indexed LDR and friends.
...
llvm-svn: 121354
2010-12-09 02:56:12 +00:00
Eric Christopher
ea350b4c4b
Fix up some comments.
...
llvm-svn: 121351
2010-12-09 01:57:45 +00:00
Owen Anderson
767a95816d
Fix Thumb2 fixups for ldr.
...
llvm-svn: 121350
2010-12-09 01:51:07 +00:00
Jim Grosbach
5658d982b4
Add a textual message to the assert.
...
llvm-svn: 121349
2010-12-09 01:23:51 +00:00
Jim Grosbach
da9353523f
Add a sanity check assert() for t2ADD/SUBrSPi instructions that they really are
...
referencing the stack pointer as they say they are.
llvm-svn: 121347
2010-12-09 01:22:19 +00:00
Jim Grosbach
fb71e10e93
When using multiple instructions to reference a frame index, make sure to
...
update the opcode when necessary as well as the source register.
llvm-svn: 121346
2010-12-09 01:22:13 +00:00
Jim Grosbach
e38a2a39c6
The add/sub SP instructions are really pseudos. The assembler should ignore
...
them.
llvm-svn: 121345
2010-12-09 01:21:27 +00:00
Matt Beaumont-Gay
a8aa446938
Remove unused variables
...
llvm-svn: 121343
2010-12-09 01:04:43 +00:00
Owen Anderson
43177d405a
Fix typo in Thumb2 branch fixup.
...
llvm-svn: 121342
2010-12-09 01:02:09 +00:00
Bill Wendling
baf852a1d6
Remove extraneous semicolon.
...
llvm-svn: 121338
2010-12-09 00:51:54 +00:00
Bill Wendling
9205cc6ea8
Attempt to make the bit-twiddling readable resulted in the binary value being
...
overwritten.
llvm-svn: 121337
2010-12-09 00:44:33 +00:00
Bill Wendling
cd8fdfd65f
The BLX instruction is encoded differently than the BL, because why not? In
...
particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.
Attempt to get the encoding at slightly more correct with this.
llvm-svn: 121336
2010-12-09 00:39:08 +00:00
Owen Anderson
b956593730
Fix Thumb2 BCC encoding and fixups.
...
llvm-svn: 121329
2010-12-09 00:27:41 +00:00
Jason W Kim
e270068021
Style nit and whitespace cleanup
...
llvm-svn: 121317
2010-12-08 23:35:25 +00:00
Jim Grosbach
5a00173ead
Clean up the add/sub w/ SP source reg instructions in Thumb2 a bit. Add a FIXME
...
for more thorough cleanup.
llvm-svn: 121315
2010-12-08 23:30:19 +00:00
Jim Grosbach
2eda2e0be9
Fix T2TwoRegImm and use it for t2ADDrSPi12 and friends.
...
llvm-svn: 121314
2010-12-08 23:24:29 +00:00
Jason W Kim
e8047d9ec4
Removed dead comment.
...
llvm-svn: 121313
2010-12-08 23:19:44 +00:00
Jason W Kim
2e6e50c1b0
ARM/MC/ELF TPsoft is now a proper pseudo inst.
...
Added test to check bl __aeabi_read_tp gets emitted properly for ELF/ASM
as well as ELF/OBJ (including fixup)
Also added support for ELF::R_ARM_TLS_IE32
llvm-svn: 121312
2010-12-08 23:14:44 +00:00
Jim Grosbach
7a9e43e642
T2TwoRegImm isn't right for t2SUBrSPi12. Use T2I instead.
...
llvm-svn: 121311
2010-12-08 23:13:01 +00:00
Jim Grosbach
4f11f0f871
Add operand encoding for Thumb2 subw SP + imm. rdar://8745434
...
llvm-svn: 121310
2010-12-08 23:12:09 +00:00
Jim Grosbach
a423fbc4c7
Add operand encoding for Thumb2 addw Rn + imm. rdar://8745434
...
llvm-svn: 121309
2010-12-08 23:04:16 +00:00
Bill Wendling
9756f7c7b0
Support the "target" encodings for the CB[N]Z instructions.
...
llvm-svn: 121308
2010-12-08 23:01:43 +00:00
Evan Cheng
9fcb62eed1
Fix an obvious cut-n-paste error.
...
llvm-svn: 121307
2010-12-08 23:01:18 +00:00
Jim Grosbach
51082ed2a4
Add operand encoding for Thumb2 addw SP + imm. rdar://8745434
...
llvm-svn: 121305
2010-12-08 22:50:19 +00:00
Jim Grosbach
e1eb84a44a
Parameterize opcode encoding bits for Thumb2 extended precision integer
...
multiply instructions.
llvm-svn: 121301
2010-12-08 22:38:41 +00:00
Jim Grosbach
13c16125f1
Fix operand encoding for Thumb2 extended precision multiplies. rdar://8745555
...
llvm-svn: 121297
2010-12-08 22:29:28 +00:00
Jim Grosbach
063c38c6df
Simplify T2 operand assignment notation a bit. No need to specify a bit range
...
for the source field when it's the whole thing that's being referenced.
llvm-svn: 121291
2010-12-08 22:10:43 +00:00
Jim Grosbach
5e900612ff
Tweak ARM fixup value adjustments for Thumb to better handle the half-word
...
ordering of thumb mode.
llvm-svn: 121280
2010-12-08 20:32:07 +00:00
Andrew Trick
fb72ca2129
Generalize PostRAHazardRecognizer so it can be used in any pass for
...
both forward and backward scheduling. Rename it to
ScoreboardHazardRecognizer (Scoreboard is one word). Remove integer
division from the scoreboard's critical path.
llvm-svn: 121274
2010-12-08 20:04:29 +00:00
Owen Anderson
d5c17d5981
Improve comment.
...
llvm-svn: 121272
2010-12-08 19:31:11 +00:00
Jim Grosbach
16cdaf34bc
Add initializer.
...
llvm-svn: 121262
2010-12-08 15:36:45 +00:00
Evan Cheng
5582f058f4
Add comments.
...
llvm-svn: 121238
2010-12-08 06:29:02 +00:00
Bill Wendling
dac1f24d98
Add support for loading from a constant pool.
...
llvm-svn: 121226
2010-12-08 01:57:09 +00:00
Jim Grosbach
d4eea7c10d
Let target asm backends see assembler flags as they go by. Use that to handle
...
thumb vs. arm mode differences in WriteNopData().
llvm-svn: 121219
2010-12-08 01:16:55 +00:00
Owen Anderson
d00dc39a11
Simplify the byte reordering logic slightly.
...
llvm-svn: 121216
2010-12-08 00:21:33 +00:00
Owen Anderson
ba5edcfe05
VLDR fixups need special handling under Thumb. While the encoding is the same,
...
the order of the bytes in the data stream is flipped around.
llvm-svn: 121215
2010-12-08 00:18:36 +00:00
Matt Beaumont-Gay
5e680ad101
Fix a warning about a variable which is only used in an assertion.
...
llvm-svn: 121206
2010-12-07 23:26:21 +00:00
Bill Wendling
45bdb13970
Cleanup in the Darwin end. No functionality change.
...
llvm-svn: 121198
2010-12-07 23:11:00 +00:00
Evan Cheng
3bd9b95b4d
Fix a bad prologue / epilogue codegen bug where the compiler would emit illegal
...
vpush instructions to save / restore VFP / NEON registers like this:
vpush {d8,d10,d11}
vpop {d8,d10,d11}
vpush and vpop do not allow gaps in the register list.
rdar://8728956
llvm-svn: 121197
2010-12-07 23:08:38 +00:00
Bill Wendling
4399d09458
A bit of cleanup: early exit ApplyFixup and cache the Fixup offset. No
...
functionality change.
llvm-svn: 121195
2010-12-07 23:05:20 +00:00
Jim Grosbach
77b631549c
Binary encoding for ARM tLDRspi and tSTRspi.
...
llvm-svn: 121186
2010-12-07 21:50:47 +00:00
Owen Anderson
a23e10f29d
Fix Thumb2 encoding of the S bit.
...
llvm-svn: 121182
2010-12-07 20:50:15 +00:00
Jim Grosbach
1aa6a676cf
Refactor the ARM CMPz* patterns to just use the normal CMP instructions when
...
possible. They were duplicates for everything exception the source pattern
before.
llvm-svn: 121179
2010-12-07 20:41:06 +00:00
Evan Cheng
9af09ebf8b
Code clean up; no functionality change.
...
llvm-svn: 121176
2010-12-07 20:11:46 +00:00
Evan Cheng
0295c17fbc
Code clean up; no functionality change.
...
llvm-svn: 121172
2010-12-07 19:59:34 +00:00
Jim Grosbach
c99517ecc6
Encode the literal field for tCMPzi instruction.
...
llvm-svn: 121153
2010-12-07 17:48:24 +00:00
Benjamin Kramer
fb17a54866
Add parens to pacify gcc.
...
llvm-svn: 121142
2010-12-07 15:50:35 +00:00
Jay Foad
79e18ed269
PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and
...
zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method
trunc(), to be const and to return a new value instead of modifying the
object in place.
llvm-svn: 121120
2010-12-07 08:25:19 +00:00
Owen Anderson
81f8b084e6
Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it.
...
llvm-svn: 121082
2010-12-07 00:45:21 +00:00
Jim Grosbach
2d361b9318
Add fixup for Thumb1 BL/BLX instructions.
...
llvm-svn: 121072
2010-12-06 23:57:07 +00:00
Rafael Espindola
65c25aef87
Remove the instruction fragment to data fragment lowering since it was causing
...
freed data to be read. I will open a bug to track it being reenabled.
llvm-svn: 121028
2010-12-06 19:08:48 +00:00
Owen Anderson
8e9cb84ea2
Revert r121021, which broke the buildbots.
...
llvm-svn: 121026
2010-12-06 18:57:40 +00:00
Jim Grosbach
f2e0e808ba
Trailing whitespace.
...
llvm-svn: 121024
2010-12-06 18:47:44 +00:00
Owen Anderson
0c51a02230
Improve handling of Thumb2 PC-relative loads by converting LDRpci (and friends) to Pseudos.
...
llvm-svn: 121021
2010-12-06 18:35:51 +00:00
Jim Grosbach
6c27b4f3cf
Encode the register operand of ARM CondCode operands correctly. ARM::CPSR if
...
the instruction is predicated, reg0 otherwise.
llvm-svn: 121020
2010-12-06 18:30:57 +00:00
Jim Grosbach
c79c6290ee
The ARM AsmMatcher needs to know that the CCOut operand is a register value,
...
not an immediate. It stores either ARM::CPSR or reg0.
llvm-svn: 121018
2010-12-06 18:21:12 +00:00
Evan Cheng
4d9d54e44e
Eliminate unneeded #include's.
...
llvm-svn: 120971
2010-12-05 23:41:43 +00:00
NAKAMURA Takumi
594d4094ca
ARM/CMakeLists.txt: Add missing MLxExpansionPass.cpp since r120960.
...
llvm-svn: 120966
2010-12-05 23:08:57 +00:00
Evan Cheng
12561e250d
Code clean up.
...
llvm-svn: 120965
2010-12-05 23:03:45 +00:00
Evan Cheng
854ec53564
Remove an unused variable.
...
llvm-svn: 120964
2010-12-05 23:03:35 +00:00
Evan Cheng
fc78767730
Making use of VFP / NEON floating point multiply-accumulate / subtraction is
...
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.
Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.
A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.
Work in progress, only A+B are enabled.
llvm-svn: 120960
2010-12-05 22:04:16 +00:00
Bob Wilson
20c65a9d33
The Thumb tADDrSPi instruction is not valid when the destination is SP.
...
Check for that and try narrowing it to tADDspi instead. Radar 8724703.
llvm-svn: 120892
2010-12-04 04:40:19 +00:00
Jim Grosbach
4c10ffa7c3
Encode condition code for Thumb1 conditional branch instruction.
...
llvm-svn: 120865
2010-12-04 00:20:40 +00:00
Jim Grosbach
1dac8796d5
Correctly size-reduce the t2CMPzrr instruction to tCMPzr when possible.
...
tCMPzhir has undefined behavior when both source registers are low registers.
rdar://8728577
llvm-svn: 120858
2010-12-03 23:54:18 +00:00
Bill Wendling
7e27f17312
Use correct variable names to match the patterns.
...
llvm-svn: 120857
2010-12-03 23:44:24 +00:00
Jim Grosbach
3b5c857f01
Match pattern operand names to expected encoding field names. This corrects the
...
operand encoding ordering of the instruction.
llvm-svn: 120852
2010-12-03 23:21:25 +00:00
Jim Grosbach
dbefb3e7e5
Remove incorrect BL target encoding (it's similar to, but not the same as the
...
ARM instruction). Add encoding of bits 13 and 11.
llvm-svn: 120849
2010-12-03 22:33:42 +00:00
Jim Grosbach
8cef570ed9
Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order
...
halfword being emitted to the stream first. rdar://8728174
llvm-svn: 120848
2010-12-03 22:31:40 +00:00
Jim Grosbach
c69ad2176a
When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the
...
32-bit wide version by adding the .w suffix.
llvm-svn: 120838
2010-12-03 20:33:01 +00:00
Benjamin Kramer
e27eff8888
Remove unused variable.
...
llvm-svn: 120836
2010-12-03 19:55:37 +00:00
Jim Grosbach
c8ce9a3453
Reduce t2 ldr/str instructions to the correct t1 versions when there's an
...
immediate offset.
llvm-svn: 120833
2010-12-03 19:47:11 +00:00
Jason W Kim
27bbab7e31
fix ARM::fixup_arm_branch, cleanup, and share more code between ELF and Darwin
...
llvm-svn: 120832
2010-12-03 19:40:23 +00:00
Jim Grosbach
25da270139
No need to declare EncoderMethod property anymore; just assign to it.
...
llvm-svn: 120831
2010-12-03 19:31:00 +00:00