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363 Commits

Author SHA1 Message Date
Evan Cheng
30ef170ddf Use bl to call Thumb fuctions directly. 
llvm-svn: 33433
 2007-01-22 19:40:10 +00:00
Evan Cheng
6271410520 Round up stack to multiple of alignment only if it's a leaf function without alloca. 
llvm-svn: 33401
 2007-01-20 10:22:33 +00:00
Evan Cheng
5ea6a8d9e4 Prologue and epilogue bugs for non-Darwin targets. 
llvm-svn: 33390
 2007-01-20 03:24:07 +00:00
Evan Cheng
a6803554ab Clean up ARM PEI code. 
llvm-svn: 33389
 2007-01-20 02:09:25 +00:00
Evan Cheng
5d0be572b5 Code clean up. Use def : pat instead of defining new instructions. 
llvm-svn: 33368
 2007-01-19 20:27:35 +00:00
Evan Cheng
51292f4863 isDarwin -> isTargetDarwin 
llvm-svn: 33366
 2007-01-19 19:28:01 +00:00
Evan Cheng
99725bd310 Restructure code a bit to make use of continue (simplifying things). Generalize 
the .zerofill directive emission to not be darwin-specific.

llvm-svn: 33365
 2007-01-19 19:25:36 +00:00
Evan Cheng
025816f18c Darwin doesn't support .bss, but it does have .zerofill 
llvm-svn: 33364
 2007-01-19 19:23:47 +00:00
Evan Cheng
b1a4190523 Introduce TargetType's ELF and Darwin. 
llvm-svn: 33363
 2007-01-19 19:22:40 +00:00
Evan Cheng
9203bd4339 Modify emission of jump tables on darwin to emit an extra "l" label that 
delimits the boundaries of jump tables.  This lets the linker's dead code
stripping optimization do a better job.

llvm-svn: 33362
 2007-01-19 18:59:56 +00:00
Lauro Ramos Venancio
f53f62b91d Fix section definition. 
llvm-svn: 33359
 2007-01-19 17:33:22 +00:00
Evan Cheng
c6e1d453d3 ARM backend contribution from Apple. 
llvm-svn: 33353
 2007-01-19 07:51:42 +00:00
Lauro Ramos Venancio
14cf9f2c03 Don't add or sub zero to sp. 
llvm-svn: 33142
 2007-01-12 20:52:27 +00:00
Lauro Ramos Venancio
97e120a71c Build constants using instructions mov/orr or mvn/eor. 
llvm-svn: 33141
 2007-01-12 20:35:49 +00:00
Lauro Ramos Venancio
078b85bdaa Expand SELECT (f32/f64) and FCOPYSIGN (f32/f64). 
llvm-svn: 32870
 2007-01-04 14:01:38 +00:00
Evan Cheng
bd6a333b52 Fix naming inconsistency. 
llvm-svn: 32823
 2007-01-02 21:33:40 +00:00
Rafael Espindola
d1baea3471 implement missing compares 
patch by Lauro
bug fixed by me

llvm-svn: 32795
 2006-12-31 18:52:39 +00:00
Reid Spencer
dda168599d For PR950: 
Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
   type of an function parameter was used to determine whether it should
   be sign extended or zero extended before the call. This information is
   now communicated via the function type's parameter attributes.
3. The interface to LowerCallTo had to be changed in order to accommodate
   the parameter attribute information. Although it would have been
   convenient to pass in the FunctionType itself, there isn't always one
   present in the caller. Consequently, a signedness indication for the
   result type and for each parameter was provided for in the interface
   to this method. All implementations were changed to make the adjustment
   necessary.

llvm-svn: 32788
 2006-12-31 05:55:36 +00:00
Rafael Espindola
16af307d42 fix comment 
llvm-svn: 32767
 2006-12-29 14:28:12 +00:00
Lauro Ramos Venancio
c87ce8ee4b Define StaticCtorsSection and StaticDtorsSection for ARM. 
llvm-svn: 32763
 2006-12-28 13:13:00 +00:00
Lauro Ramos Venancio
7bfe536783 Implement SELECT_CC (f32/f64) for ARM. 
llvm-svn: 32762
 2006-12-28 13:11:14 +00:00
Rafael Espindola
da5b9584ce remove duplicated line 
bug noticed by Lauro

llvm-svn: 32761
 2006-12-28 12:51:40 +00:00
Lauro Ramos Venancio
2cde823f98 This patch defines extloadi1 and fixes an internal compiler error on 
arm.

llvm-svn: 32760
 2006-12-26 19:30:42 +00:00
Chris Lattner
fd16bf61d8 Fix for ARM weak symbols, patch by Lauro Ramos Venancio! 
llvm-svn: 32740
 2006-12-21 22:59:58 +00:00
Chris Lattner
8896b6cb46 eliminate static ctors for Statistic objects. 
llvm-svn: 32703
 2006-12-19 22:59:26 +00:00
Rafael Espindola
05b3447706 macros -> Inline functions 
Lauros's patch

llvm-svn: 32656
 2006-12-18 11:07:09 +00:00
Rafael Espindola
08c0825f18 move ExtWeakSymbols to AsmPrinter 
llvm-svn: 32648
 2006-12-18 03:37:18 +00:00
Rafael Espindola
d19ea53887 avoid using a constant table when a constant can be used inline 
llvm-svn: 32580
 2006-12-14 18:58:37 +00:00
Rafael Espindola
0d92ae76fb Avoid creating invalid sub/add instructions on the prolog/epilog 
patch by Lauro

llvm-svn: 32577
 2006-12-14 13:31:27 +00:00
Rafael Espindola
7c4245c4e3 more general matching of the MVN instruction 
llvm-svn: 32484
 2006-12-12 17:10:13 +00:00
Rafael Espindola
a65fd68f23 don't use "ordinary" addressing mode 1 when mvn is appropriate 
llvm-svn: 32482
 2006-12-12 14:03:29 +00:00
Rafael Espindola
d29cb12dfc use MVN to handle small negative constants 
llvm-svn: 32459
 2006-12-12 01:03:11 +00:00
Rafael Espindola
b8163fd828 add mvn 
llvm-svn: 32454
 2006-12-12 00:37:38 +00:00
Rafael Espindola
e3aafd29a9 add note 
llvm-svn: 32452
 2006-12-11 23:56:10 +00:00
Rafael Espindola
9fe91fc84f .align is in bits 
.comm is in bytes
:-(

llvm-svn: 32408
 2006-12-10 02:53:14 +00:00
Rafael Espindola
620b3430c8 %progbits not @progbits 
llvm-svn: 32376
 2006-12-08 22:06:02 +00:00
Rafael Espindola
7e99603152 add \"aw\",@progbits" to ctors and dtors 
llvm-svn: 32373
 2006-12-08 21:24:58 +00:00
Rafael Espindola
514fcabb29 fix truncstorei1 
llvm-svn: 32364
 2006-12-08 18:41:21 +00:00
Rafael Espindola
bb753d7121 fix alignment 
llvm-svn: 32337
 2006-12-07 22:38:06 +00:00
Bill Wendling
f13d78d3b8 What should be the last unnecessary <iostream>s in the library. 
llvm-svn: 32333
 2006-12-07 22:21:48 +00:00
Rafael Espindola
a908b2dfd9 make sure that we don't use a common symbol if a section was specified 
llvm-svn: 32310
 2006-12-07 18:33:58 +00:00
Chris Lattner
a531ce882e Detemplatize the Statistic class. The only type it is instantiated with 
is 'unsigned'.

llvm-svn: 32279
 2006-12-06 17:46:33 +00:00
Rafael Espindola
7ad537568f print weak references 
llvm-svn: 32276
 2006-12-06 13:35:10 +00:00
Chris Lattner
fd152e4ed6 These asm printers shouldn't use assembly/writer.h 
llvm-svn: 32262
 2006-12-06 06:13:25 +00:00
Rafael Espindola
5e8a6ca4c0 expand memmove and memcpy 
llvm-svn: 32226
 2006-12-05 17:57:23 +00:00
Rafael Espindola
38062acebb add support for the "r" asm constraint 
patch by Lauro Ramos Venancio

llvm-svn: 32224
 2006-12-05 17:37:31 +00:00
Rafael Espindola
da1fffc4e1 add support for weak linkage 
llvm-svn: 32222
 2006-12-05 17:00:17 +00:00
Evan Cheng
98fa7ab4d7 Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 
of opcode and number of operands.

llvm-svn: 31947
 2006-11-27 23:37:22 +00:00
Rafael Espindola
5daebfdae0 implement load effective address similar to the alpha backend 
remove lea_addri and the now unused memri addressing mode

llvm-svn: 31592
 2006-11-09 13:58:55 +00:00
Evan Cheng
736a8eb3cd Match tblegen changes. 
llvm-svn: 31571
 2006-11-08 20:34:28 +00:00
Rafael Espindola
f7b898d497 initial implementation of addressing mode 2 
TODO: fix lea_addri

llvm-svn: 31552
 2006-11-08 17:07:32 +00:00
Chris Lattner
7c265ad682 remove dead/redundant vars 
llvm-svn: 31435
 2006-11-03 23:48:56 +00:00
Rafael Espindola
3459a4b85b revert previous patch 
llvm-svn: 31411
 2006-11-03 03:08:28 +00:00
Rafael Espindola
5cfe91aaca add createCFGSimplificationPass to ARMTargetMachine::addInstSelector 
llvm-svn: 31400
 2006-11-03 01:39:25 +00:00
Rafael Espindola
04afe6eb37 move ARMCondCodeToString to ARMAsmPrinter.cpp 
remove unused variables from lowerCall

llvm-svn: 31378
 2006-11-02 15:00:02 +00:00
Rafael Espindola
3ae2b33d17 print null values in bss 
llvm-svn: 31349
 2006-11-01 14:26:44 +00:00
Rafael Espindola
a52f709418 implement zextload bool and truncstore bool 
llvm-svn: 31348
 2006-11-01 14:13:27 +00:00
Rafael Espindola
ba8771a3db add support for calling functions when the caller has variable sized objects 
llvm-svn: 31312
 2006-10-31 13:03:26 +00:00
Evan Cheng
5766dd6455 All targets expand BR_JT for now. 
llvm-svn: 31294
 2006-10-30 08:02:39 +00:00
Rafael Espindola
99322ef58c initial support for frame pointers 
llvm-svn: 31197
 2006-10-26 13:31:26 +00:00
Rafael Espindola
a962656c07 expand ISD::VACOPY 
llvm-svn: 31170
 2006-10-24 20:15:21 +00:00
Rafael Espindola
2259fab5cf fix warning about missing newline at end of file 
llvm-svn: 31162
 2006-10-24 17:07:11 +00:00
Chris Lattner
71dc932fcb implement uncond branch insertion, mark branches with isBranch. 
llvm-svn: 31160
 2006-10-24 16:47:57 +00:00
Rafael Espindola
70f01d5cc0 implement STRB and STRH 
llvm-svn: 31138
 2006-10-23 20:34:27 +00:00
Rafael Espindola
357f151d9d expand ISD::MEMSET 
llvm-svn: 31137
 2006-10-23 20:08:22 +00:00
Reid Spencer
d414793dbc For PR950: 
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.

llvm-svn: 31063
 2006-10-20 07:07:24 +00:00
Rafael Espindola
c08546401b use Pat to implement extloadi8 and extloadi16 
llvm-svn: 31052
 2006-10-19 17:05:03 +00:00
Rafael Espindola
35e92188e0 implement undef 
llvm-svn: 31049
 2006-10-19 13:45:00 +00:00
Rafael Espindola
f7a41f3ddd print common symbols 
llvm-svn: 31048
 2006-10-19 13:30:40 +00:00
Rafael Espindola
722266845b implement extloadi8 and extloadi16 
llvm-svn: 31047
 2006-10-19 12:45:04 +00:00
Rafael Espindola
17544c1c1d expand SIGN_EXTEND_INREG 
llvm-svn: 31046
 2006-10-19 12:06:50 +00:00
Rafael Espindola
6cc20c7950 expand brind so that we don't have to implement jump tables right now 
llvm-svn: 31045
 2006-10-19 10:56:43 +00:00
Rafael Espindola
1220d18e11 add blx 
llvm-svn: 31037
 2006-10-18 16:21:43 +00:00
Rafael Espindola
73e8f41749 add isTerminatortto b and bcond 
llvm-svn: 31036
 2006-10-18 16:20:57 +00:00
Rafael Espindola
80c7461ada implement CallingConv::Fast as CallingConv::C 
llvm-svn: 31034
 2006-10-18 12:03:07 +00:00
Rafael Espindola
58233f9db2 expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM 
llvm-svn: 31014
 2006-10-17 21:05:33 +00:00
Rafael Espindola
4e8824608e add the FPUnaryOp and DFPUnaryOp classes 
llvm-svn: 31013
 2006-10-17 20:45:22 +00:00
Rafael Espindola
fe0a9a6fe2 add FABSS and FABSD 
llvm-svn: 31012
 2006-10-17 20:33:13 +00:00
Rafael Espindola
64f93033bc remove extra [] in stores 
llvm-svn: 31008
 2006-10-17 18:29:14 +00:00
Rafael Espindola
47970f96ac initial implementation of addressing mode 5 
llvm-svn: 31002
 2006-10-17 18:04:53 +00:00
Rafael Espindola
d5a6eaec14 add the immediate to the Offset in eliminateFrameIndex 
llvm-svn: 30998
 2006-10-17 14:34:02 +00:00
Rafael Espindola
31f59f5b94 add FSTD and FSTS 
llvm-svn: 30996
 2006-10-17 13:36:07 +00:00
Rafael Espindola
01400015fc add FCPYS and FCPYD 
llvm-svn: 30995
 2006-10-17 13:13:23 +00:00
Rafael Espindola
a156538e34 add fdivs e fdivd 
llvm-svn: 30988
 2006-10-16 21:50:04 +00:00
Rafael Espindola
4f61431679 expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS 
llvm-svn: 30987
 2006-10-16 21:10:32 +00:00
Rafael Espindola
25fbeb5ec2 define the DFPBinOp class 
llvm-svn: 30981
 2006-10-16 18:39:22 +00:00
Rafael Espindola
57dc40a3a8 add the FPBinOp class 
llvm-svn: 30980
 2006-10-16 18:32:36 +00:00
Rafael Espindola
8a40de94f2 define the Addr1BinOp class 
llvm-svn: 30979
 2006-10-16 18:18:14 +00:00
Rafael Espindola
6554b1014d define the IntBinOp class and use it to implement the multiply instructions 
llvm-svn: 30978
 2006-10-16 17:57:20 +00:00
Rafael Espindola
71ae8c3d4a fix assembly syntax 
llvm-svn: 30977
 2006-10-16 17:38:12 +00:00
Rafael Espindola
d255bfb09b implement LDRB, LDRSB, LDRH and LDRSH 
llvm-svn: 30976
 2006-10-16 17:17:22 +00:00
Rafael Espindola
93359fa883 implement smull and umull 
llvm-svn: 30975
 2006-10-16 16:33:29 +00:00
Rafael Espindola
c426cede28 expand ISD::BRCOND 
llvm-svn: 30963
 2006-10-14 17:59:54 +00:00
Rafael Espindola
38c602f658 fix some fp condition codes 
use non trapping comparison instructions

llvm-svn: 30962
 2006-10-14 13:42:53 +00:00
Evan Cheng
fe5bb5dbe6 Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. 
llvm-svn: 30945
 2006-10-13 21:14:26 +00:00
Rafael Espindola
1f85e7a2a1 add FNEGS and FNEGD 
llvm-svn: 30932
 2006-10-13 17:37:35 +00:00
Rafael Espindola
042e61af25 add SBCS and SUBS 
llvm-svn: 30930
 2006-10-13 17:19:20 +00:00
Rafael Espindola
24d7976d1d implement calls to functions that return long 
llvm-svn: 30929
 2006-10-13 16:47:22 +00:00
Rafael Espindola
bd50a4d757 implement unordered floating point compares 
llvm-svn: 30928
 2006-10-13 13:14:59 +00:00
Chris Lattner
b7ff3d59f7 mark call adjustments as modifying the SP 
llvm-svn: 30911
 2006-10-12 18:00:26 +00:00
Evan Cheng
ca66f49574 Add properties to ComplexPattern. 
llvm-svn: 30891
 2006-10-11 21:03:53 +00:00
Rafael Espindola
46e7aceb1d uint <-> double conversion 
llvm-svn: 30862
 2006-10-10 20:38:57 +00:00
Rafael Espindola
0112351e9a add fp sub 
llvm-svn: 30859
 2006-10-10 19:35:01 +00:00
Rafael Espindola
27d68a3c22 add double <-> int conversion 
llvm-svn: 30858
 2006-10-10 18:55:14 +00:00
Rafael Espindola
413aa20bc8 compare doubles 
llvm-svn: 30856
 2006-10-10 16:33:47 +00:00
Rafael Espindola
b0719f1374 initial support for fp compares. Unordered compares not implemented yet 
llvm-svn: 30854
 2006-10-10 12:56:00 +00:00
Evan Cheng
d22f3dd3ed Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. 
llvm-svn: 30844
 2006-10-09 20:57:25 +00:00
Rafael Espindola
bae07b25d6 add float -> double and double -> float conversion 
llvm-svn: 30835
 2006-10-09 17:50:29 +00:00
Rafael Espindola
f917f096e2 add ADDS and ADCS 
llvm-svn: 30830
 2006-10-09 17:18:28 +00:00
Rafael Espindola
319b5e9c95 expand ISD::SELECT 
llvm-svn: 30829
 2006-10-09 16:28:33 +00:00
Rafael Espindola
fed11f040c add a note 
llvm-svn: 30828
 2006-10-09 14:18:33 +00:00
Rafael Espindola
aaeadcb6f5 expand ISD::EXTLOAD 
llvm-svn: 30827
 2006-10-09 14:13:40 +00:00
Rafael Espindola
1e16a7e972 most ARM targets are little endian 
llvm-svn: 30826
 2006-10-09 14:12:15 +00:00
Rafael Espindola
38e9e2e01d implement FUITOS and FUITOD 
llvm-svn: 30803
 2006-10-07 14:24:52 +00:00
Rafael Espindola
90a24709fb implement FLDD 
llvm-svn: 30802
 2006-10-07 14:03:39 +00:00
Rafael Espindola
b8ce0f8bbd implement fadds, faddd, fmuls and fmuld 
llvm-svn: 30801
 2006-10-07 13:46:42 +00:00
Rafael Espindola
a96c205e12 add optional input flag to FMRRD 
llvm-svn: 30774
 2006-10-06 20:33:26 +00:00
Rafael Espindola
54301ca490 add support for calling functions that return double 
llvm-svn: 30771
 2006-10-06 19:10:05 +00:00
Rafael Espindola
d870b158b3 fix some bugs affecting functions with no arguments 
llvm-svn: 30767
 2006-10-06 17:26:30 +00:00
Rafael Espindola
f35563ff66 fix the stack alignment 
llvm-svn: 30766
 2006-10-06 14:29:47 +00:00
Rafael Espindola
f679bdf121 add support for calling functions that have double arguments 
llvm-svn: 30765
 2006-10-06 12:50:22 +00:00
Evan Cheng
275825195a Make use of getStore(). 
llvm-svn: 30759
 2006-10-05 23:01:46 +00:00
Rafael Espindola
2e4743b6d1 use a const ref for passing the vector to ArgumentLayout 
llvm-svn: 30756
 2006-10-05 17:46:48 +00:00
Rafael Espindola
f0e4950ef4 implement a ArgumentLayout class to factor code common to LowerFORMAL_ARGUMENTS and LowerCALL 
implement FMDRR
add support for f64 function arguments

llvm-svn: 30754
 2006-10-05 16:48:49 +00:00
Chris Lattner
068190eb91 Pass the MachineFunction into EmitJumpTableInfo. 
llvm-svn: 30742
 2006-10-05 03:01:21 +00:00
Chris Lattner
cc21d20348 Use getSectionForFunction. 
llvm-svn: 30740
 2006-10-05 02:49:23 +00:00
Rafael Espindola
b77754ce4d Implement floating point constants 
llvm-svn: 30704
 2006-10-03 17:27:58 +00:00
Rafael Espindola
36c3e0028b fix the names of the 64bit fp register 
initial support for returning 64bit floating point numbers

llvm-svn: 30692
 2006-10-02 19:30:56 +00:00
Rafael Espindola
1b39270c95 add floating point registers 
implement SINT_TO_FP

llvm-svn: 30673
 2006-09-29 21:20:16 +00:00
Rafael Espindola
9cfd72a3d1 add a note 
llvm-svn: 30581
 2006-09-22 11:36:17 +00:00
Rafael Espindola
a51ec7153c more condition codes 
llvm-svn: 30567
 2006-09-21 13:06:26 +00:00
Rafael Espindola
4de4f87be5 if a constant can't be an immediate, add it to the constant pool 
llvm-svn: 30566
 2006-09-21 11:29:52 +00:00
Rafael Espindola
cd52f85028 fix header 
add comments
untabify

llvm-svn: 30486
 2006-09-19 16:41:40 +00:00
Rafael Espindola
6c7627e002 Implement a MachineFunctionPass to fix the mul instruction 
llvm-svn: 30485
 2006-09-19 15:49:25 +00:00
Rafael Espindola
1a3020bfcf add shifts to addressing mode 1 
llvm-svn: 30291
 2006-09-13 12:09:43 +00:00
Evan Cheng
dd52a60189 Reflects MachineConstantPoolEntry changes. 
llvm-svn: 30279
 2006-09-12 21:04:05 +00:00
Rafael Espindola
7722bae67e implement SRL and MUL 
llvm-svn: 30262
 2006-09-11 19:24:19 +00:00
Rafael Espindola
d8b1142d79 add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1 
llvm-svn: 30261
 2006-09-11 19:23:32 +00:00
Rafael Espindola
89ac048c5d partial implementation of the ARM Addressing Mode 1 
llvm-svn: 30252
 2006-09-11 17:25:40 +00:00
Rafael Espindola
a8dd3960f1 call AsmPrinter::doInitialization in ARMAsmPrinter::doInitialization 
llvm-svn: 30246
 2006-09-11 12:49:38 +00:00
Anton Korobeynikov
4141c7992e Removed unnecessary Mangler creation. 
llvm-svn: 30239
 2006-09-10 21:17:03 +00:00
Rafael Espindola
20146be5e8 implement shl and sra 
llvm-svn: 30191
 2006-09-08 17:36:23 +00:00
Rafael Espindola
9ffcdb8ab7 add the eor (xor) instruction 
llvm-svn: 30189
 2006-09-08 16:59:47 +00:00
Rafael Espindola
af1689d5a5 implement unconditional branches 
fix select.ll

llvm-svn: 30186
 2006-09-08 12:47:03 +00:00
Jim Laskey
160a8aa339 1. Remove condition on delete. 
2. Protect and outline createTargetAsmInfo.

3. Misc. kruft.

llvm-svn: 30169
 2006-09-07 23:39:26 +00:00
Jim Laskey
9da25f6119 Make target asm info a property of the target machine. 
llvm-svn: 30162
 2006-09-07 22:06:40 +00:00
Jim Laskey
a64fe8ccf2 Break out target asm info into separate files. 
llvm-svn: 30161
 2006-09-07 22:05:02 +00:00
Jim Laskey
6b86ef852c Separate target specific asm properties from the asm printers. 
llvm-svn: 30126
 2006-09-06 18:34:40 +00:00
Rafael Espindola
d9cebd5e48 add the orr instruction 
llvm-svn: 30125
 2006-09-06 18:03:12 +00:00
Chris Lattner
9cd4e3429e Completely eliminate def&use operands. Now a register operand is EITHER a 
def operand or a use operand.

llvm-svn: 30109
 2006-09-05 02:31:13 +00:00
Rafael Espindola
de18749e1f add support for returning 64bit values 
llvm-svn: 30103
 2006-09-04 19:05:01 +00:00
Chris Lattner
33c9ddc91d Completely rearchitect the interface between targets and the pass manager. 
This pass:

1. Splits TargetMachine into TargetMachine (generic targets, can be implemented
any way, like the CBE) and LLVMTargetMachine (subclass of TM that is used by
things using libcodegen and other support).
2. Instead of having each target fully populate the passmgr for file or JIT
   output, move all this to common code, and give targets hooks they can
   implement.
3. Commonalize the target population stuff between file emission and JIT
   emission.
4. All (native code) codegen stuff now happens in a FunctionPassManager, which
   paves the way for "fast -O0" stuff in the CFE later, and now LLC could
   lazily stream .bc files from disk to use less memory.
5. There are now many fewer #includes and the targets don't depend on the
   scalar xforms or libanalysis anymore (but codegen does).
6. Changing common code generator pass ordering stuff no longer requires
   touching all targets.
7. The JIT now has the option of "-fast" codegen or normal optimized codegen,
   which is now orthogonal to the fact that JIT'ing is being done.

llvm-svn: 30081
 2006-09-04 04:14:57 +00:00
Chris Lattner
fb12884be6 Simplify target construction. 
llvm-svn: 30070
 2006-09-03 18:44:02 +00:00
Rafael Espindola
65007fc49c add the SETULT condition code 
llvm-svn: 30067
 2006-09-03 13:19:16 +00:00
Rafael Espindola
5c0443c41e add more condition codes 
llvm-svn: 30056
 2006-09-02 20:24:25 +00:00
Evan Cheng
2db7799507 Select() no longer require Result operand by reference. 
llvm-svn: 29898
 2006-08-26 05:34:46 +00:00
Rafael Espindola
91954ae78f use @ for comments 
store LR in an arbitrary stack slot
add support for writing varargs functions

llvm-svn: 29876
 2006-08-25 17:55:16 +00:00
Rafael Espindola
fb63eba81c add the "eq" condition code 
implement a movcond instruction

llvm-svn: 29857
 2006-08-24 17:19:08 +00:00
Rafael Espindola
cf999a6d39 create a generic bcond instruction that has a conditional code argument 
llvm-svn: 29856
 2006-08-24 16:13:15 +00:00
Rafael Espindola
9e2a2dfb2d initial support for branches 
llvm-svn: 29854
 2006-08-24 13:45:55 +00:00
Rafael Espindola
af0512fc8d add a README.txt 
llvm-svn: 29814
 2006-08-22 12:22:46 +00:00
Rafael Espindola
474f6c5bf1 initial support for select 
llvm-svn: 29802
 2006-08-21 22:00:32 +00:00
Rafael Espindola
13eb38e699 add the and instruction 
llvm-svn: 29793
 2006-08-21 13:58:59 +00:00
Rafael Espindola
c255c4c434 call computeRegisterProperties 
llvm-svn: 29780
 2006-08-20 01:49:49 +00:00
Chris Lattner
db290f7479 Constify some methods. Patch provided by Anton Vayvod, thanks! 
llvm-svn: 29756
 2006-08-17 22:00:08 +00:00
Rafael Espindola
ff879761c1 add a "load effective address" 
llvm-svn: 29748
 2006-08-17 17:09:40 +00:00
Rafael Espindola
b98e92cb78 Declare the callee saved regs 
Remove the hard coded store and load of the link register
Implement ARMFrameInfo

llvm-svn: 29727
 2006-08-16 14:43:33 +00:00
Rafael Espindola
48bed9023d select code like 
ldr rx, [ry, #offset]

llvm-svn: 29664
 2006-08-14 19:01:24 +00:00
Chris Lattner
8ca6e82bce Eliminate use of getNode that takes a vector. 
llvm-svn: 29614
 2006-08-11 17:38:39 +00:00
Chris Lattner
be2765058e elimiante use of getNode that takes vector of operands. 
llvm-svn: 29612
 2006-08-11 17:22:35 +00:00
Evan Cheng
6053206580 Match tablegen changes. 
llvm-svn: 29604
 2006-08-11 09:08:15 +00:00
Evan Cheng
34a49551f5 CALLSEQ_* produces chain even if that's not needed. 
llvm-svn: 29603
 2006-08-11 09:03:33 +00:00
Rafael Espindola
2ddcf46717 correctly set LocalAreaOffset of TargetFrameInfo 
llvm-svn: 29589
 2006-08-09 17:37:45 +00:00
Rafael Espindola
f0b265b48b fix the spill code 
llvm-svn: 29583
 2006-08-09 16:41:12 +00:00
Rafael Espindola
9e8af5c486 fix the loading of the link register in emitepilogue 
llvm-svn: 29580
 2006-08-09 13:15:47 +00:00
Rafael Espindola
ae2d1c53c7 change the addressing mode of the str instruction to reg+imm 
llvm-svn: 29571
 2006-08-08 20:35:03 +00:00
Rafael Espindola
7bfbb91f75 initial support for variable number of arguments 
llvm-svn: 29567
 2006-08-08 13:02:29 +00:00
Evan Cheng
d18be1d9c1 Match tablegen isel changes. 
llvm-svn: 29549
 2006-08-07 22:28:20 +00:00
Rafael Espindola
bd29d36be4 use a 'register pressure reducing' scheduler 
make sure only one move is used in a hello world

llvm-svn: 29520
 2006-08-04 12:48:42 +00:00
Rafael Espindola
97918b1d11 Bug fix: always generate a RET_FLAG in LowerRET 
fixes ret_null.ll and call.ll

llvm-svn: 29519
 2006-08-03 22:50:11 +00:00
Rafael Espindola
fa94338687 add and use ARMISD::RET_FLAG 
llvm-svn: 29499
 2006-08-03 17:02:20 +00:00
Rafael Espindola
719336441f start comments with # 
move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save

llvm-svn: 29451
 2006-08-01 18:53:10 +00:00
Rafael Espindola
f11277971f implement LowerConstantPool and LowerGlobalAddress 
llvm-svn: 29433
 2006-08-01 12:58:43 +00:00
Rafael Espindola
0ea0399411 handle GlobalValue::InternalLinkage in doFinalization 
llvm-svn: 29417
 2006-07-31 20:38:13 +00:00
Evan Cheng
3b5f1c6248 Remove InFlightSet hack. No longer needed. 
llvm-svn: 29373
 2006-07-28 00:47:19 +00:00
Rafael Espindola
c0ede90402 emit global constants 
llvm-svn: 29344
 2006-07-27 11:38:51 +00:00
Rafael Espindola
2919d4ce24 implement function calling of functions with up to 4 arguments 
llvm-svn: 29274
 2006-07-25 20:17:20 +00:00
Rafael Espindola
9ea0bc742c implemented sub 
correctly update the stack pointer in the prologue and epilogue

llvm-svn: 29244
 2006-07-21 12:26:16 +00:00
Rafael Espindola
ad256854c0 initial prologue and epilogue implementation. Need to define add and sub before finishing it :-) 
llvm-svn: 29175
 2006-07-18 17:00:30 +00:00
Rafael Espindola
40073f5767 skeleton of a lowerCall implementation for ARM 
llvm-svn: 29159
 2006-07-16 01:02:57 +00:00
Rafael Espindola
fdfaee67f5 add the memri memory operand 
this makes it possible for ldr instructions with non-zero immediate

llvm-svn: 29103
 2006-07-11 11:36:48 +00:00
Rafael Espindola
071c83dff0 create the raddr addressing mode that matches any register and the frame index 
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot

llvm-svn: 29079
 2006-07-10 01:41:35 +00:00
Rafael Espindola
f11f34a3d6 handle the "mov reg1, reg2" case in isMoveInstr 
llvm-svn: 28945
 2006-06-27 21:52:45 +00:00
Rafael Espindola
14a59f5b6e initial implementation of ARMRegisterInfo::eliminateFrameIndex 
fixes test/Regression/CodeGen/ARM/ret_arg5.ll

llvm-svn: 28854
 2006-06-18 00:08:07 +00:00
Chris Lattner
6a9ec7e80e Don't pass target name into TargetData anymore, it is never used or needed. 
Remove explicit casts to std::string now that there is no overload resolution
issues in the TargetData ctors.

llvm-svn: 28830
 2006-06-16 18:22:52 +00:00
Rafael Espindola
bcba226a99 lower more then 4 formal arguments. The offset is currently hard coded. 
implement SelectFrameIndex

llvm-svn: 28751
 2006-06-12 12:28:08 +00:00
Rafael Espindola
42375303a6 add R0 to liveout 
expand "ret null" (implements test/Regression/CodeGen/ARM/ret_void.ll)
note that a Flag link is missing between the copy and the branch

llvm-svn: 28691
 2006-06-05 22:26:14 +00:00
Rafael Espindola
1bf57da16e Expand ret into "CopyToReg;BRIND" 
llvm-svn: 28559
 2006-05-30 17:33:19 +00:00
Chris Lattner
e1552475d3 Ignore generated files 
llvm-svn: 28520
 2006-05-27 01:23:30 +00:00
Evan Cheng
de0f25081a Change RET node to include signness information of the return values. i.e. 
RET chain, value1, sign1, value2, sign2, ...

llvm-svn: 28510
 2006-05-26 23:10:12 +00:00