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llvm-mirror/test/CodeGen/RISCV
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Craig Topper acb413fc74 [RISCV] Custom lower ISD::VSCALE. 
This patch custom lowers ISD::VSCALE into a csrr vlenb followed
by a shift right by 3 followed by a multiply by the scale amount.

I've added computeKnownBits support to indicate that the csrr vlenb
always produces 3 trailng bits of 0s so the shift right is "exact".
This allows the shift and multiply sequence to be nicely optimized
into a single shift or removed completely when the scale amount is
a power of 2.

The non power of 2 case multiplying by 24 is still producing
suboptimal code. We could remove the right shift and use a
multiply by 3. Hopefully we can improve DAG combine to fix that
since it's not unique to this sequence.

This replaces D94144.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D94249
2021-01-13 17:14:49 -08:00
..
GlobalISel
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
intrinsics
[RISCV] Lower llvm.trap and llvm.debugtrap
2019-10-28 09:54:33 +00:00
rvv
[RISCV] Custom lower ISD::VSCALE.
2021-01-13 17:14:49 -08:00
add-before-shl.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
add-imm.ll
[RISCV] optimize addition with a pair of (addi imm)
2020-07-07 18:57:28 -07:00
addc-adde-sube-subc.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
addcarry.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
addimm-mulimm.ll
[RISCV][test] Add a test for (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) transformation
2020-07-10 18:33:12 -07:00
addrspacecast.ll
[RISCV] Assume no-op addrspacecasts by default
2020-12-18 21:03:37 +00:00
align.ll
…
alloca.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
alu8.ll
[RISCV] Don't print zext.b alias.
2021-01-05 10:41:08 -08:00
alu16.ll
…
alu32.ll
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
2019-08-06 00:24:00 +00:00
alu64.ll
[RISCV] Add isel pattern to match (i64 (sra (shl X, 32), C)) to SRAIW if C > 32.
2020-11-25 21:57:48 -08:00
analyze-branch.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
arith-with-overflow.ll
[TargetLowering] Simplify expansion of S{ADD,SUB}O
2019-09-30 07:58:50 +00:00
atomic-cmpxchg-flag.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
atomic-cmpxchg.ll
[RISCV] Don't print zext.b alias.
2021-01-05 10:41:08 -08:00
atomic-fence.ll
…
atomic-load-store.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
atomic-rmw.ll
[RISCV] Don't print zext.b alias.
2021-01-05 10:41:08 -08:00
attributes.ll
[RISCV] ELF attribute section for RISC-V.
2020-03-31 16:16:19 +08:00
bare-select.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
blockaddress.ll
[RISCV] Fix inaccurate annotations on PseudoBRIND
2020-08-21 11:38:42 +01:00
branch-relaxation.ll
[RISCV] Indirect branch generation in position independent code
2020-08-17 13:09:26 +01:00
branch.ll
Revert "[BPI] Improve static heuristics for integer comparisons"
2020-08-17 20:44:33 +02:00
bswap-ctlz-cttz-ctpop.ll
[RISCV] Don't print zext.b alias.
2021-01-05 10:41:08 -08:00
byval.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
callee-saved-fpr32s.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
callee-saved-fpr64s.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
callee-saved-gprs.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
calling-conv-ilp32-ilp32f-common.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll
[RISCV] Don't print zext.b alias.
2021-01-05 10:41:08 -08:00
calling-conv-ilp32.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
calling-conv-ilp32d.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
calling-conv-ilp32f-ilp32d-common.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
calling-conv-lp64-lp64f-common.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
calling-conv-lp64-lp64f-lp64d-common.ll
[RISCV] Don't print zext.b alias.
2021-01-05 10:41:08 -08:00
calling-conv-lp64.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
calling-conv-rv32f-ilp32.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
calling-conv-sext-zext.ll
[RISCV] Don't print zext.b alias.
2021-01-05 10:41:08 -08:00
calls.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
cmp-bool.ll
[DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1)
2020-07-15 07:34:22 +00:00
codemodel-lowering.ll
[RISCV] Fix inaccurate annotations on PseudoBRIND
2020-08-21 11:38:42 +01:00
compress-float.ll
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
compress-inline-asm.ll
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
compress.ll
[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump
2020-12-04 10:34:12 -08:00
copy-frameindex.mir
[RISCV] Only return DestSourcePair from isCopyInstrImpl for registers
2020-11-03 03:55:47 +00:00
copysign-casts.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
disable-tail-calls.ll
…
disjoint.ll
[RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook
2019-11-05 09:39:06 +00:00
div.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
double-arith.ll
[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
2020-11-25 15:07:34 -08:00
double-bitmanip-dagcombines.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
double-br-fcmp.ll
[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
2021-01-12 10:45:03 -08:00
double-calling-conv.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
double-convert.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
double-fcmp.ll
[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
2021-01-12 10:45:03 -08:00
double-frem.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
double-imm.ll
[RISCV] Support Constant Pools in Load/Store Peephole
2020-05-11 19:20:38 +01:00
double-intrinsics.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
double-isnan.ll
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
double-mem.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
double-previous-failure.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
double-select-fcmp.ll
[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
2021-01-12 10:45:03 -08:00
double-stack-spill-restore.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
dwarf-eh.ll
[RISCV][NFC] Remove outdated TODO from test/CodeGen/RISCV/dwarf-eh.ll
2019-07-17 14:04:48 +00:00
exception-pointer-register.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
fastcc-float.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
fastcc-int.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
fixups-diff.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
fixups-relax-diff.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
float-arith.ll
[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
2020-11-25 15:07:34 -08:00
float-bit-preserving-dagcombines.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
float-bitmanip-dagcombines.ll
…
float-br-fcmp.ll
[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
2021-01-12 10:45:03 -08:00
float-convert.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
float-fcmp.ll
[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
2021-01-12 10:45:03 -08:00
float-frem.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
float-imm.ll
[RISCV] Support Constant Pools in Load/Store Peephole
2020-05-11 19:20:38 +01:00
float-intrinsics.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
float-isnan.ll
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
float-mem.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
float-select-fcmp.ll
[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
2021-01-12 10:45:03 -08:00
flt-rounds.ll
…
fold-addi-loadstore.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
fp16-promote.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
fp128.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
fp-imm.ll
[RISCV] Support Constant Pools in Load/Store Peephole
2020-05-11 19:20:38 +01:00
frame-info.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
frame.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
frameaddr-returnaddr.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
get-register-invalid.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
get-register-noreserve.ll
[RISCV] Implement the TargetLowering::getRegisterByName hook
2019-11-04 11:23:54 +00:00
get-register-reserve.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
get-setcc-result-type.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
ghccc-rv32.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
ghccc-rv64.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
half-arith.ll
[RISCV] Add additional half precision fnmadd/fnmsub tests with an fneg on the second operand instead of the first.
2020-12-02 21:13:42 -08:00
half-bitmanip-dagcombines.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
half-br-fcmp.ll
[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
2021-01-12 10:45:03 -08:00
half-convert.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
half-fcmp.ll
[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
2021-01-12 10:45:03 -08:00
half-imm.ll
[RISCV] Support Zfh half-precision floating-point extension.
2020-12-03 09:16:33 +08:00
half-intrinsics.ll
[RISCV] Add f16 to isFMAFasterThanFMulAndFAdd now that the Zfh extension is supported
2020-12-02 20:31:43 -08:00
half-isnan.ll
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
half-mem.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
half-select-fcmp.ll
[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
2021-01-12 10:45:03 -08:00
hoist-global-addr-base.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
i32-icmp.ll
[RISCV] Optimize seteq/setne pattern expansions for better code size
2020-02-11 22:45:15 +08:00
imm-cse.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
imm.ll
[RISCV][NFC] Add more tests for 32-bit constant materialization
2020-10-22 11:36:34 +01:00
indirectbr.ll
[RISCV] Fix inaccurate annotations on PseudoBRIND
2020-08-21 11:38:42 +01:00
init-array.ll
…
inline-asm-abi-names.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
inline-asm-clobbers.ll
[RISCV] Add support for lowering floating point inlineasm clobbers
2019-07-31 09:07:21 +00:00
inline-asm-d-abi-names.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
inline-asm-d-constraint-f.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
inline-asm-f-abi-names.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
inline-asm-f-constraint-f.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
Emit diagnostic if an inline asm constraint requires an immediate
2019-08-03 05:52:47 +00:00
inline-asm.ll
[MC][RISCV] Set UseIntegratedAssembler to true
2020-07-12 21:04:48 -07:00
interrupt-attr-args-error.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
interrupt-attr-callee.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
interrupt-attr-invalid.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
interrupt-attr-nocall.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
interrupt-attr-ret-error.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
interrupt-attr.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
jumptable.ll
[RISCV] Basic jump table lowering
2020-12-22 15:05:54 +00:00
large-stack.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
legalize-fneg.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
lit.local.cfg
…
lsr-legaladdimm.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
machineoutliner.mir
[RISCV] Enable the machine outliner for RISC-V
2019-12-19 16:41:53 +00:00
mattr-invalid-combination.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
mem64.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
mem.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
mir-target-flags.ll
[TargetMachine] Don't imply dso_local on function declarations in Reloc::Static model for ELF/wasm
2020-12-05 14:54:37 -08:00
module-target-abi2.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
module-target-abi.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
mul.ll
[RISCV] Optimize multiplication with constant
2021-01-09 10:37:21 +08:00
musttail-call.ll
OpaquePtr: Bulk update tests to use typed sret
2020-11-20 17:58:26 -05:00
neg-abs.ll
[SelectionDAGBuilder] Add SPF_NABS support to visitSelect
2020-11-25 14:54:26 -08:00
nomerge.ll
Add NoMerge MIFlag to avoid MIR branch folding
2020-05-29 12:31:06 -07:00
option-nopic.ll
[RISCV][AsmParser] Implement .option (no)pic
2020-04-17 12:08:30 +00:00
option-norelax.ll
[llvm-objdump] -d: print 00000000 <foo>: instead of 00000000 foo:
2020-03-05 18:05:28 -08:00
option-norvc.ll
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
option-pic.ll
[RISCV][AsmParser] Implement .option (no)pic
2020-04-17 12:08:30 +00:00
option-relax.ll
[llvm-objdump] -d: print 00000000 <foo>: instead of 00000000 foo:
2020-03-05 18:05:28 -08:00
option-rvc.ll
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
pic-models.ll
Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
2020-07-14 11:15:01 +01:00
pr40333.ll
…
prefetch.ll
…
readcyclecounter.ll
[RISCV] Support @llvm.readcyclecounter() Intrinsic
2019-07-05 12:35:21 +00:00
rem.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
remat.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
reserved-reg-errors.ll
[RISCV] Add support for -ffixed-xX flags
2019-10-22 21:25:01 +01:00
reserved-regs.ll
[RISCV] Add support for -ffixed-xX flags
2019-10-22 21:25:01 +01:00
rotl-rotr.ll
…
rv32e.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
rv32i-rv64i-float-double.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
rv32i-rv64i-half.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
rv32Zbb.ll
[RISCV] Legalize select when Zbt extension available
2021-01-12 21:24:38 +00:00
rv32Zbbp.ll
[RISCV] Legalize select when Zbt extension available
2021-01-12 21:24:38 +00:00
rv32Zbp.ll
[RISCV] Form GORCI from (or (rotl/rotr X, Bitwidth/2), X).
2020-12-07 10:28:04 -08:00
rv32Zbs.ll
[RISCV] Legalize select when Zbt extension available
2021-01-12 21:24:38 +00:00
rv32Zbt.ll
[RISCV] Legalize select when Zbt extension available
2021-01-12 21:24:38 +00:00
rv64-large-stack.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
rv64d-double-convert.ll
[RISCV] Use fcvt.h/d/f.w if the input is an assertsexti32 not just when the input is sext_inreg.
2020-12-04 18:40:02 -08:00
rv64f-float-convert.ll
[RISCV] Use fcvt.h/d/f.w if the input is an assertsexti32 not just when the input is sext_inreg.
2020-12-04 18:40:02 -08:00
rv64f-half-convert.ll
[RISCV] Use fcvt.h/d/f.w if the input is an assertsexti32 not just when the input is sext_inreg.
2020-12-04 18:40:02 -08:00
rv64i-complex-float.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
rv64i-demanded-bits.ll
[RISCV] Improve worklist management in the DAG combine for SLLW/SRLW/SRAW
2020-10-29 14:52:53 -07:00
rv64i-double-softfloat.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
rv64i-exhaustive-w-insts.ll
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
2019-08-06 00:24:00 +00:00
rv64i-single-softfloat.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
rv64m-exhaustive-w-insts.ll
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
2019-08-06 00:24:00 +00:00
rv64m-w-insts-legalization.ll
Revert "[BPI] Improve static heuristics for integer comparisons"
2020-08-17 20:44:33 +02:00
rv64Zbb.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
rv64Zbbp.ll
[RISCV] Don't print zext.b alias.
2021-01-05 10:41:08 -08:00
rv64Zbp.ll
[RISCV] Form GORCI from (or (rotl/rotr X, Bitwidth/2), X).
2020-12-07 10:28:04 -08:00
rv64Zbs.ll
[RISCV] Add isel patterns for SBCLRI/SBSETI/SBINVI(W) instruction
2020-12-08 12:22:40 -08:00
rv64Zbt.ll
[RISCV] Legalize select when Zbt extension available
2021-01-12 21:24:38 +00:00
saverestore.ll
[RISCV] Add support for save/restore of callee-saved registers via libcalls
2020-02-11 21:23:03 +00:00
sdata-limit-0.ll
…
sdata-limit-4.ll
…
sdata-limit-8.ll
…
sdata-local-sym.ll
…
select-and.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
select-cc.ll
…
select-const.ll
[RISCV] Support Constant Pools in Load/Store Peephole
2020-05-11 19:20:38 +01:00
select-optimize-multiple.ll
[RISCV] Add MemOperand to the instruction created by storeRegToStackSlot/loadRegFromStackSlot
2020-11-18 19:20:03 -08:00
select-optimize-multiple.mir
[MachineVerifier] Verify that a DBG_VALUE has a debug location
2020-05-28 13:53:40 -07:00
select-or.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
setcc-logic.ll
[RISCV] Optimize seteq/setne pattern expansions for better code size
2020-02-11 22:45:15 +08:00
sext-zext-trunc.ll
[RISCV] Don't print zext.b alias.
2021-01-05 10:41:08 -08:00
shadowcallstack.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
shift-masked-shamt.ll
…
shifts.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
shrinkwrap.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
split-offsets.ll
[RISCV] Fix wrong CFI directives
2019-11-14 18:29:50 +00:00
split-sp-adjust.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
srem-lkk.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
srem-vector-lkk.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
stack-realignment-with-variable-sized-objects.ll
[RISCV] Do not grow the stack a second time when we need to realign the stack
2021-01-09 16:51:09 +00:00
stack-realignment.ll
[RISCV] Do not grow the stack a second time when we need to realign the stack
2021-01-09 16:51:09 +00:00
stack-store-check.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
subtarget-features-std-ext.ll
[RISCV] Support ABI checking with per function target-features
2020-01-22 08:12:28 -08:00
tail-calls.ll
OpaquePtr: Bulk update tests to use typed sret
2020-11-20 17:58:26 -05:00
target-abi-invalid.ll
…
target-abi-valid.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
thread-pointer.ll
[RISCV] Support llvm.thread.pointer
2020-03-27 17:30:12 -07:00
tls-models.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
umulo-128-legalisation-lowering.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
urem-lkk.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
urem-vector-lkk.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
vararg.ll
[RISCV] Replace i32 with XLenVT in (add AddrFI, simm12) isel patterns.
2021-01-04 10:53:27 -08:00
verify-instr.mir
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
wide-mem.ll
[RISCV] Fold ADDIs into load/stores with nonzero offsets
2020-07-06 17:32:57 +01:00
zext-with-load-is-free.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
zfh-imm.ll
[RISCV] Support Zfh half-precision floating-point extension.
2020-12-03 09:16:33 +08:00