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14862 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
0b1e64c1d4 Replace copyRegToReg with copyPhysReg for PowerPC. 
llvm-svn: 108083
 2010-07-11 07:31:00 +00:00
Jakob Stoklund Olesen
84ac13069a Fix PIC16 comments referencing copyRegToReg. 
llvm-svn: 108082
 2010-07-11 07:30:57 +00:00
Jakob Stoklund Olesen
b15ffc7e90 Replace copyRegToReg with copyPhysReg for PIC16. 
llvm-svn: 108081
 2010-07-11 06:53:33 +00:00
Jakob Stoklund Olesen
fb3525531b Replace copyRegToReg with copyPhysReg for MSP430. 
llvm-svn: 108080
 2010-07-11 06:53:30 +00:00
Jakob Stoklund Olesen
beb86cfa27 Replace copyRegToReg with copyPhysReg for MBlaze. 
llvm-svn: 108079
 2010-07-11 06:53:27 +00:00
Jakob Stoklund Olesen
938e41c1fa Replace copyRegToReg with copyPhysReg for ARM. 
llvm-svn: 108078
 2010-07-11 06:33:54 +00:00
Jakob Stoklund Olesen
18e465659f Replace copyRegToReg with copyPhysReg for Blackfin. 
llvm-svn: 108077
 2010-07-11 05:44:34 +00:00
Jakob Stoklund Olesen
821d058fd2 X86InstrInfo::copyRegToReg is dead. Long live copyPhysReg! 
llvm-svn: 108076
 2010-07-11 05:44:30 +00:00
Jakob Stoklund Olesen
08fc7eaaa2 Use COPY in X86FastISel::X86SelectRet. 
Don't try a cross-class copy. That is very unlikely anywy since return value
registers are usually register class friendly. (%EAX, %XMM0, etc).

llvm-svn: 108074
 2010-07-11 05:17:02 +00:00
Rafael Espindola
84716579d4 Fix va_arg for doubles. With this patch VAARG nodes always contain the 
correct alignment information, which simplifies ExpandRes_VAARG a bit.

The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:

* The 's' in target data: If this is set to the minimal alignment of any
  argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
  example.
* The getTransientStackAlignment method. It is possible for an architecture to
  have argument less aligned than what we maintain the stack pointer.

llvm-svn: 108072
 2010-07-11 04:01:49 +00:00
Jakob Stoklund Olesen
57bbaf37c0 Use COPY in FastISel everywhere it is safe and trivial. 
The remaining copyRegToReg calls actually check the return value (shock!), so we
cannot trivially replace them with COPY instructions.

llvm-svn: 108069
 2010-07-11 03:31:00 +00:00
Jakob Stoklund Olesen
c1aca7464d Replace copyRegToReg with copyPhysReg for Mips. 
llvm-svn: 108066
 2010-07-11 01:08:31 +00:00
Jakob Stoklund Olesen
0fc69a96b7 Replace copyRegToReg with copyPhysReg for Alpha. 
llvm-svn: 108065
 2010-07-11 01:08:23 +00:00
Jakob Stoklund Olesen
b1c6191d3b Use COPY in targets 
llvm-svn: 108063
 2010-07-10 22:43:03 +00:00
Jakob Stoklund Olesen
b1e88a2725 Don't emit st(0)/st(1) copies as FpMOV instructions. Use FpSET_ST? instead. 
Based on a patch by Rafael Espíndola.

Attempt to make the FpSET_ST1 hack more robust, but we are still relying on
FpSET_ST0 preceeding it. This is only for supporting really weird x87 inline
asm.

We support:

  FpSET_ST0
  INLINEASM

  FpSET_ST0
  FpSET_ST1
  INLINEASM

with and without kills on the arguments. We don't support:

  FpSET_ST1
  FpSET_ST0
  INLINEASM

nor

  FpSET_ST1
  INLINEASM

Just Don't Do It!

llvm-svn: 108047
 2010-07-10 17:42:34 +00:00
Chandler Carruth
1efbf423c5 Add parentheses yet again to satisfy GCC's warnings. 
llvm-svn: 108043
 2010-07-10 12:06:22 +00:00
Dan Gohman
fef30fcd5e Reapply bottom-up fast-isel, with several fixes for x86-32: 
- Check getBytesToPopOnReturn().
 - Eschew ST0 and ST1 for return values.
 - Fix the PIC base register initialization so that it doesn't ever
   fail to end up the top of the entry block.

llvm-svn: 108039
 2010-07-10 09:00:22 +00:00
Jakob Stoklund Olesen
bf7dddd5b7 An x86 function returns a floating point value in st(0), and we must make sure 
it is popped, even if it is ununsed. A CopyFromReg node is too weak to represent
the required sideeffect, so insert an FpGET_ST0 instruction directly instead.

This will matter when CopyFromReg gets lowered to a generic COPY instruction.

llvm-svn: 108037
 2010-07-10 04:04:25 +00:00
Bruno Cardoso Lopes
3b9d36bde7 Declare YMM subregisters in the right way! Thanks Jakob 
llvm-svn: 108022
 2010-07-09 21:46:19 +00:00
Bruno Cardoso Lopes
f4180a9a7b Add AVX 256-bit packed MOVNT variants 
llvm-svn: 108021
 2010-07-09 21:42:42 +00:00
Jakob Stoklund Olesen
ef941722c5 Remember the *_TC opcodes for load/store 
llvm-svn: 108020
 2010-07-09 21:27:55 +00:00
Bruno Cardoso Lopes
6ca8dc935c Add AVX 256-bit unpack and interleave 
llvm-svn: 108017
 2010-07-09 21:20:35 +00:00
Jakob Stoklund Olesen
d7c882a505 Automatically fold COPY instructions into stack load/store. 
llvm-svn: 108012
 2010-07-09 20:43:13 +00:00
Jakob Stoklund Olesen
53d777f3bd Fix a few tests 
llvm-svn: 108011
 2010-07-09 20:43:09 +00:00
Jim Grosbach
b591b3b48d In the presence of variable sized objects, allocate an emergency spill slot. 
rdar://8131327

llvm-svn: 108008
 2010-07-09 20:27:06 +00:00
Bruno Cardoso Lopes
3676e24b67 Start the support for AVX instructions with 256-bit %ymm registers. A couple of 
notes:
- The instructions are being added with dummy placeholder patterns using some 256
  specifiers, this is not meant to work now, but since there are some multiclasses
  generic enough to accept them,  when we go for codegen, the stuff will be already
  there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
  file.

llvm-svn: 107996
 2010-07-09 18:27:43 +00:00
Bob Wilson
9e8c9204ef --- Reverse-merging r107947 into '.': 
U    utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U    test/CodeGen/X86/fast-isel.ll
U    test/CodeGen/X86/fast-isel-loads.ll
U    include/llvm/Target/TargetLowering.h
U    include/llvm/Support/PassNameParser.h
U    include/llvm/CodeGen/FunctionLoweringInfo.h
U    include/llvm/CodeGen/CallingConvLower.h
U    include/llvm/CodeGen/FastISel.h
U    include/llvm/CodeGen/SelectionDAGISel.h
U    lib/CodeGen/LLVMTargetMachine.cpp
U    lib/CodeGen/CallingConvLower.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U    lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U    lib/CodeGen/SelectionDAG/FastISel.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U    lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U    lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U    lib/CodeGen/SelectionDAG/TargetLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.h
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86ISelLowering.h

llvm-svn: 107987
 2010-07-09 16:37:18 +00:00
Bruno Cardoso Lopes
144923dccf Merge VEX enums with other x86 enum forms. Also fix all checks of which VEX 
fields to use. 

llvm-svn: 107952
 2010-07-09 01:56:45 +00:00
Dan Gohman
dad9d461c3 Fix the memoperand offsets in code generated for va_start. 
llvm-svn: 107948
 2010-07-09 01:06:48 +00:00
Chris Lattner
a5c1c795a2 have the mc lowering process handle a few tail call forms, lowering them to 
jumps where possible and turning the TAILCALL marker in the instruction
asm string into a proper comment.

This eliminates a FIXME and is on the path to finishing:
rdar://7639610 - eliminate encoding and asm info for TAILJMPd TAILJMPr TAILJMPn, etc.

However, I can't eliminate the encodings for these instructions because the JIT
still exists and has its own copy of the encoder, sigh.

llvm-svn: 107946
 2010-07-09 00:49:41 +00:00
Bob Wilson
f15e542bdc Print "dregpair" NEON operands with a space between them, for readability and 
consistency with other instructions that have lists of register operands.

llvm-svn: 107944
 2010-07-09 00:47:20 +00:00
Dan Gohman
7e6e4dd058 Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting 
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.

llvm-svn: 107943
 2010-07-09 00:39:23 +00:00
Bruno Cardoso Lopes
a6bfda61b9 Factor out x86 segment override prefix encoding, and also use it for VEX 
llvm-svn: 107942
 2010-07-09 00:38:14 +00:00
Chris Lattner
fe434abafa reject pseudo instructions early in the encoder. 
llvm-svn: 107939
 2010-07-09 00:17:50 +00:00
Bruno Cardoso Lopes
f00a155876 Remove trailing whitespaces from file 
llvm-svn: 107937
 2010-07-09 00:07:19 +00:00
Chris Lattner
49ac65543c Change LEA to have 5 operands for its memory operand, just 
like all other instructions, even though a segment is not
allowed.  This resolves a bunch of gross hacks in the 
encoder and makes LEA more consistent with the rest of the
instruction set.

No functionality change.

llvm-svn: 107934
 2010-07-08 23:46:44 +00:00
Chris Lattner
18802e1a55 add some long-overdue enums to refer to the parts of the 5-operand 
X86 memory operand.

llvm-svn: 107925
 2010-07-08 22:41:28 +00:00
Jakob Stoklund Olesen
1ae7342eaf Remember the VR64 register class 
llvm-svn: 107920
 2010-07-08 22:30:35 +00:00
Chris Lattner
012d7537ee Rework segment prefix emission code to handle segments 
in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax

This fixes rdar://8127102.  I have several cleanup patches coming
next.

llvm-svn: 107917
 2010-07-08 22:28:12 +00:00
Chris Lattner
660851a040 introduce a new X86II::getMemoryOperandNo method, which 
returns the start of the memory operand for an instruction.

Introduce a new "X86AddrSegment" enum to reduce # magic numbers
referring to X86 memory operand layout.

llvm-svn: 107916
 2010-07-08 22:27:06 +00:00
Kalle Raiskila
725a1a4ad2 Switch SPU calling convention (function arguments) 
to a Tablegen implementation.

llvm-svn: 107913
 2010-07-08 21:15:22 +00:00
Evan Cheng
5307ec12d7 Check for FiniteOnlyFPMath as well. 
llvm-svn: 107904
 2010-07-08 20:12:24 +00:00
Jakob Stoklund Olesen
f9441b5025 Teach the x86 floating point stackifier to handle COPY instructions. 
This pass runs before COPY instructions are passed to copyPhysReg, so we simply
translate COPY to the proper pseudo instruction. Note that copyPhysReg does not
handle floating point stack copies.

Once COPY is used everywhere, this can be cleaned up a bit, and most of the
pseudo instructions can be removed.

llvm-svn: 107899
 2010-07-08 19:46:30 +00:00
Jakob Stoklund Olesen
aed86b1af7 Implement X86InstrInfo::copyPhysReg 
llvm-svn: 107898
 2010-07-08 19:46:25 +00:00
Bob Wilson
12922e6bec The NEONPreAllocPass should never have to assign fixed registers anymore. 
This pass can go away entirely soon.

llvm-svn: 107892
 2010-07-08 17:45:26 +00:00
Bob Wilson
fca7a252fb For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap the 
words within the 64-bit D registers.  Use VLD1/VST1 with 64-bit elements
instead.

llvm-svn: 107890
 2010-07-08 17:44:00 +00:00
Bob Wilson
b07d97d333 Clean up a comment. 
llvm-svn: 107882
 2010-07-08 16:54:45 +00:00
Jakob Stoklund Olesen
30aacf68b9 Convert EXTRACT_SUBREG to COPY when emitting machine instrs. 
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.

Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.

llvm-svn: 107879
 2010-07-08 16:40:22 +00:00
Jakob Stoklund Olesen
8983ea915c Remove references to INSERT_SUBREG after de-SSA. 
Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of
INSERT_SUBREG.

llvm-svn: 107878
 2010-07-08 16:40:15 +00:00
Benjamin Kramer
27eb255a70 Teach instcombine to transform 
(X >s -1) ? C1 : C2 and (X <s  0) ? C2 : C1
into ((X >>s 31) & (C2 - C1)) + C1, avoiding the conditional.

This optimization could be extended to take non-const C1 and C2 but we better
stay conservative to avoid code size bloat for now.

for
int sel(int n) {
     return n >= 0 ? 60 : 100;
}

we now generate
  sarl  $31, %edi
  andl  $40, %edi
  leal  60(%rdi), %eax

instead of
  testl %edi, %edi
  movl  $60, %ecx
  movl  $100, %eax
  cmovnsl %ecx, %eax

llvm-svn: 107866
 2010-07-08 11:39:10 +00:00
Eric Christopher
091bf69467 A slight reworking of the custom patterns for x86-64 tpoff codegen and 
correct the testcase for valid assembly.

Needs more tests.

llvm-svn: 107860
 2010-07-08 07:36:46 +00:00
Evan Cheng
3e8530bf14 r107852 is only safe with -enable-unsafe-fp-math to account for +0.0 == -0.0. 
llvm-svn: 107856
 2010-07-08 06:01:49 +00:00
Evan Cheng
ed3f224f04 Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met: 
1. The arguments are f32.
2. The arguments are loads and they have no uses other than the comparison.
3. The comparison code is EQ or NE.

e.g.
        vldr.32 s0, [r1]
        vldr.32 s1, [r0]
        vcmpe.f32       s1, s0
        vmrs    apsr_nzcv, fpscr
	beq     LBB0_2
=>
        ldr     r1, [r1]
        ldr     r0, [r0]
        cmp     r0, r1
        beq     LBB0_2

More complicated cases will be implemented in subsequent patches.

llvm-svn: 107852
 2010-07-08 02:08:50 +00:00
Dale Johannesen
2df647f882 Changes to ARM tail calls, mostly cosmetic. 
Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.

llvm-svn: 107851
 2010-07-08 01:18:23 +00:00
Dan Gohman
4dcc56a102 Revert 107840 107839 107813 107804 107800 107797 107791. 
Debug info intrinsics win for now.

llvm-svn: 107850
 2010-07-08 01:00:56 +00:00
Jakob Stoklund Olesen
6afcd69bee fix copies to/from GR8_ABCD_H even more 
llvm-svn: 107832
 2010-07-07 23:04:56 +00:00
Jim Grosbach
46d94f1c1e grammar 
llvm-svn: 107831
 2010-07-07 22:53:35 +00:00
Jim Grosbach
8f27ad0d9d Handle cases where the post-RA scheduler may move instructions between the 
address calculation instructions leading up to a jump table when we're trying
to convert them into a TB[H] instruction in Thumb2. This realistically
shouldn't happen much, if at all, for well formed inputs, but it's more correct
to handle it. rdar://7387682

llvm-svn: 107830
 2010-07-07 22:51:22 +00:00
Chris Lattner
155420f59f finish up support for callw: PR7195 
llvm-svn: 107826
 2010-07-07 22:35:13 +00:00
Chris Lattner
6a5db9c9c9 Implement the major chunk of PR7195: support for 'callw' 
in the integrated assembler.  Still some discussion to be
done.

llvm-svn: 107825
 2010-07-07 22:27:31 +00:00
Bruno Cardoso Lopes
b92b51191e Add more assembly opcodes for SSE compare instructions 
llvm-svn: 107823
 2010-07-07 22:24:03 +00:00
Evan Cheng
22b3e8f3b1 Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake. 
llvm-svn: 107820
 2010-07-07 22:15:37 +00:00
Devang Patel
82ccfed750 Print undefined/unknown debug value as "undef". 
llvm-svn: 107818
 2010-07-07 21:52:21 +00:00
Jim Grosbach
d13cc7716e grammar and trailing whitespace 
llvm-svn: 107811
 2010-07-07 21:06:51 +00:00
Jakob Stoklund Olesen
34ec644313 Allow copies between GR8_ABCD_L and GR8_ABCD_H. 
This fixes PR7540.

llvm-svn: 107809
 2010-07-07 20:33:27 +00:00
Dan Gohman
d0caefa601 Implement bottom-up fast-isel. This has the advantage of not requiring 
a separate DCE pass over MachineInstrs.

llvm-svn: 107804
 2010-07-07 19:20:32 +00:00
Dan Gohman
424cc6b616 Add X86FastISel support for return statements. This entails refactoring 
a bunch of stuff, to allow the target-independent calling convention
logic to be employed.

llvm-svn: 107800
 2010-07-07 18:32:53 +00:00
Bruno Cardoso Lopes
8d350872d4 Add AVX AES instructions 
llvm-svn: 107798
 2010-07-07 18:24:20 +00:00
Dan Gohman
b2d5b47efb Give FunctionLoweringInfo an MBB member, avoiding the need to pass it 
around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.

llvm-svn: 107791
 2010-07-07 16:47:08 +00:00
Dan Gohman
b87c534168 Simplify FastISel's constructor by giving it a FunctionLoweringInfo 
instance, rather than pointers to all of FunctionLoweringInfo's
members.

This eliminates an NDEBUG ABI sensitivity.

llvm-svn: 107789
 2010-07-07 16:29:44 +00:00
Dan Gohman
c768525273 Split the SDValue out of OutputArg so that SelectionDAG-independent 
code can do calling-convention queries. This obviates OutputArgReg.

llvm-svn: 107786
 2010-07-07 15:54:55 +00:00
Bruno Cardoso Lopes
6222076cd1 Add AVX SSE4.2 instructions 
llvm-svn: 107752
 2010-07-07 03:39:29 +00:00
Bruno Cardoso Lopes
931471d7e8 Use only one multiclass to pinsrq instructions 
llvm-svn: 107750
 2010-07-07 01:43:01 +00:00
Bruno Cardoso Lopes
65fbd0530f Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes 
llvm-svn: 107749
 2010-07-07 01:33:38 +00:00
Bruno Cardoso Lopes
675ebe2dc0 Add AVX SSE4.1 insertps, ptest and movntdqa instructions 
llvm-svn: 107747
 2010-07-07 01:14:56 +00:00
Bruno Cardoso Lopes
fa10461265 Add AVX SSE4.1 extractps and pinsr instructions 
llvm-svn: 107746
 2010-07-07 01:01:13 +00:00
Bob Wilson
822b21f0de Also use REG_SEQUENCE for VTBX instructions. 
llvm-svn: 107743
 2010-07-07 00:08:54 +00:00
Jim Grosbach
71b7efe8ad Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where 
they've been tested to work.

llvm-svn: 107742
 2010-07-07 00:07:57 +00:00
Bruno Cardoso Lopes
54c2f858b3 Add AVX SSE4.1 Extract Integer instructions 
llvm-svn: 107740
 2010-07-07 00:07:24 +00:00
Jim Grosbach
657ab4a8ee By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather 
than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.

llvm-svn: 107734
 2010-07-06 23:44:52 +00:00
Bob Wilson
ce80768ebf Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be 
allocated to consecutive registers.

llvm-svn: 107730
 2010-07-06 23:36:25 +00:00
Dale Johannesen
81ea05c193 Accept RIP-relative symbols with 'i' constraint, and 
print the (%rip) only if the 'a' modifier is present.
PR 7528.

llvm-svn: 107727
 2010-07-06 23:27:00 +00:00
Jakob Stoklund Olesen
44c333e87c Track defs for all aliases in NEONMoveFix. 
This means that an instruction defining an S register will affect the domain of
the parent D register.

llvm-svn: 107725
 2010-07-06 23:26:23 +00:00
Bruno Cardoso Lopes
b9e1c33054 Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions 
llvm-svn: 107723
 2010-07-06 23:15:17 +00:00
Bruno Cardoso Lopes
0c6ec0b068 Add part of AVX SSE4.1 packed move with sign/zero extend instructions 
llvm-svn: 107720
 2010-07-06 23:01:41 +00:00
Bruno Cardoso Lopes
af8968696a Fix comment from previous patch 
llvm-svn: 107717
 2010-07-06 22:38:32 +00:00
Bruno Cardoso Lopes
a0b37e839c Add AVX vblendvpd, vblendvps and vpblendvb instructions 
Update VEX encoding to support those new instructions

llvm-svn: 107715
 2010-07-06 22:36:24 +00:00
Dan Gohman
d409104054 CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext. 
SelectBasicBlock doesn't needs its BasicBlock argument.

llvm-svn: 107712
 2010-07-06 22:19:37 +00:00
Devang Patel
7ab104353b Propagate debug loc. 
llvm-svn: 107710
 2010-07-06 22:08:15 +00:00
Bob Wilson
084a11cb59 Represent NEON load/store alignments in bytes, not bits. 
llvm-svn: 107701
 2010-07-06 21:26:18 +00:00
Dan Gohman
808f334f79 Reapply r107655 with fixes; insert the pseudo instruction into 
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.

llvm-svn: 107691
 2010-07-06 20:24:04 +00:00
Devang Patel
ffc54b23fe Fix PR7545 crash. 
llvm-svn: 107678
 2010-07-06 18:18:32 +00:00
Rafael Espindola
e5689571a1 Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion 
if profitable.

llvm-svn: 107673
 2010-07-06 16:24:34 +00:00
Dan Gohman
4d264f7e51 Revert r107655. 
llvm-svn: 107668
 2010-07-06 15:49:48 +00:00
Dan Gohman
c88c36181f Make getMinimalPhysRegClass' comment mention what makes it different 
from getPhysicalRegisterRegClass.

llvm-svn: 107660
 2010-07-06 15:31:55 +00:00
Dan Gohman
6a73079aba Fix a bunch of custom-inserter functions to handle the case where 
the pseudo instruction is not at the end of the block.

llvm-svn: 107655
 2010-07-06 15:18:19 +00:00
Eric Christopher
e873e9978c Fix up -fstack-protector on linux to use the segment 
registers.  Split out testcases per architecture and os
now.

Patch from Nelson Elhage.

llvm-svn: 107640
 2010-07-06 05:18:56 +00:00
Eric Christopher
f1bb5da020 Have the X86 backend use Triple instead of a string and some enums. 
llvm-svn: 107625
 2010-07-05 19:26:33 +00:00
Kalle Raiskila
59cf410bf5 Remove some unused/redundant code. 
llvm-svn: 107622
 2010-07-05 18:40:09 +00:00
Chris Lattner
252f82acc6 more tidying. 
llvm-svn: 107615
 2010-07-05 05:53:14 +00:00
Chris Lattner
6a9b6e3253 some notes about suboptimal insertps's 
llvm-svn: 107613
 2010-07-05 05:48:41 +00:00
Chris Lattner
e7c95bcd9e rip out even more sporadic v2f32 support. 
llvm-svn: 107610
 2010-07-05 04:38:33 +00:00
Chris Lattner
82c3b22a55 rip out the various v2f32 "mmx" handling logic, now that 
v2f32 is illegal on x86.

llvm-svn: 107609
 2010-07-05 04:36:27 +00:00
Chris Lattner
cecaa1b061 Just rip v2f32 support completely out of the X86 backend. In 
the example in the testcase, we now generate:

_test1:                                 ## @test1
	movss	4(%esp), %xmm0
	addss	8(%esp), %xmm0
	movl	12(%esp), %eax
	movss	%xmm0, (%eax)
	ret

instead of:

_test1:                                                     ## @test1
	subl	$20, %esp
	movl	24(%esp), %eax
	movq	%mm0, (%esp)
	movq	%mm0, 8(%esp)
	movss	(%esp), %xmm0
	addss	12(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$20, %esp
	ret

v2f32 support did not work reliably because most of the X86
backend didn't know it was legal.  It was apparently only added
to support returning source-level v2f32 values in MMX registers
in x86-32 mode.  If ABI compatibility is important on this
GCC-extended-vector type for some reason, then the frontend
should generate IR that returns v2i32 instead of v2f32.  However,
we generally don't try very hard to be abi compatible on gcc
extended vectors. 

llvm-svn: 107601
 2010-07-04 23:07:25 +00:00
Chris Lattner
b17c4f3936 fix PR7518 - terrible codegen of <2 x float>, by only marking 
v2f32 as legal in 32-bit mode.  It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.

llvm-svn: 107600
 2010-07-04 22:57:10 +00:00
Chris Lattner
1e38d7d66d indentation 
llvm-svn: 107599
 2010-07-04 22:56:10 +00:00
Bill Wendling
689155c673 Revert r107583. I no longer think that this is the way to solve the problem. 
llvm-svn: 107585
 2010-07-04 09:16:57 +00:00
Bill Wendling
8a3ecba7a4 Mark sse_load_f32 and sse_load_f64 as having memory operands 
(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.

llvm-svn: 107583
 2010-07-04 08:59:55 +00:00
Eli Friedman
4cac2d90a2 Minor amendment to switch-lowering improvement. 
llvm-svn: 107569
 2010-07-03 08:43:32 +00:00
Eli Friedman
663bc3ce7e Note switch-lowering inefficiency. 
llvm-svn: 107565
 2010-07-03 07:38:12 +00:00
Bruno Cardoso Lopes
dc16024895 Add AVX SSE4.1 blend, mpsadbw and vdp 
llvm-svn: 107560
 2010-07-03 01:37:03 +00:00
Bruno Cardoso Lopes
9cbb625579 Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions 
llvm-svn: 107558
 2010-07-03 01:15:47 +00:00
Bruno Cardoso Lopes
df02d037e4 Add AVX SSE4.1 Horizontal Minimum and Position instruction 
llvm-svn: 107552
 2010-07-03 00:49:21 +00:00
Evan Cheng
47f3a2db40 Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false. 
llvm-svn: 107550
 2010-07-03 00:40:23 +00:00
Bruno Cardoso Lopes
e6b70efcb0 Add AVX SSE4.1 round instructions 
llvm-svn: 107549
 2010-07-03 00:37:44 +00:00
Bruno Cardoso Lopes
473863e456 Simple refactoring of SSE4.1 instructions, making room for the AVX forms 
llvm-svn: 107540
 2010-07-02 23:27:59 +00:00
Bruno Cardoso Lopes
4931e183b5 - Add support for the rest of AVX SSE3 instructions 
- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode

llvm-svn: 107523
 2010-07-02 22:06:54 +00:00
Evan Cheng
8c4e6ba789 Remove early IT block formation. It's not used. 
llvm-svn: 107513
 2010-07-02 21:07:09 +00:00
Evan Cheng
2954bb814e - Two-address pass should not assume unfolding is always successful. 
- X86 unfolding should check if the instructions being unfolded has memoperands.
  If there is no memoperands, then it must assume conservative alignment. If this
  would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand
  etc. should not unfold the instruction.

llvm-svn: 107509
 2010-07-02 20:36:18 +00:00
Gabor Greif
7d4ffef197 beautify output 
llvm-svn: 107500
 2010-07-02 19:26:28 +00:00
Gabor Greif
92502bcde7 use ArgOperand API 
llvm-svn: 107498
 2010-07-02 19:08:46 +00:00
Bob Wilson
f96aab3079 Fix incorrect asm-printing of some NEON immediates. Fix weak testcase so 
that it checks the immediate values, not just the instructions opcodes.
Radar 8110263.

llvm-svn: 107487
 2010-07-02 17:23:44 +00:00
Gabor Greif
7c64164e6a use ArgOperand API (found by my previous commit) 
llvm-svn: 107482
 2010-07-02 13:37:16 +00:00
Bruno Cardoso Lopes
c5670fcb23 Shrink down SSE3 code by more multiclass refactoring 
llvm-svn: 107448
 2010-07-01 23:10:49 +00:00
Bruno Cardoso Lopes
c215186088 Shrink down SSE3 code by some multiclass refactoring - 1st part 
llvm-svn: 107438
 2010-07-01 22:33:18 +00:00
Bob Wilson
17dc7d716b ARM function alignments were off by a power of two. svn 83242 changed 
getFunctionAlignment and the corresponding use of that value in the ARM
asm printer, but now we're using the standard asm printer.  The result of
this was that function alignments were dropped completely for Thumb functions.
Radar 8143571.

llvm-svn: 107435
 2010-07-01 22:26:26 +00:00
Bill Wendling
90b6422f2f Implement the "linker_private_weak" linkage type. This will be used for 
Objective-C metadata types which should be marked as "weak", but which the
linker will remove upon final linkage. However, this linkage isn't specific to
Objective-C.

For example, the "objc_msgSend_fixup_alloc" symbol is defined like this:

      .globl l_objc_msgSend_fixup_alloc
      .weak_definition l_objc_msgSend_fixup_alloc
      .section __DATA, __objc_msgrefs, coalesced
      .align 3
l_objc_msgSend_fixup_alloc:
       .quad   _objc_msgSend_fixup
       .quad   L_OBJC_METH_VAR_NAME_1

This is different from the "linker_private" linkage type, because it can't have
the metadata defined with ".weak_definition".

Currently only supported on Darwin platforms.

llvm-svn: 107433
 2010-07-01 21:55:59 +00:00
Bruno Cardoso Lopes
511e5f47de Move SSE3 Move patterns to a more appropriate section 
Add AVX SSE3 packed horizontal and & sub instructions

llvm-svn: 107405
 2010-07-01 17:35:02 +00:00
Bruno Cardoso Lopes
0a3048e8b9 Add AVX SSE3 packed addsub instructions 
llvm-svn: 107404
 2010-07-01 17:08:18 +00:00
Dan Gohman
7219aedff5 Enable on-demand fast-isel. 
llvm-svn: 107377
 2010-07-01 02:58:57 +00:00
Dan Gohman
dff0454d78 Fix X86FastISel's add folding to actually work, and not fall back 
to SelectionDAG.

llvm-svn: 107376
 2010-07-01 02:58:21 +00:00
Bruno Cardoso Lopes
c1abe91367 Add AVX SSE3 replicate and convert instructions 
llvm-svn: 107375
 2010-07-01 02:33:39 +00:00
Dan Gohman
243bda093e Teach X86FastISel to fold constant offsets and scaled indices in 
the same address.

llvm-svn: 107373
 2010-07-01 02:27:15 +00:00
Bruno Cardoso Lopes
956316a3d7 - Add AVX SSE2 Move doubleword and quadword instructions. 
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
  in the .td file now have a AVX encoded form already working.

llvm-svn: 107365
 2010-07-01 01:20:06 +00:00
Bruno Cardoso Lopes
7ae1ebd3b4 Move MOVD/MODQ code around, creating sections for each of them 
llvm-svn: 107308
 2010-06-30 18:49:10 +00:00
Bruno Cardoso Lopes
f8855c22be Add AVX SSE2 mask creation and conditional store instructions 
llvm-svn: 107306
 2010-06-30 18:38:10 +00:00
Bruno Cardoso Lopes
6c468039a2 Fix a bug introduced in r107211 where instructions with memory operands are declared as commutable 
llvm-svn: 107300
 2010-06-30 18:06:01 +00:00
Bruno Cardoso Lopes
3c02702830 Add AVX SSE2 packed integer extract/insert instructions 
llvm-svn: 107293
 2010-06-30 17:03:03 +00:00
Gabor Greif
fdaf0459be use ArgOperand API 
llvm-svn: 107280
 2010-06-30 13:03:37 +00:00
Bruno Cardoso Lopes
39594cc5d0 Add AVX SSE2 integer unpack instructions 
llvm-svn: 107246
 2010-06-30 04:06:39 +00:00
Bruno Cardoso Lopes
419f8f29c3 Add AVX SSE2 packed integer shuffle instructions 
llvm-svn: 107245
 2010-06-30 03:47:56 +00:00
Bruno Cardoso Lopes
c2f5cd2389 Small refactoring of SSE2 packed integer shuffle instructions 
llvm-svn: 107243
 2010-06-30 03:29:36 +00:00
Bruno Cardoso Lopes
d9acb34aa2 Add AVX SSE2 pack with saturation integer instructions 
llvm-svn: 107241
 2010-06-30 02:30:25 +00:00
Bruno Cardoso Lopes
c470ba9937 Add AVX SSE2 integer packed compare instructions 
llvm-svn: 107240
 2010-06-30 02:21:09 +00:00
Bruno Cardoso Lopes
cfbebb3921 - Add AVX form of all SSE2 logical instructions 
- Add VEX encoding bits to x86 MRM0r-MRM7r

llvm-svn: 107238
 2010-06-30 01:58:37 +00:00
Bruno Cardoso Lopes
2439877e05 Add *several* AVX integer packed binop instructions 
llvm-svn: 107225
 2010-06-29 23:47:49 +00:00
Bill Wendling
59ef9bcc6d Revert r107205 and r107207. 
llvm-svn: 107215
 2010-06-29 22:34:52 +00:00
Eric Christopher
4c54014a1e Add another bswap idiom that isn't matched. 
llvm-svn: 107213
 2010-06-29 22:22:22 +00:00
Bruno Cardoso Lopes
b80121d316 Move SSE2 Packed Integer instructions around, and create specific sections for each of them 
llvm-svn: 107211
 2010-06-29 22:12:16 +00:00
Bruno Cardoso Lopes
45e0ab4762 Add AVX Move Aligned/Unaligned packed integers 
llvm-svn: 107206
 2010-06-29 21:25:12 +00:00
Bill Wendling
05a4c0b1f2 Introducing the "linker_weak" linkage type. This will be used for Objective-C 
metadata types which should be marked as "weak", but which the linker will
remove upon final linkage. For example, the "objc_msgSend_fixup_alloc" symbol is
defined like this:

       .globl l_objc_msgSend_fixup_alloc
       .weak_definition l_objc_msgSend_fixup_alloc
       .section __DATA, __objc_msgrefs, coalesced
       .align 3
l_objc_msgSend_fixup_alloc:
        .quad   _objc_msgSend_fixup
        .quad   L_OBJC_METH_VAR_NAME_1

This is different from the "linker_private" linkage type, because it can't have
the metadata defined with ".weak_definition".

llvm-svn: 107205
 2010-06-29 21:24:00 +00:00
Bruno Cardoso Lopes
e1b05180de Add AVX ld/st XCSR register. 
Add VEX encoding bits for MRMXm x86 form

llvm-svn: 107204
 2010-06-29 20:35:48 +00:00
Bob Wilson
1b4210315e Add support for encoding VDUP (ARM core register) instructions. 
llvm-svn: 107201
 2010-06-29 20:13:29 +00:00
Bruno Cardoso Lopes
e60533aa42 Add AVX non-temporal stores 
llvm-svn: 107178
 2010-06-29 18:22:01 +00:00
Bruno Cardoso Lopes
4731169504 Move non-temporal movs to their own section 
llvm-svn: 107168
 2010-06-29 17:42:37 +00:00
Bob Wilson
be81c92b41 Add support for encoding NEON VMOV (from core register to scalar) instructions. 
The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.

llvm-svn: 107167
 2010-06-29 17:34:07 +00:00
Bruno Cardoso Lopes
2dca1dd168 Add sqrt, rsqrt and rcp AVX instructions 
llvm-svn: 107166
 2010-06-29 17:26:30 +00:00
Jim Grosbach
151bec3c2d skip dbg_value instructions 
llvm-svn: 107154
 2010-06-29 16:55:24 +00:00
Bob Wilson
74996289e3 The t2MOVi16 and t2MOVTi16 instructions do not set CPSR. Trying to add 
a CPSR operand to them causes an assertion failure, so apparently these
instructions haven't been getting a lot of use.

llvm-svn: 107147
 2010-06-29 16:25:11 +00:00
Rafael Espindola
832e4ddde7 Add a VT argument to getMinimalPhysRegClass and replace the copy related uses 
of getPhysicalRegisterRegClass with it.

If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.

llvm-svn: 107140
 2010-06-29 14:02:34 +00:00
Duncan Sands
1a45e3dbce Remove pointless variable LastDef. 
llvm-svn: 107135
 2010-06-29 13:23:22 +00:00
Duncan Sands
9eff796264 Remove unused variable Loc and pointless variables unified_syntax 
and thumb_mode.

llvm-svn: 107133
 2010-06-29 13:04:35 +00:00
Duncan Sands
25a2d02c5c Remove an unused and a pointless variable. 
llvm-svn: 107131
 2010-06-29 13:00:29 +00:00
Duncan Sands
aecd43c04e Remove pointless and unused variables. 
llvm-svn: 107130
 2010-06-29 12:48:49 +00:00
Duncan Sands
b955b3bf92 Remove initialized but otherwise unused variables. 
llvm-svn: 107127
 2010-06-29 11:22:26 +00:00
Evan Cheng
6349fa5ec4 PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas. 
llvm-svn: 107122
 2010-06-29 05:38:36 +00:00
Evan Cheng
9883684f03 Change if-cvt options to something that actually as useable. 
llvm-svn: 107121
 2010-06-29 05:37:59 +00:00
Bruno Cardoso Lopes
1fe3ed0e67 Refactoring of arithmetic instruction classes with unary operator 
llvm-svn: 107116
 2010-06-29 01:33:09 +00:00
Jakob Stoklund Olesen
b72b136170 When no memoperands are present, assume unaligned, volatile. 
llvm-svn: 107114
 2010-06-29 01:13:07 +00:00
Bruno Cardoso Lopes
e4809f15bf Described the missing AVX forms of SSE2 convert instructions 
llvm-svn: 107108
 2010-06-29 00:36:02 +00:00
Bob Wilson
2a4e6d0e34 Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding is 
the same as ARM except that the condition code field is always set to ARMCC::AL.

llvm-svn: 107107
 2010-06-29 00:26:13 +00:00
Bob Wilson
aee90dacaa Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead 
of the Subtarget.

llvm-svn: 107086
 2010-06-28 22:23:17 +00:00
Jim Grosbach
8441e67098 tidy up style. no functional change. 
llvm-svn: 107073
 2010-06-28 21:29:17 +00:00
Bob Wilson
378395412f Refactor encoding function for NEON 1-register with modified immediate format. 
llvm-svn: 107070
 2010-06-28 21:16:30 +00:00
Bob Wilson
6385cb2386 Support Thumb mode encoding of NEON instructions. 
llvm-svn: 107068
 2010-06-28 21:12:19 +00:00
Bill Wendling
4fe5512827 Reduce indentation via early exit. NFC. 
llvm-svn: 107067
 2010-06-28 21:08:32 +00:00
Jim Grosbach
a0473aa51c minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. No functional change. 
llvm-svn: 106988
 2010-06-28 04:27:01 +00:00
Gabor Greif
8868af8702 use ArgOperand API 
llvm-svn: 106946
 2010-06-26 12:17:21 +00:00
Gabor Greif
1625cb2320 use ArgOperand API 
llvm-svn: 106945
 2010-06-26 12:09:10 +00:00
Gabor Greif
14814144af use ArgOperand API 
llvm-svn: 106944
 2010-06-26 11:51:52 +00:00
Eli Friedman
893ce468be Followup to r106770: actually generate SXTB and SXTH for sign-extensions. 
llvm-svn: 106940
 2010-06-26 04:36:50 +00:00
Bob Wilson
aff7e7c1cc Add support for encoding NEON VMOV (from scalar to core register) instructions. 
llvm-svn: 106938
 2010-06-26 04:07:15 +00:00
Evan Cheng
f222c09b61 It's now possible to run code placement pass for ARM. 
llvm-svn: 106935
 2010-06-26 01:52:05 +00:00
Jakob Stoklund Olesen
6dee31aa07 When creating X86 MUL8 and DIV8 instructions, make sure we don't produce 
CopyFromReg nodes for aliasing registers (AX and AL). This confuses the fast
register allocator.

Instead of CopyFromReg(AL), use ExtractSubReg(CopyFromReg(AX), sub_8bit).

This fixes PR7312.

llvm-svn: 106934
 2010-06-26 00:39:23 +00:00
Bob Wilson
a3b10d15f2 Renumber NEON instruction formats to be consecutive. 
llvm-svn: 106927
 2010-06-26 00:05:09 +00:00
Bob Wilson
b8eaf1ed72 Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm to 
"N..." instead of "NEON..." for consistency with the other NEON format names.

llvm-svn: 106921
 2010-06-25 23:56:05 +00:00
Bruno Cardoso Lopes
277fcdf1c1 Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions 
llvm-svn: 106917
 2010-06-25 23:47:23 +00:00
Bob Wilson
3ace799cfe Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats. 
Renumber MiscFrm to 25.

llvm-svn: 106916
 2010-06-25 23:45:37 +00:00
Bruno Cardoso Lopes
45109dd6c1 Reapply r106896: 
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg

llvm-svn: 106912
 2010-06-25 23:33:42 +00:00
Daniel Dunbar
c0c37cea64 Thumb2ITBlockPass: Fix a possible dereference of an invalid iterator. This was 
introduced in r106343, but only showed up recently (with a particular compiler &
linker combination) because of the particular check, and because we have no
builtin checking for dereferencing the end of an array, which is truly
unfortunate.

llvm-svn: 106908
 2010-06-25 23:14:54 +00:00
Bruno Cardoso Lopes
cc4c01f859 revert this now, it's using avx instead of sse :) 
llvm-svn: 106906
 2010-06-25 23:04:29 +00:00
Evan Cheng
346aecdb8b Change if-conversion block size limit checks to add some flexibility. 
llvm-svn: 106901
 2010-06-25 22:42:03 +00:00
Bob Wilson
d1e4e67954 Add support for encoding 3-register NEON instructions, and fix 
emitNEON2RegInstruction's handling of 2-address operands.

llvm-svn: 106900
 2010-06-25 22:40:46 +00:00
Bruno Cardoso Lopes
04ac570a8d Add several AVX MOV flavors 
Support VEX encoding for MRMDestReg

llvm-svn: 106896
 2010-06-25 22:27:51 +00:00
Dale Johannesen
b1fc776fca The hasMemory argument is irrelevant to how the argument 
for an "i" constraint should get lowered; PR 6309.  While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.

llvm-svn: 106893
 2010-06-25 21:55:36 +00:00
Bob Wilson
a1739048a1 Add support for encoding 2-register NEON instructions. 
llvm-svn: 106891
 2010-06-25 21:17:19 +00:00
Dan Gohman
388f198fe5 pcmpeqd and friends are Commutable. 
llvm-svn: 106886
 2010-06-25 21:05:35 +00:00
Bob Wilson
4d54e03068 Fix indentation. 
llvm-svn: 106881
 2010-06-25 20:54:44 +00:00
Bill Wendling
3f9cb6828a - Reapply r106066 now that the bzip2 build regression has been fixed. 
- 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878.

llvm-svn: 106880
 2010-06-25 20:48:10 +00:00
Bruno Cardoso Lopes
72ca75e10f Move the last piece of SSE2 convert instructions to the Convert Instructions section 
llvm-svn: 106877
 2010-06-25 20:29:27 +00:00
Bruno Cardoso Lopes
fc7bfafe52 More SSE refactoring, this time with different types of MOVs 
llvm-svn: 106876
 2010-06-25 20:22:12 +00:00
Jim Grosbach
584fae6cc4 IT instructions are considered to be scheduling hazards, but are scheduled 
with the following instructions. This is done via trickery by considering the
instruction preceding the IT to be the hazard. Care must be taken to ensure
it's the first non-debug instruction, or the presence of debug info will
affect codegen.

Part of the continuing work for rdar://7797940, making ARM code-gen unaffected
by the presence of debug information.

llvm-svn: 106871
 2010-06-25 18:43:14 +00:00
Bruno Cardoso Lopes
0db2df31f4 Refactoring of more SSE conversion instructions. Also add some AVX instrinsics Int_V... placeholders 
llvm-svn: 106867
 2010-06-25 18:06:22 +00:00
Bob Wilson
a779332a5e Add missing ARM and Thumb data layout info for vector types. 
Radar 8128745.

llvm-svn: 106820
 2010-06-25 04:41:08 +00:00
Bob Wilson
0a84b9b677 Reduce indentation. 
llvm-svn: 106819
 2010-06-25 04:12:31 +00:00
Bruno Cardoso Lopes
bde2881855 Add some AVX convert instructions 
llvm-svn: 106815
 2010-06-25 00:39:30 +00:00
Bruno Cardoso Lopes
4663112339 Refactoring of SSE convert intrinsics 
llvm-svn: 106808
 2010-06-24 23:37:07 +00:00
Bruno Cardoso Lopes
bacc90a80d Refactoring of SSE conversion instructions 
llvm-svn: 106804
 2010-06-24 22:22:21 +00:00
Bruno Cardoso Lopes
84ce865fea Refactor SSE cmp intrinsics and declare the same for AVX 
llvm-svn: 106796
 2010-06-24 22:04:40 +00:00
Bruno Cardoso Lopes
11a236d970 - Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}. 
- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.

llvm-svn: 106787
 2010-06-24 20:48:23 +00:00
Dale Johannesen
257b602b8b Disallow matching "i" constraint to symbol addresses when 
address requires a register or secondary load to compute
(most PIC modes).  This improves "g" constraint handling.  8015842.

The test from 2007 is attempting to test the fix for PR1761,
but since -relocation-model=static doesn't work on Darwin
x86-64, it was not testing what it was supposed to be testing
and was passing erroneously.  Fixed to use Linux x86-64.

llvm-svn: 106779
 2010-06-24 20:14:51 +00:00
Evan Cheng
c3976de390 Oops. IT block formation pass needs to be run at any optimization level. 
llvm-svn: 106775
 2010-06-24 19:10:14 +00:00
Eli Friedman
0698ec53f6 Always allow Thumb-2 SXTB, SXTH, UXTB, and UXTH. Fixes PR7324. 
llvm-svn: 106770
 2010-06-24 18:20:04 +00:00
Bob Wilson
26297589b7 PR7458: Try commuting Thumb2 instruction operands to put them into 2-address 
form so they can be narrowed to 16-bit instructions.

llvm-svn: 106762
 2010-06-24 16:50:20 +00:00
Dan Gohman
a08a9b8a0b Reapply r106634, now that the bug it exposed is fixed. 
llvm-svn: 106746
 2010-06-24 14:30:44 +00:00
Chris Lattner
606dc0529b Teach the x86 mc assembler that %dr6 = %db6, this implements 
rdar://8013734

llvm-svn: 106725
 2010-06-24 07:29:18 +00:00
Chris Lattner
877cc43dbb more cleanups 
llvm-svn: 106724
 2010-06-24 07:18:14 +00:00
Chris Lattner
57b7692849 reduce indentation 
llvm-svn: 106723
 2010-06-24 07:16:25 +00:00
Chris Lattner
ec4bb143ef fix breakage from r98938 by correctly marking msp430 calls as variadic. 
Patch by Ben Ransford!

llvm-svn: 106722
 2010-06-24 06:46:50 +00:00
Dan Gohman
214ba7c014 Fix a bug in the code which determines when it's safe to use the 
bt instruction, which was exposed by r106263.

llvm-svn: 106718
 2010-06-24 02:07:59 +00:00
Eric Christopher
657b8b040e Add a couple more quick comments. 
llvm-svn: 106717
 2010-06-24 02:07:57 +00:00
Devang Patel
0c927a80fe Use ValueMap instead of DenseMap. 
The ValueMapper used by various cloning utility maps MDNodes also.

llvm-svn: 106706
 2010-06-24 00:33:28 +00:00
Bruno Cardoso Lopes
633f345ba9 Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases 
llvm-svn: 106705
 2010-06-24 00:32:06 +00:00
Bruno Cardoso Lopes
5aea735b46 Move SSE and AVX shuffle, unpack and compare code to more appropriate places 
llvm-svn: 106702
 2010-06-24 00:15:50 +00:00
Bill Wendling
777c025ad8 We are missing opportunites to use ldm. Take code like this: 
void t(int *cp0, int *cp1, int *dp, int fmd) {
  int c0, c1, d0, d1, d2, d3;
  c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
  c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
  /* ... */
}

It code gens into something pretty bad. But with this change (analogous to the
X86 back-end), it will use ldm and generate few instructions.

llvm-svn: 106693
 2010-06-23 23:00:16 +00:00
Bruno Cardoso Lopes
b1bfbacead Add AVX MOVMSK{PS,PD}rr instructions 
llvm-svn: 106683
 2010-06-23 21:30:27 +00:00
Bruno Cardoso Lopes
c6ac26123d Add tests for different AVX cmp opcodes, also teach the x86 asm parser to understand the vcmp instruction 
llvm-svn: 106678
 2010-06-23 21:10:57 +00:00
Eric Christopher
436ff8863f Update according to feedback. 
llvm-svn: 106677
 2010-06-23 20:49:35 +00:00
Bruno Cardoso Lopes
8cfdcf7691 Add AVX SHUF{PS,PD}{rr,rm} instructions 
llvm-svn: 106672
 2010-06-23 20:07:15 +00:00
Nico Weber
04606293a5 Add support for the x86 instructions "pusha" and "popa". 
llvm-svn: 106671
 2010-06-23 20:00:58 +00:00
Dale Johannesen
e618e80a13 Do not do tail calls to external symbols. If the 
branch turns out to be ARM-to-Thumb or vice versa
the linker cannot resolve this.  8120438.

If this optimization is going to be useful we probably
need a compiler flag "assume callees are same architecture"
or something like that.

llvm-svn: 106662
 2010-06-23 18:52:34 +00:00
Daniel Dunbar
be50ef88bd Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled. 
llvm-svn: 106634
 2010-06-23 17:09:26 +00:00
Jim Grosbach
ef4e0249a0 The generic DAG combiner can now fold atomic fences when needed, so switch 
to using that.

llvm-svn: 106633
 2010-06-23 16:25:07 +00:00
Jim Grosbach
414eb48a14 When using libcall expansions for the atomic intrinsics, the explicit 
MEMBARRIER fences aren't necessary for ARM. Tell the combiner to fold them
away.

llvm-svn: 106631
 2010-06-23 16:08:49 +00:00
Eric Christopher
c6382036ef Update uses, defs, and comments for darwin tls patterns. 
llvm-svn: 106621
 2010-06-23 08:01:49 +00:00
Daniel Dunbar
e6ee7409b9 Revert r106066, "Create a more targeted fix for not sinking instructions into a range where it"... it causes bzip2 to be miscompiled by Clang. 
Conflicts:

	lib/CodeGen/MachineSink.cpp

llvm-svn: 106614
 2010-06-23 00:48:25 +00:00
Bruno Cardoso Lopes
db9027d95d Add AVX compare packed instructions 
llvm-svn: 106600
 2010-06-22 23:37:59 +00:00
Bruno Cardoso Lopes
424b206ad4 Reapply support for AVX unpack and interleave instructions, with 
testcases this time.

llvm-svn: 106593
 2010-06-22 23:02:38 +00:00
Bruno Cardoso Lopes
93ec8dcd01 Add AVX MOV{SS,SD}{rr,rm} instructions 
llvm-svn: 106588
 2010-06-22 22:38:56 +00:00
Bill Wendling
c29fd1120a Fix the formatting of the switch statement and add a missing break. 
llvm-svn: 106586
 2010-06-22 22:16:17 +00:00
Bob Wilson
cb414cca8d Thumb1 functions using @llvm.returnaddress were not saving the incoming LR. 
Radar 8031193.

llvm-svn: 106582
 2010-06-22 22:04:24 +00:00
Jim Grosbach
69e4d59ce5 fix typo 
llvm-svn: 106574
 2010-06-22 20:52:02 +00:00
Bruno Cardoso Lopes
2cf78d18d5 Reorganize logical and arithmetic SSE 1 & 2 instructions 
llvm-svn: 106557
 2010-06-22 18:17:40 +00:00
Bruno Cardoso Lopes
22aca94946 Reorganize SSE instructions, making easier to see oportunities for refactoring 
llvm-svn: 106556
 2010-06-22 18:09:32 +00:00
Dan Gohman
74d5144414 Use pre-increment instead of post-increment when the result is not used. 
llvm-svn: 106542
 2010-06-22 15:08:57 +00:00
Evan Cheng
a1ebf91a39 Tail merging pass shall not break up IT blocks. rdar://8115404 
llvm-svn: 106517
 2010-06-22 01:18:16 +00:00
Chris Lattner
3de7445da3 make sure to initialize indent_level 
llvm-svn: 106513
 2010-06-22 00:40:26 +00:00
Chris Lattner
6be03758e4 add some support for blockaddress. This isn't really enough to be useful, 
but it will cover uses of blockaddress that are actually in a function.

llvm-svn: 106502
 2010-06-21 23:19:36 +00:00
Chris Lattner
1d76d7e9b2 eliminate a mutable global variable, use raw_ostream::indent instead of 
rolling our own.

llvm-svn: 106501
 2010-06-21 23:14:47 +00:00
Chris Lattner
580470b914 un-indent a huge amount of code out of an anonymous namespace. 
llvm-svn: 106500
 2010-06-21 23:12:56 +00:00
Bruno Cardoso Lopes
d4d53fdb7f revert r106482 
llvm-svn: 106499
 2010-06-21 22:59:03 +00:00
Bruno Cardoso Lopes
33256723a7 change parameter name to avoid confusion with global definition 
llvm-svn: 106486
 2010-06-21 21:28:07 +00:00
Bob Wilson
ef565a2ffd sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM. 
Radar 8104310.

llvm-svn: 106484
 2010-06-21 21:27:34 +00:00
Jim Grosbach
bc31f7a24b LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it 
being moved around away from the jump table it references. rdar://8104340

llvm-svn: 106483
 2010-06-21 21:27:27 +00:00
Bruno Cardoso Lopes
40debaf4b8 Add unpack and interleave AVX instructions, encoding tests cooming soon 
llvm-svn: 106482
 2010-06-21 21:21:48 +00:00
Evan Cheng
167a8655c7 Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed. 
llvm-svn: 106481
 2010-06-21 21:21:14 +00:00
Eric Christopher
318243d2c6 Remove isTwoAddress from SystemZ. 
llvm-svn: 106467
 2010-06-21 20:25:57 +00:00
Eric Christopher
5b757ab002 Remove isTwoAddress from Sparc. 
llvm-svn: 106466
 2010-06-21 20:22:35 +00:00
Eric Christopher
caf8285bff Remove isTwoAddress from Mips. 
llvm-svn: 106465
 2010-06-21 20:19:21 +00:00
Eric Christopher
109380247d Remove isTwoAddress from Blackfin. 
llvm-svn: 106457
 2010-06-21 20:13:37 +00:00
Eric Christopher
4173fa9514 Remove isTwoAddress from MSP430. 
llvm-svn: 106455
 2010-06-21 20:07:30 +00:00
Eric Christopher
27afc6b948 Make 80-column. 
llvm-svn: 106448
 2010-06-21 18:56:55 +00:00
Eric Christopher
22c623f01c Remove isTwoAddress from PIC16. 
llvm-svn: 106447
 2010-06-21 18:55:01 +00:00
Eric Christopher
2dae43dbe4 Remove isTwoAddress from XCore. 
llvm-svn: 106446
 2010-06-21 18:51:38 +00:00
Eric Christopher
f0e2a62b21 Remove isTwoAddress from Alpha. 
llvm-svn: 106445
 2010-06-21 18:48:55 +00:00
Bruno Cardoso Lopes
24af70c17f Move part of SSE 1 & 2 compare, shuffle and unpack instructions closely. Preparing them for refactoring and to the addition of their AVX forms 
llvm-svn: 106437
 2010-06-21 18:36:04 +00:00
Bruno Cardoso Lopes
aff9b1c52f Add AVX regular (non-aliased ones) and,or,xor,andn packed instructions. They are already tested in the MC framework, no test needed 
llvm-svn: 106436
 2010-06-21 18:22:54 +00:00
Dale Johannesen
ef3db5dea3 Fix PR 7433. Silly typo in non-Darwin ARM tail call 
handling, plus correct R9 handling in that mode.

llvm-svn: 106434
 2010-06-21 18:21:49 +00:00
Eric Christopher
8909d46ea2 Add some codegen patterns for x86_64-linux-gnu tls codegen matching. 
Based on a patch by Patrick Marlier!

llvm-svn: 106433
 2010-06-21 18:21:27 +00:00
Jim Grosbach
e35d35fd0a early exit for dbg_value instructions 
llvm-svn: 106430
 2010-06-21 17:49:23 +00:00
Chris Lattner
02b23bfd33 remove some dead variables reported by clang++ 
llvm-svn: 106428
 2010-06-21 17:20:18 +00:00
Kalle Raiskila
2001fd19b9 Mark the SPU 'lr' instruction to never have side effects. 
This allows the fast regiser allocator to remove redundant 
register moves.
Update a set of tests that depend on the register allocator
to be linear scan. 

llvm-svn: 106420
 2010-06-21 15:08:16 +00:00
Kalle Raiskila
cbd0b7c43b Fix the lowering of VECTOR_SHUFFLE on SPU to handle splats. 
llvm-svn: 106419
 2010-06-21 14:42:19 +00:00
Rafael Espindola
5e123a1745 Fix an unintentional commit. I think I typed "git svn dcommit" in the wrong branch. 
I was trying to do some refactoring on the copyRegToReg, but this is realyl a work in progress and not generally useful yet.

llvm-svn: 106413
 2010-06-21 13:31:32 +00:00
Kalle Raiskila
a30e45e2d3 Fix lowering of VECTOR_SHUFFLE on SPU. Old algorithm 
used to choke llc with the attached test.
 

llvm-svn: 106411
 2010-06-21 10:17:36 +00:00
Rafael Espindola
84260ed15a wip 
llvm-svn: 106408
 2010-06-21 02:17:34 +00:00
Nick Lewycky
059e327790 Fix warning in no-asserts build. 
llvm-svn: 106405
 2010-06-20 20:27:42 +00:00
Evan Cheng
c18fbafa74 Fix a crash caused by dereference of MBB.end(). rdar://8110842 
llvm-svn: 106399
 2010-06-20 00:54:38 +00:00
Bob Wilson
059880161b Remove a fixme comment that is no longer relevant. 
llvm-svn: 106382
 2010-06-19 05:32:41 +00:00
Bob Wilson
44afe2065d Fix error message to match function name. 
llvm-svn: 106381
 2010-06-19 05:32:09 +00:00
Bruno Cardoso Lopes
0403eaadce Refactoring of regular logical packed instructions to prepare for AVX ones. 
llvm-svn: 106375
 2010-06-19 04:09:22 +00:00
Bruno Cardoso Lopes
c41dfa7cad Refactor aliased packed logical instructions, also add 
AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.

llvm-svn: 106374
 2010-06-19 02:44:01 +00:00
Evan Cheng
142feca0de Ignore dbg_value's. 
llvm-svn: 106373
 2010-06-19 02:36:21 +00:00
Bruno Cardoso Lopes
4e76c6a522 Move new sse 1 & 2 generic classes to a more appropriate place 
llvm-svn: 106372
 2010-06-19 01:32:46 +00:00
Bruno Cardoso Lopes
962d79ed72 Remove unnecessary arguments 
llvm-svn: 106371
 2010-06-19 01:22:34 +00:00
Bruno Cardoso Lopes
2ca4dde535 Add AVX packed intrinsics for MIN, MAX 
llvm-svn: 106370
 2010-06-19 01:17:05 +00:00
Evan Cheng
f40b8f0e32 Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them. 
llvm-svn: 106368
 2010-06-19 01:01:32 +00:00
Eric Christopher
b6dfc01862 Finish ripping isTwoAddress out of X86. Some mindless formatting 
and operand renaming to help.

The giant turn the constraints on and selectively turn it off
should probably be inverted at some point since it's just largely
50/50.

llvm-svn: 106367
 2010-06-19 00:37:40 +00:00
Bruno Cardoso Lopes
d6d12f37c6 Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions 
llvm-svn: 106366
 2010-06-19 00:37:31 +00:00
Chris Lattner
def4def8f9 rip out dead code. 
llvm-svn: 106365
 2010-06-19 00:34:14 +00:00
Chris Lattner
ed5a217085 fix rdar://7873482 by teaching the instruction encoder to emit 
segment prefixes.  Daniel wrote most of this patch.

llvm-svn: 106364
 2010-06-19 00:34:00 +00:00
Evan Cheng
604fd85b52 Indentation and remove dead code. 
llvm-svn: 106362
 2010-06-19 00:11:54 +00:00
Bruno Cardoso Lopes
018fd49970 Clean up: remove now unnecessary Constraints 
llvm-svn: 106361
 2010-06-19 00:09:27 +00:00
Dan Gohman
8f0bc55ea5 Silence compiler warnings. 
llvm-svn: 106360
 2010-06-19 00:02:06 +00:00
Bruno Cardoso Lopes
c016e11c53 more refactoring! yay! big win over the intrinsics 
llvm-svn: 106359
 2010-06-19 00:00:22 +00:00
Eric Christopher
e0cc8e131e Remove isTwoAddress from here too. 
llvm-svn: 106358
 2010-06-18 23:56:07 +00:00
Bruno Cardoso Lopes
5af812b35b Fix typo, SSE1 should be used by XS, not SSE2 
llvm-svn: 106357
 2010-06-18 23:53:27 +00:00
Eric Christopher
10fa91df80 Remove isTwoAddress from 64-bit files. 
llvm-svn: 106356
 2010-06-18 23:51:21 +00:00
Evan Cheng
e9ba3241a3 Move ARM if-conversion before post-ra scheduling. 
llvm-svn: 106355
 2010-06-18 23:32:07 +00:00
Dan Gohman
823dff64cd Teach regular and fast isel to set dead flags on unused implicit defs 
on calls and similar instructions.

llvm-svn: 106353
 2010-06-18 23:28:01 +00:00