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2942 Commits

Author SHA1 Message Date
Bill Wendling
7e9607ab56 Don't assign the shift the same type as the variable being shifted. This could 
result in illegal types for the SHL operator.

llvm-svn: 92797
 2010-01-05 22:39:10 +00:00
Dan Gohman
5fa04f2707 Delete useless trailing semicolons. 
llvm-svn: 92740
 2010-01-05 17:55:26 +00:00
Dan Gohman
73b0882c6e Make this test more portable. 
llvm-svn: 92514
 2010-01-04 21:23:34 +00:00
Dan Gohman
b71bc40eed Add some tests and update an existing test to reflect recent 
x86 isel peeps.

llvm-svn: 92509
 2010-01-04 20:53:54 +00:00
Anton Korobeynikov
3915cf5ef4 Fix invalid chain folding for memory variant of sdiv / udiv 
llvm-svn: 92472
 2010-01-04 10:31:54 +00:00
Chris Lattner
8e83066d12 fix PR5930, allowing the asmprinter to emit difference between 
two labels as a truncate.

llvm-svn: 92455
 2010-01-03 18:33:18 +00:00
Chris Lattner
49cda26f7e add PR# 
llvm-svn: 92451
 2010-01-03 18:10:58 +00:00
Chris Lattner
7246a69d2b differences between two blockaddress's don't cause a 
global variable initializer to require relocations.

llvm-svn: 92450
 2010-01-03 18:09:40 +00:00
Chris Lattner
9e64bad0da allow this to work on linux hosts. 
llvm-svn: 92407
 2010-01-02 00:22:15 +00:00
Chris Lattner
fe8af82cd4 Teach codegen to handle: 
(X != null) | (Y != null) --> (X|Y) != 0
 (X == null) & (Y == null) --> (X|Y) == 0

so that instcombine can stop doing this for pointers.  This is part of PR3351,
which is a case where instcombine doing this for pointers (inserting ptrtoint)
is pessimizing code.

llvm-svn: 92406
 2010-01-02 00:00:03 +00:00
Chris Lattner
4e49a69ec5 rename file. 
llvm-svn: 92405
 2010-01-01 23:55:04 +00:00
Chris Lattner
44298d184a Teach codegen to lower llvm.powi to an efficient (but not optimal) 
multiply sequence when the power is a constant integer.  Before, our
codegen for std::pow(.., int) always turned into a libcall, which was
really inefficient.

This should also make many gfortran programs happier I'd imagine.

llvm-svn: 92388
 2010-01-01 03:32:16 +00:00
Chris Lattner
3d38dbff2a Make this more likely to generate a libcall. 
llvm-svn: 92387
 2010-01-01 03:26:51 +00:00
Sanjiv Gupta
543a6716fb Extern declaration for unordered.f32 libcall was not being emitted. Fixed that. 
llvm-svn: 92242
 2009-12-29 03:24:34 +00:00
Sanjiv Gupta
efad5b2a93 Fixed llc crash for zext (i1 -> i8) loads. 
llvm-svn: 92201
 2009-12-28 04:53:24 +00:00
Chris Lattner
4e96d36f72 handle equality memcmp of 8 bytes on x86-64 with two unaligned loads and a 
compare.  On other targets we end up with a call to memcmp because we don't
want 16 individual byte loads.  We should be able to use movups as well, but
we're failing to select the generated icmp.

llvm-svn: 92107
 2009-12-24 01:07:17 +00:00
Chris Lattner
5d3919d5f9 move an optimization for memcmp out of simplifylibcalls and into 
SDISel.  This optimization was causing simplifylibcalls to 
introduce type-unsafe nastiness.  This is the first step, I'll be 
expanding the memcmp optimizations shortly, covering things that
we really really wouldn't want simplifylibcalls to do.

llvm-svn: 92098
 2009-12-24 00:37:38 +00:00
Sanjiv Gupta
7872817f59 Reapply 91904. 
llvm-svn: 91996
 2009-12-23 11:19:09 +00:00
Sanjiv Gupta
1cd15ef29f deleting empty file. 
llvm-svn: 91994
 2009-12-23 10:35:24 +00:00
Sanjiv Gupta
70e1523215 Reverting back 91904. 
llvm-svn: 91993
 2009-12-23 09:46:01 +00:00
Dale Johannesen
b4485fd8a9 Use more sensible type for flags in asms. PR 5570. 
Patch by Sylve`re Teissier (sorry, ASCII only).

llvm-svn: 91988
 2009-12-23 07:32:51 +00:00
Eric Christopher
ce677a909d Update objectsize intrinsic and associated dependencies. Fix 
lowering code and update testcases.

llvm-svn: 91979
 2009-12-23 02:51:48 +00:00
Anton Korobeynikov
04878d43e1 Add testcase for PR5703 
llvm-svn: 91931
 2009-12-22 22:37:23 +00:00
Evan Cheng
7cd6bfe549 Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size. 
llvm-svn: 91910
 2009-12-22 17:47:23 +00:00
Sanjiv Gupta
9581b4dc62 While converting one of the operands to a memory operand, we need to check if it is Legal and does not result into a cyclic dep. 
llvm-svn: 91904
 2009-12-22 14:25:37 +00:00
Sanjiv Gupta
14c9f2ed42 Emit direction operand in binary insns that stores in memory. 
llvm-svn: 91777
 2009-12-19 13:52:01 +00:00
Sanjiv Gupta
df6eadc436 Test cases for changes done in 91768. 
llvm-svn: 91773
 2009-12-19 11:38:14 +00:00
Evan Cheng
bc37151dea Increase opportunities to optimize (brcond (srl (and c1), c2)). 
llvm-svn: 91717
 2009-12-18 21:31:31 +00:00
Evan Cheng
d97d025eba On recent Intel u-arch's, folding loads into some unary SSE instructions can 
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.

movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0

instead of
cvtss2sd (%rdi), %xmm0

An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0

llvm-svn: 91672
 2009-12-18 07:40:29 +00:00
Dan Gohman
d97f165eb2 Tidy up this testcase and add test for tailcall optimization 
with unreachable.

llvm-svn: 91650
 2009-12-18 01:05:06 +00:00
Bob Wilson
a9f20f9f6e Handle ARM inline asm "w" constraints with 64-bit ("d") registers. 
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types.  Radar 7457110.

llvm-svn: 91649
 2009-12-18 01:03:29 +00:00
Dan Gohman
c382d6519c Remove "tail" keywords. These calls are not intended to be tail calls. 
This protects this test from depending on codegen not performing the
tail call optimization by default.

llvm-svn: 91648
 2009-12-18 01:02:18 +00:00
Jakob Stoklund Olesen
b39930cf6d Add test case for the phi reuse patch. 
llvm-svn: 91642
 2009-12-18 00:11:44 +00:00
Sean Callanan
06b6feb2e1 Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier

llvm-svn: 91638
 2009-12-18 00:01:26 +00:00
Evan Cheng
dbd8789125 Revert this dag combine change: 
Fold (zext (and x, cst)) -> (and (zext x), cst)

DAG combiner likes to optimize expression in the other way so this would end up cause an infinite looping.

llvm-svn: 91574
 2009-12-17 00:40:05 +00:00
Nick Lewycky
503ef79cc5 Make this test pass on Linux. 
llvm-svn: 91521
 2009-12-16 07:35:25 +00:00
Evan Cheng
aaf2f58a04 Re-enable 91381 with fixes. 
llvm-svn: 91489
 2009-12-16 00:53:11 +00:00
Dale Johannesen
365ae431a7 Do better with physical reg operands (typically, from inline asm) 
in local register allocator.  If a reg-reg copy has a phys reg
input and a virt reg output, and this is the last use of the phys
reg, assign the phys reg to the virt reg.  If a reg-reg copy has
a phys reg output and we need to reload its spilled input, reload
it directly into the phys reg than passing it through another reg.

Following 76208, there is sometimes no dependency between the def of
a phys reg and its use; this creates a window where that phys reg
can be used for spilling (this is true in linear scan also).  This
is bad and needs to be fixed a better way, although 76208 works too
well in practice to be reverted.  However, there should normally be
no spilling within inline asm blocks.  The patch here goes a long way
towards making this actually be true.

llvm-svn: 91485
 2009-12-16 00:29:41 +00:00
Kenneth Uildriks
c0ab5a6e88 For fastcc on x86, let ECX be used as a return register after EAX and EDX 
llvm-svn: 91410
 2009-12-15 03:27:52 +00:00
Evan Cheng
4adb4acc7b Disable 91381 for now. It's miscompiling ARMISelDAG2DAG.cpp. 
llvm-svn: 91405
 2009-12-15 03:07:11 +00:00
Evan Cheng
c531da60aa Make 91378 more conservative. 
1. Only perform (zext (shl (zext x), y)) -> (shl (zext x), y) when y is a constant. This makes sure it remove at least one zest.
2. If the shift is a left shift, make sure the original shift cannot shift out bits.

llvm-svn: 91399
 2009-12-15 03:00:32 +00:00
Evan Cheng
cd8f0de016 Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's. 
llvm-svn: 91381
 2009-12-15 00:53:42 +00:00
Evan Cheng
bd48ad16fa Fold (zext (and x, cst)) -> (and (zext x), cst). 
llvm-svn: 91380
 2009-12-15 00:52:11 +00:00
Evan Cheng
f3b2e55b34 Propagate zest through logical shift. 
llvm-svn: 91378
 2009-12-15 00:41:36 +00:00
Dan Gohman
57dc006590 Fix integer cast code to handle vector types. 
llvm-svn: 91362
 2009-12-14 23:40:38 +00:00
Evan Cheng
ee5b5917fd Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit. 
llvm-svn: 91223
 2009-12-12 20:03:14 +00:00
Anton Korobeynikov
724c82337f Lower setcc branchless, if this is profitable. 
Based on the patch by Brian Lucas!

llvm-svn: 91175
 2009-12-11 23:01:29 +00:00
Dan Gohman
2e616e859b Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG. 
llvm-svn: 91158
 2009-12-11 21:31:27 +00:00
Dan Gohman
0a78e32f6b Change this to the correct PR number. 
llvm-svn: 91148
 2009-12-11 20:09:21 +00:00
Dan Gohman
b2cbb1e37e Fix the result type of SELECT nodes lowered from Select instructions with 
aggregate return values. This fixes PR5754.

llvm-svn: 91145
 2009-12-11 19:50:50 +00:00
Anton Korobeynikov
f8b2e2868e Honour setHasCalls() set from isel. 
This is used in some weird cases like general dynamic TLS model.
This fixes PR5723

llvm-svn: 91144
 2009-12-11 19:39:55 +00:00
Evan Cheng
4c304eebe9 Tests for 91103 and 91104. 
llvm-svn: 91105
 2009-12-11 06:02:21 +00:00
Evan Cheng
4b7cf3ed41 It's not safe to coalesce a move where src and dst registers have different subregister indices. e.g.: 
%reg16404:1<def> = MOV8rr %reg16412:2<kill>

llvm-svn: 91061
 2009-12-10 20:59:45 +00:00
Evan Cheng
bc633478bd Fix test. 
llvm-svn: 90988
 2009-12-09 22:24:42 +00:00
Evan Cheng
9e2442c0be Optimize splat of a scalar load into a shuffle of a vector load when it's legal. e.g. 
vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0>
=>
vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1>

iff ptr is 16-byte aligned (or can be made into 16-byte aligned).

llvm-svn: 90984
 2009-12-09 21:00:30 +00:00
Evan Cheng
41c13e41fe Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 isl lowering code. 
llvm-svn: 90925
 2009-12-09 01:53:58 +00:00
Evan Cheng
edcc21919f - Support inline asm 'w' constraint for 128-bit vector types. 
- Also support the 'q' NEON registers asm code.

llvm-svn: 90894
 2009-12-08 23:06:22 +00:00
Anton Korobeynikov
0ace515a4c Reduce (cmp 0, and_su (foo, bar)) into (bit foo, bar). This saves extra instruction. Patch inspired by Brian Lucas! 
llvm-svn: 90819
 2009-12-08 01:03:04 +00:00
David Greene
73ad44c6b6 Use FileCheck and set nounwind on calls. 
llvm-svn: 90790
 2009-12-07 19:40:26 +00:00
Dan Gohman
44e25ed254 Don't enable the post-RA scheduler on x86 except at -O3. In its 
current form, it is too expensive in compile time.

llvm-svn: 90781
 2009-12-07 19:04:31 +00:00
Anton Korobeynikov
eee906f4f0 Dynamic stack realignment use of sp register as source/dest register 
in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4

llvm-svn: 90724
 2009-12-06 22:39:50 +00:00
Bill Wendling
887646a585 Temporarily revert r90502. It was causing the llvm-gcc bootstrap on PPC to fail. 
llvm-svn: 90653
 2009-12-05 07:30:23 +00:00
Jakob Stoklund Olesen
7c5af26d12 Also attempt trivial coalescing for live intervals that end in a copy. 
The coalescer is supposed to clean these up, but when setting up parameters
for a function call, there may be copies to physregs. If the defining
instruction has been LICM'ed far away, the coalescer won't touch it.

The register allocation hint does not always work - when the register
allocator is backtracking, it clears the hints.

This patch takes care of a few more cases that r90163 missed.

llvm-svn: 90502
 2009-12-04 00:16:04 +00:00
Nate Begeman
3a9c51f256 Don't pull vector sext through both hands of a logical operation, since doing so prevents the fusion of vector sext and setcc into vsetcc. 
Add a testcase for the above transformation.
Fix a bogus use of APInt noticed while tracking this down.

llvm-svn: 90423
 2009-12-03 07:11:29 +00:00
Bob Wilson
b53c801366 Recognize canonical forms of vector shuffles where the same vector is used for 
both source operands.  In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand.  Radar 7434842.

llvm-svn: 90417
 2009-12-03 06:40:55 +00:00
Bill Wendling
0eb481a249 Remove unnecessary check. 
llvm-svn: 90352
 2009-12-02 22:02:20 +00:00
Evan Cheng
0c687845b1 Fix PR5391: support early clobber physical register def tied with a use (ewwww) 
- A valno should be set HasRedefByEC if there is an early clobber def in the middle of its live ranges. It should not be set if the def of the valno is defined by an early clobber.
- If a physical register def is tied to an use and it's an early clobber, it just means the HasRedefByEC is set since it's still one continuous live range.
- Add a couple of missing checks for HasRedefByEC in the coalescer. In general, it should not coalesce a vr with a physical register if the physical register has a early clobber def somewhere. This is overly conservative but that's the price for using such a nasty inline asm "feature".

llvm-svn: 90269
 2009-12-01 22:25:00 +00:00
Jim Grosbach
7688d320c9 test case for IV-Users simplification loop improvement 
llvm-svn: 90260
 2009-12-01 21:53:51 +00:00
Jakob Stoklund Olesen
f07d6129a2 Use CFG connectedness as a secondary sort key when deciding the order of copy coalescing. 
This means that well connected blocks are copy coalesced before the less connected blocks. Connected blocks are more difficult to
coalesce because intervals are more complicated, so handling them first gives a greater chance of success.

llvm-svn: 90194
 2009-12-01 03:03:00 +00:00
Evan Cheng
fcbc30f36e Fix PR5614: parts of a physical register def may be killed the rest. 
llvm-svn: 90180
 2009-12-01 00:44:45 +00:00
Jakob Stoklund Olesen
ce2743a619 New virtual registers created for spill intervals should inherit allocation hints from the original register. 
This helps us avoid silly copies when rematting values that are copied to a physical register:

leaq	_.str44(%rip), %rcx
movq	%rcx, %rsi
call	_strcmp

becomes:

leaq	_.str44(%rip), %rsi
call	_strcmp

The coalescer will not touch the movq because that would tie down the physical register.

llvm-svn: 90163
 2009-11-30 22:55:54 +00:00
Mon P Wang
22b4e4e223 Add test case for r90108 
llvm-svn: 90109
 2009-11-30 02:42:27 +00:00
Duncan Sands
638c57757d While this test is testing a problem in the generic part of codegen, 
the problem only shows for msp430 and pic16 which is why it specifies
them using -march.  But it is wrong to put such tests in CodeGen/Generic,
since not everyone builds these targets.  Put a copy of the test in each
of the target test directories.

llvm-svn: 90005
 2009-11-27 16:04:14 +00:00
Evan Cheng
dd352c2a81 Test for 89905. 
llvm-svn: 89906
 2009-11-26 00:35:01 +00:00
Evan Cheng
bdedf32e51 ProcessImplicitDefs should watch out for invalidated iterator and extra implicit operands on copies. 
llvm-svn: 89880
 2009-11-25 21:13:39 +00:00
Bruno Cardoso Lopes
038281c523 Support PIC loading of constant pool entries 
llvm-svn: 89863
 2009-11-25 12:17:58 +00:00
Dale Johannesen
5809ff0e58 Do not store R31 into the caller's link area on PPC. 
This violates the ABI (that area is "reserved"), and
while it is safe if all code is generated with current
compilers, there is some very old code around that uses
that slot for something else, and breaks if it is stored
into.  Adjust testcases looking for current behavior.
I've verified that the stack frame size is right in all
testcases, whether it changed or not.  7311323.

llvm-svn: 89811
 2009-11-24 22:59:02 +00:00
Evan Cheng
b81878ed80 Enable predication of NEON instructions in Thumb2 mode. 
llvm-svn: 89748
 2009-11-24 08:06:15 +00:00
Anton Korobeynikov
0f885eb7fd Materialize global addresses via movt/movw pair, this is always better 
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

llvm-svn: 89720
 2009-11-24 00:44:37 +00:00
Jim Grosbach
76b545e988 move fconst[sd] to UAL. <rdar://7414913> 
llvm-svn: 89700
 2009-11-23 21:08:25 +00:00
Jim Grosbach
b7607ee5fe update test for 89694 
llvm-svn: 89695
 2009-11-23 20:39:53 +00:00
Edward O'Callaghan
573a04cfbb Miss two, PR5307. 
llvm-svn: 89596
 2009-11-22 15:35:28 +00:00
Edward O'Callaghan
a295e7bd9b Convert Thumb2 tests to FileCheck for PR5307. 
llvm-svn: 89595
 2009-11-22 15:18:27 +00:00
Benjamin Kramer
7968de0cde Turns out stuff gets allocated to different registers depending on the subtarget. 
llvm-svn: 89594
 2009-11-22 15:15:52 +00:00
Edward O'Callaghan
d1c7b40bb5 Convert ARM tests to FileCheck for PR5307. 
llvm-svn: 89593
 2009-11-22 14:23:33 +00:00
Benjamin Kramer
a08534a88d Convert test to FileCheck. 
llvm-svn: 89589
 2009-11-22 13:16:36 +00:00
Edward O'Callaghan
1a250b4109 Forgot to alter RUN line when converting to FileCheck. 
llvm-svn: 89588
 2009-11-22 13:09:48 +00:00
Edward O'Callaghan
5ae4559914 Fix for bad FileCheck converts in revision 89584. 
llvm-svn: 89586
 2009-11-22 12:50:05 +00:00
Edward O'Callaghan
949850890f Convert a few tests to FileCheck for PR5307. 
llvm-svn: 89584
 2009-11-22 11:45:44 +00:00
Jim Grosbach
99c5b49c61 Revert 89562. We're being sneakier than I was giving us credit for, and this 
isn't necessary.

llvm-svn: 89568
 2009-11-21 23:34:09 +00:00
Jim Grosbach
d4603a5c4e Darwin requires a frame pointer for all non-leaf functions to support correct 
backtraces.

llvm-svn: 89562
 2009-11-21 21:40:08 +00:00
Jakob Stoklund Olesen
78f465dc49 Don't leave temporary files in the test directory. 
llvm-svn: 89531
 2009-11-21 02:05:31 +00:00
Dale Johannesen
907ff5a620 When generating a vector the really slow way, via loads 
and stores, handle the case where the element size is not
a valid target type correctly (PPC).

llvm-svn: 89521
 2009-11-21 00:53:23 +00:00
Evan Cheng
9828118adf Enable hoisting load from constant memories. 
llvm-svn: 89510
 2009-11-20 23:31:34 +00:00
Sean Callanan
78ee7f5d57 Recommitting PALIGNR shift width fixes. 
Thanks to Daniel Dunbar for fixing clang intrinsics:
  http://llvm.org/viewvc/llvm-project?view=rev&revision=89499

llvm-svn: 89500
 2009-11-20 22:28:42 +00:00
Dale Johannesen
45f80d39f6 Remove an incorrect overaggressive optimization 
(PPC specific).

llvm-svn: 89496
 2009-11-20 22:16:40 +00:00
Sean Callanan
d92626fc0d Reverting PALIGNR fix until I figure out how this 
broke the Clang testsuite.

llvm-svn: 89495
 2009-11-20 22:09:28 +00:00
Sean Callanan
0da77167d3 Fixed PALIGNR to take 8-bit rotations in all cases. 
Also fixed the corresponding testcase, and the PALIGNR
  intrinsic (tested for correctness with llvm-gcc).

llvm-svn: 89491
 2009-11-20 21:40:28 +00:00
Evan Cheng
9f57c4916e Remat VLDRD from constpool. Clean up some instruction property specifications. 
llvm-svn: 89478
 2009-11-20 19:57:15 +00:00
Duncan Sands
072d688d75 Fix PR5558, which was caused by a wrong fix for PR3393 (see commit 63048), 
which was an expensive checks failure due to a bug in the checking.  This
patch in essence reverts the original fix for PR3393, and refixes it by a
tweak to the way expensive checking is done.

llvm-svn: 89454
 2009-11-20 10:45:10 +00:00
Dan Gohman
d3d7358309 Fix fast-isel to avoid selecting the return instruction if a 
tail call has been encountered.

llvm-svn: 89444
 2009-11-20 02:51:26 +00:00
Evan Cheng
5fe8b0b3c5 Also CSE non-pic load from constant pools. 
llvm-svn: 89440
 2009-11-20 02:10:27 +00:00
Evan Cheng
405012b096 Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. 
llvm-svn: 89423
 2009-11-20 00:54:03 +00:00
Daniel Dunbar
cfcc2952fb Unbreak test, Bruno please check. 
llvm-svn: 89329
 2009-11-19 07:18:49 +00:00
Evan Cheng
987b8c3d9a More consistent thumb1 asm printing. 
llvm-svn: 89328
 2009-11-19 06:57:41 +00:00
Evan Cheng
c2e359a418 Shrink ldr / str [sp, imm0-1024] to 16-bit instructions. 
llvm-svn: 89326
 2009-11-19 06:32:27 +00:00
Bruno Cardoso Lopes
bf95b9699e - Add sugregister logic to handle f64=(f32,f32). 
- Support mips1 like load/store of doubles:

Instead of:
  sdc $f0, X($3)
Generate:
  swc $f0, X($3)
  swc $f1, X+4($3)

llvm-svn: 89322
 2009-11-19 06:06:13 +00:00
Bill Wendling
ecc50bcc77 Test from Dhrystone to make sure that we're not emitting an aligned load for a 
string that's aligned at 8-bytes instead of 16-bytes.

llvm-svn: 89295
 2009-11-19 01:33:57 +00:00
Bob Wilson
70bfa110eb Fix buildbots. 
llvm-svn: 89274
 2009-11-18 23:30:38 +00:00
Richard Osborne
fc2d5141a4 Add XCore support for indirectbr / blockaddress. 
llvm-svn: 89273
 2009-11-18 23:20:42 +00:00
Bob Wilson
dccd3bdb4e Tail duplication still needs to iterate. Duplicating new instructions onto 
the tail of a block may make that block a new candidate for duplication.

llvm-svn: 89264
 2009-11-18 22:52:37 +00:00
Jakob Stoklund Olesen
7b5afd4dd6 Fix PR5300. 
When TwoAddressInstructionPass deletes a dead instruction, make sure that all
register kills are accounted for. The 2-addr register does not get special
treatment.

llvm-svn: 89246
 2009-11-18 21:33:35 +00:00
Jakob Stoklund Olesen
9472aae362 Fix inverted test and add testcase from failing self-host. 
llvm-svn: 89167
 2009-11-18 00:02:18 +00:00
Jakob Stoklund Olesen
f96b51a084 Remove fragile test. 
llvm-svn: 89150
 2009-11-17 21:52:40 +00:00
Jim Grosbach
d4db2d58ae Enable arm jumpt table adjustment. 
llvm-svn: 89143
 2009-11-17 21:24:11 +00:00
Anton Korobeynikov
6b1a243be8 Forgot to commit test fixes 
llvm-svn: 89138
 2009-11-17 20:38:36 +00:00
Jakob Stoklund Olesen
0ca73b9208 Enable -split-phi-edges by default, except when -regalloc=local. 
The local register allocator doesn't like it when LiveVariables is run.
We should also disable edge splitting under -O0, but that has to wait a bit.

llvm-svn: 89125
 2009-11-17 19:15:50 +00:00
Evan Cheng
0f7e9f7cec Revert 89021. It's miscompiling llvm-gcc driver driver at -O0. 
llvm-svn: 89082
 2009-11-17 09:55:52 +00:00
Jakob Stoklund Olesen
6ac8f7ec34 Enable -split-phi-edges by default 
llvm-svn: 89021
 2009-11-17 01:07:22 +00:00
Evan Cheng
6e4430374e MOV64rm should be marked isReMaterializable. 
llvm-svn: 89019
 2009-11-17 00:55:55 +00:00
Jim Grosbach
b123a9cbc0 Convert to FileCheck 
llvm-svn: 89007
 2009-11-17 00:20:26 +00:00
Jim Grosbach
2f09113304 Convert to FileCheck 
llvm-svn: 89002
 2009-11-17 00:03:38 +00:00
Jim Grosbach
299e4e76c4 Cleanup. Missed removing these when converting. Oops. 
llvm-svn: 89001
 2009-11-17 00:00:33 +00:00
Dan Gohman
c2979de134 Fix this test - there don't appear to be any actual Reload Reuses 
in this testcase.

llvm-svn: 88998
 2009-11-16 23:49:55 +00:00
Dan Gohman
c35e84e1f5 Revert r87049, which was the workaround for the regression triggered 
by the recent FixedStackPseudoSourceValue-related changes, now that
the specific bug that affected it is fixed, in r88954.

llvm-svn: 88997
 2009-11-16 23:43:42 +00:00
Jim Grosbach
95cf7fad36 Convert to FileCheck 
llvm-svn: 88991
 2009-11-16 23:19:29 +00:00
Evan Cheng
78be20d62e - Check memoperand alignment instead of checking stack alignment. Most load / store folding instructions are not referencing spill stack slots. 
- Mark MOVUPSrm re-materializable.

llvm-svn: 88974
 2009-11-16 21:56:03 +00:00
Jim Grosbach
f4abb1280a Convert to FileCheck 
llvm-svn: 88947
 2009-11-16 20:04:15 +00:00
Lang Hames
6a5810c037 Added a testcase for PR5495. 
llvm-svn: 88946
 2009-11-16 20:03:13 +00:00
Jim Grosbach
deee4fbd5d Convert to FileCheck 
llvm-svn: 88942
 2009-11-16 19:46:46 +00:00
Jim Grosbach
0ba7bb08d7 tbb opt off by default 
llvm-svn: 88921
 2009-11-16 17:24:45 +00:00
David Greene
6469fa6824 Support spill comments. 
Have the asm printer emit a comment if an instruction is a spill or
reload and have the spiller mark copies it introdues so the asm printer
can also annotate those.

llvm-svn: 88911
 2009-11-16 15:12:23 +00:00
Evan Cheng
ea46259f53 Check if subreg index is zero. 
llvm-svn: 88899
 2009-11-16 06:31:49 +00:00
Evan Cheng
2fa416debd For some targets, a copy can use a register multiple times, e.g. ppc. 
llvm-svn: 88895
 2009-11-16 05:52:06 +00:00
Evan Cheng
5c06a152a8 xfail for now. It has been failing. 
llvm-svn: 88892
 2009-11-16 05:44:04 +00:00
Bruno Cardoso Lopes
21ca44ba49 - Fix a small bug while handling target constant pools (one param was missing). 
- Add a smarter constant pool loading, instead of:

lui $2, %hi($CPI1_0)
addiu $2, $2, %lo($CPI1_0)
lwc1 $f0, 0($2)

Generate:

lui $2, %hi($CPI1_0)
lwc1 $f0, %lo($CPI1_0)($2)

llvm-svn: 88886
 2009-11-16 04:33:42 +00:00
Jim Grosbach
1aa571da3c Detect need for autoalignment of the stack earlier to catch spills more 
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling

llvm-svn: 88874
 2009-11-15 21:45:34 +00:00
Jim Grosbach
6028068e88 remove xfail 
llvm-svn: 88817
 2009-11-14 21:57:35 +00:00
Richard Osborne
8748f55236 Add XCore support for arbitrary-sized aggregate returns. 
llvm-svn: 88802
 2009-11-14 19:33:35 +00:00
Evan Cheng
b8c04e1226 Added getSubRegIndex(A,B) that returns subreg index of A to B. Use it to replace broken code in VirtRegRewriter. 
llvm-svn: 88753
 2009-11-14 03:42:17 +00:00
Evan Cheng
9b46e74f42 - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo. 
- If destination is a physical register and it has a subreg index, use the
  sub-register instead.
This fixes PR5423.

llvm-svn: 88745
 2009-11-14 02:55:43 +00:00
Evan Cheng
3781b2e7b3 Add radar number. 
llvm-svn: 88739
 2009-11-14 02:11:32 +00:00
Evan Cheng
c56b0a0f14 Fix PR5412: Fix an inverted check and another missing sub-register check. 
llvm-svn: 88738
 2009-11-14 02:09:09 +00:00
Dan Gohman
b36274632d Enable the tail call optimization when the caller returns undef. 
llvm-svn: 88737
 2009-11-14 02:06:30 +00:00
Evan Cheng
e43198c166 When expanding t2STRDi8 r, r to two stores, add kill markers correctly. 
llvm-svn: 88734
 2009-11-14 01:50:00 +00:00
Evan Cheng
e2907b91de Fix PR5411. Bug in UpdateKills. A reg def partially define its super-registers. 
llvm-svn: 88719
 2009-11-13 23:16:41 +00:00
Dan Gohman
972293611d When optimizing for size, don't tail-merge unless it's likely to be a 
code-size win, and not when it's only likely to be code-size neutral,
such as when only a single instruction would be eliminated and a new
branch would be required.

This fixes rdar://7392894.

llvm-svn: 88692
 2009-11-13 21:02:15 +00:00
Evan Cheng
f629fdcab2 Fix PR5410: LiveVariables lost subreg def: 
D0<def,dead> = ...
...
             = S0<use, kill>
S0<def>      = ...
...
D0<def>      = 

The first D0 def is correctly marked dead, however, livevariables should have
added an implicit def of S0 or we end up with a use without a def.

llvm-svn: 88690
 2009-11-13 20:36:40 +00:00
Dan Gohman
01b65e1e48 Don't let a noalias difference disrupt the tailcall optimization. 
llvm-svn: 88672
 2009-11-13 18:49:38 +00:00
Dale Johannesen
f57a58c4fe Adjust isConstantSplat to allow for big-endian targets. 
PPC is such a target; make it work.

llvm-svn: 87060
 2009-11-13 01:45:18 +00:00
Daniel Dunbar
cdeab5257c Update test. 
llvm-svn: 87049
 2009-11-13 01:01:58 +00:00
Jim Grosbach
8ffdb5d109 Clean up testcase a bit. Simplify case blocks and adjust switch instruction to not take an undefined value as input. 
llvm-svn: 86997
 2009-11-12 17:19:09 +00:00
Benjamin Kramer
86592507dc Fix typo in run line. 
llvm-svn: 86984
 2009-11-12 12:35:27 +00:00
Evan Cheng
deacae0dd9 RegScavenger::enterBasicBlock should always reset register state. 
llvm-svn: 86972
 2009-11-12 07:49:10 +00:00
Evan Cheng
b0a193db31 - Teach LSR to avoid changing cmp iv stride if it will create an immediate that 
cannot be folded into target cmp instruction.
- Avoid a phase ordering issue where early cmp optimization would prevent the
  later count-to-zero optimization.
- Add missing checks which could cause LSR to reuse stride that does not have
  users.
- Fix a bug in count-to-zero optimization code which failed to find the pre-inc
  iv's phi node.
- Remove, tighten, loosen some incorrect checks disable valid transformations.
- Quite a bit of code clean up.

llvm-svn: 86969
 2009-11-12 07:35:05 +00:00
Dan Gohman
f8ec4856e4 Tail merge at any size when there are two potentials blocks and one 
can be made to fall through into the other.

llvm-svn: 86909
 2009-11-12 00:39:10 +00:00
Kenneth Uildriks
82bc831061 x86 users can now return arbitrary sized structs. Structs too large to fit in return registers will be returned through a hidden sret parameter introduced during SelectionDAG construction. 
llvm-svn: 86876
 2009-11-11 19:59:24 +00:00
Dan Gohman
9f47de10e3 Add support for tail duplication to BranchFolding, and extend 
tail merging support to handle more cases.
 - Recognize several cases where tail merging is beneficial even when
   the tail size is smaller than the generic threshold.
 - Make use of MachineInstrDesc::isBarrier to help detect
   non-fallthrough blocks.
 - Check for and avoid disrupting fall-through edges in more cases.

llvm-svn: 86871
 2009-11-11 19:48:59 +00:00
Evan Cheng
913687616e Add nounwind. 
llvm-svn: 86814
 2009-11-11 07:11:02 +00:00
Bill Wendling
a6d7a411d3 Fix test to work on every platform. 
llvm-svn: 86786
 2009-11-11 01:44:22 +00:00
Bill Wendling
8718dfbbaa Fix test to work on every platform. 
llvm-svn: 86785
 2009-11-11 01:41:32 +00:00
Bill Wendling
33ab3cd1bc Make sure that the exception handling data has the same visibility as the 
function it's generated for.

llvm-svn: 86779
 2009-11-11 01:24:59 +00:00
Bill Wendling
ff705446e1 Test this on Darwin only. 
llvm-svn: 86752
 2009-11-10 23:18:33 +00:00
Dale Johannesen
20e1cd09ba Emit correct code when making a ConstantPool entry for a vector 
constant whose component type is not a legal type for the target.
(If the target ConstantPool cannot handle this type either, it has
an opportunity to merge elements.  In practice any target with
8-bit bytes must support i8 *as data*).  7320806 (partial).

llvm-svn: 86751
 2009-11-10 23:16:41 +00:00
Bill Wendling
1176227990 Modify how the prologue encoded the "move" information for the FDE. GCC 
generates a sequence similar to this:

__Z4funci:
LFB2:
        mflr r0
LCFI0:
        stmw r30,-8(r1)
LCFI1:
        stw r0,8(r1)
LCFI2:
        stwu r1,-80(r1)
LCFI3:
        mr r30,r1
LCFI4:

where LCFI3 and LCFI4 are used by the FDE to indicate what the FP, LR, and other
things are. We generated something more like this:

Leh_func_begin1:
        mflr r0
        stw r31, 20(r1)
        stw r0, 8(r1)
Llabel1:
        stwu r1, -80(r1)
Llabel2:
        mr r31, r1

Note that we are missing the "mr" instruction. This patch makes it more like the
GCC output.

llvm-svn: 86729
 2009-11-10 22:14:04 +00:00
Mike Stump
ee3ba929d0 Add testcase for recent checkin. 
llvm-svn: 86620
 2009-11-09 23:10:49 +00:00
Jim Grosbach
9f37156ae5 Update test 
llvm-svn: 86614
 2009-11-09 22:59:01 +00:00
Jim Grosbach
ea6c9c17f5 Use Unified Assembly Syntax for the ARM backend. 
llvm-svn: 86494
 2009-11-09 00:11:35 +00:00
Anton Korobeynikov
552b831b91 Add and-not (bic) patterns. Based heavily on patch by Brian Lucas! 
llvm-svn: 86471
 2009-11-08 15:33:12 +00:00
Anton Korobeynikov
6f4ee0efe1 Fix invalid operand updates & implement post-inc memory operands 
llvm-svn: 86466
 2009-11-08 14:27:38 +00:00
Anton Korobeynikov
7b3a35eee8 It is invalid to infer the value type from the result #0 of the node 
since the instruction might use the other result of different type.

llvm-svn: 86462
 2009-11-08 12:14:54 +00:00
Nate Begeman
49d93dc6d1 x86 vector shuffle cleanup/fixes: 
1. rename the movhp patfrag to movlhps, since thats what it actually matches
2. eliminate the bogus movhps load and store patterns, they were incorrect.  The load transforms are already handled (correctly) by shufps/unpack.
3. revert a recent test change to its correct form.

llvm-svn: 86415
 2009-11-07 23:17:15 +00:00
Anton Korobeynikov
9dc741f523 Add some dummy support for post-incremented loads 
llvm-svn: 86385
 2009-11-07 17:15:06 +00:00
Anton Korobeynikov
0a13189111 Add 8 bit libcalls and make use of them for msp430 
llvm-svn: 86384
 2009-11-07 17:14:39 +00:00
Anton Korobeynikov
da044db0f5 Initial support for addrmode handling. Tests by Brian Lucas! 
llvm-svn: 86382
 2009-11-07 17:13:35 +00:00
Anton Korobeynikov
30095499fc It turns out that the testcase in question uncovered subreg-handling bug. 
Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.

llvm-svn: 86375
 2009-11-07 15:20:32 +00:00
Eric Christopher
c5bcc1db29 Fix a couple of shuffle patterns to use movhlps instead 
of movhps as the constraint.  Changes optimizations so
update testcases as appropriate as well.

llvm-svn: 86360
 2009-11-07 08:45:53 +00:00
Chris Lattner
d5eaa6d39b Fix PR5421 by APInt'izing switch lowering. 
llvm-svn: 86354
 2009-11-07 07:50:34 +00:00
Chris Lattner
1be54634e0 merge cmp1 into cmp0 and filecheckize. 
llvm-svn: 86345
 2009-11-07 06:19:20 +00:00
Evan Cheng
899d8cb6a0 Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic. 
llvm-svn: 86330
 2009-11-07 04:04:34 +00:00
Evan Cheng
8eaaffb9da - Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical 
except it doesn't care if the definitions' virtual registers differ. This is
  used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
  Since pc relative constantpool entries are always different, this requires it
  it check if the values can actually the same.

llvm-svn: 86328
 2009-11-07 03:52:02 +00:00
Evan Cheng
6e3e66375a - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative 
load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.

llvm-svn: 86304
 2009-11-06 23:52:48 +00:00
Anton Korobeynikov
dca40933ee Honour subreg machine operands during asmprinting 
llvm-svn: 86303
 2009-11-06 23:45:15 +00:00
Bob Wilson
e79354a831 Print VMOV (immediate) operands as hexadecimal values. Apple's assembler 
will not accept negative values for these.  LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates.  Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.

llvm-svn: 86301
 2009-11-06 23:33:28 +00:00
Bob Wilson
68772d4db2 Fix a broken test. 
llvm-svn: 86298
 2009-11-06 23:06:42 +00:00
Evan Cheng
aaf30ce699 Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead. 
llvm-svn: 86294
 2009-11-06 22:24:13 +00:00
Eric Christopher
593cfc9984 Fix PR5315, original patch by Nicolas Capens! 
llvm-svn: 86203
 2009-11-06 00:11:57 +00:00
Dan Gohman
229f9edf7a Update these tests for the new label names. 
llvm-svn: 86192
 2009-11-05 23:31:40 +00:00
Bob Wilson
641ce17702 Add -mtriple to llc commands, attempting to fix buildbot failures. 
llvm-svn: 86086
 2009-11-05 00:51:31 +00:00
Bob Wilson
d14be3d83c Attempt again to fix buildbot failures: make expected output less specific 
and compile with -mtriple to specify *-apple-darwin targets.

llvm-svn: 86081
 2009-11-05 00:30:35 +00:00
Bob Wilson
25738f9e79 Add PowerPC codegen for indirect branches. 
llvm-svn: 86050
 2009-11-04 21:31:18 +00:00
Bob Wilson
9e30ecad4e Fix broken test. 
llvm-svn: 86045
 2009-11-04 20:04:11 +00:00
Bob Wilson
ca42ca296d Add test for ARM indirectbr codegen. 
llvm-svn: 86042
 2009-11-04 19:25:34 +00:00
Evan Cheng
801415706c RangeIsDefinedByCopyFromReg() should check for subreg_to_reg, insert_subreg, 
and extract_subreg as a "copy" that defines a valno.
Also fixes a typo. These two issues prevent a simple subreg coalescing from
happening before.

llvm-svn: 86022
 2009-11-04 08:33:14 +00:00
Evan Cheng
8b161e8f4f Fix test. 
llvm-svn: 85986
 2009-11-04 00:42:33 +00:00
Evan Cheng
caab17007b fconsts / fconstd immediate should be proceeded with #. 
llvm-svn: 85952
 2009-11-03 21:59:33 +00:00
Evan Cheng
d783406059 Re-apply 85799. It turns out my code isn't buggy. 
llvm-svn: 85947
 2009-11-03 21:40:02 +00:00
Kenneth Uildriks
e711736014 Make opt default to not adding a target data string and update tests that depend on target data to supply it within the test 
llvm-svn: 85900
 2009-11-03 15:29:06 +00:00
Evan Cheng
ed22395c61 Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8. 
llvm-svn: 85871
 2009-11-03 05:52:54 +00:00
Nate Begeman
52bcd33312 Declare sin & cos as readonly so they match the code in SelectionDAGBuild 
llvm-svn: 85853
 2009-11-03 02:19:31 +00:00
Anton Korobeynikov
bce2703f18 Temporary xfail until PR5367 will be resolved 
llvm-svn: 85848
 2009-11-03 00:37:36 +00:00
Anton Korobeynikov
48b30c79be Revert r85049, it is causing PR5367 
llvm-svn: 85847
 2009-11-03 00:24:48 +00:00
Evan Cheng
ca5847665b Revert 85799 for now. It might be breaking llvm-gcc driver. 
llvm-svn: 85827
 2009-11-02 21:49:14 +00:00
Evan Cheng
ec5cb0cdbd Initilize the machine LICM CSE map upon the first time an instruction is hoisted to 
the loop preheader. Add instructions which are already in the preheader block that
may be common expressions of those that are hoisted out. These does get a few more
instructions CSE'ed.

llvm-svn: 85799
 2009-11-02 08:09:49 +00:00
Evan Cheng
ce9d8e2737 Remove an irrelevant and poorly reduced test case. 
llvm-svn: 85794
 2009-11-02 07:11:54 +00:00
Evan Cheng
57f7c7c914 Unbreak ARMBaseRegisterInfo::copyRegToReg. 
llvm-svn: 85787
 2009-11-02 04:44:55 +00:00
Anton Korobeynikov
09147da530 Handle splats of undefs properly. This includes the testcase for PR5364 as well. 
llvm-svn: 85767
 2009-11-02 00:12:06 +00:00
Anton Korobeynikov
ed410a8ee3 64-bit FP loads & stores operate on both NEON and VFP pipelines. 
llvm-svn: 85765
 2009-11-02 00:11:06 +00:00
Evan Cheng
4a0d47f209 Make use of imm12 version of Thumb2 ldr / str instructions more aggressively. 
llvm-svn: 85743
 2009-11-01 21:12:51 +00:00
Evan Cheng
0151329ce5 Fix tests. 
llvm-svn: 85723
 2009-11-01 18:13:29 +00:00
Chris Lattner
4cf2980e59 improve x86 codegen support for blockaddress. We now compile 
the testcase into:

_test1:                                                     ## @test1
## BB#0:                                                    ## %entry
	leaq	L_test1_bb6(%rip), %rax
	jmpq	*%rax
L_test1_bb:                                                 ## Address Taken
LBB1_1:                                                     ## %bb
	movb	$1, %al
	ret
L_test1_bb6:                                                ## Address Taken
LBB1_2:                                                     ## %bb6
	movb	$2, %al
	ret

Note, it is very very strange that BlockAddressSDNode doesn't carry 
around TargetFlags.  Dan, please fix this.

llvm-svn: 85703
 2009-11-01 03:25:03 +00:00
Evan Cheng
de16fff3e8 Use cbz and cbnz instructions. 
llvm-svn: 85698
 2009-10-31 23:46:45 +00:00
Jim Grosbach
5b094f3b36 vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using 
them for scalar floating point operations for now.

llvm-svn: 85697
 2009-10-31 22:57:36 +00:00
Jim Grosbach
7dfa53d978 Consolidate test files 
llvm-svn: 85696
 2009-10-31 22:20:56 +00:00
Jim Grosbach
acb31ebed1 Change to use FileCheck 
llvm-svn: 85695
 2009-10-31 22:16:14 +00:00
Jim Grosbach
93bcf7b8ce Make tests more explicit about which instructions are expected. 
llvm-svn: 85694
 2009-10-31 22:14:17 +00:00
Jim Grosbach
84e67e8e5c Grammar tweak to comments 
llvm-svn: 85693
 2009-10-31 22:12:44 +00:00
Jim Grosbach
c003ed5615 Update test to be more explicit about what instruction sequences are expected for each operation. 
llvm-svn: 85691
 2009-10-31 22:10:38 +00:00
Jim Grosbach
2a445e5d0a Update test to be more explicit about what instruction sequences are expected for each operation. 
llvm-svn: 85689
 2009-10-31 21:52:58 +00:00
Jim Grosbach
ace75c4288 Expand 64-bit logical shift right inline 
llvm-svn: 85687
 2009-10-31 21:42:19 +00:00
Jim Grosbach
16ae289667 Expand 64-bit arithmetic shift right inline 
llvm-svn: 85685
 2009-10-31 21:00:56 +00:00
Benjamin Kramer
2cc5f86d43 Force triple; darwin's ASM syntax differs from linux's. 
llvm-svn: 85676
 2009-10-31 19:54:06 +00:00
Jim Grosbach
534d2cb249 Expand 64 bit left shift inline rather than using the libcall. For now, this 
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.

llvm-svn: 85675
 2009-10-31 19:38:01 +00:00
Benjamin Kramer
60dac7de40 Add missing colons for FileCheck. 
llvm-svn: 85674
 2009-10-31 19:22:24 +00:00
Jim Grosbach
78a5bcfa02 Convert to FileCheck 
llvm-svn: 85673
 2009-10-31 19:06:53 +00:00
Evan Cheng
9178904e56 It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming. 
llvm-svn: 85643
 2009-10-31 03:39:36 +00:00
Dan Gohman
d5dbd3f588 Add a target triple so that this test behaves consistently across hosts. 
llvm-svn: 85640
 2009-10-31 00:15:28 +00:00
Dan Gohman
14157e31a3 Fix the -mattr line for this test so that it passes on hosts that lack SSSE3. 
llvm-svn: 85637
 2009-10-30 23:18:27 +00:00
Dan Gohman
ad6c6a3d33 Fix MachineLICM to use the correct virtual register class when 
unfolding loads for hoisting.  getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.

llvm-svn: 85622
 2009-10-30 22:18:41 +00:00
Evan Cheng
52d6e56ac9 I forgot to commit this test. 
llvm-svn: 85608
 2009-10-30 20:03:40 +00:00
Rafael Espindola
d4fadd76da This fixes functions like 
void f (int a1, int a2, int a3, int a4, int a5,...)

In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.

llvm-svn: 85590
 2009-10-30 14:33:14 +00:00
Bob Wilson
f13be9d41e Reimplement BranchFolding change to avoid tail merging for a 1 instruction 
common tail, except when the OptimizeForSize function attribute is present.
Radar 7338114.

llvm-svn: 85441
 2009-10-28 22:10:20 +00:00
Dan Gohman
076a3b5e25 Teach MachineLICM to unfold loads from constant memory from 
otherwise unhoistable instructions in order to allow the loads
to be hoisted.

llvm-svn: 85364
 2009-10-28 03:21:57 +00:00
Evan Cheng
1babe43881 Use fconsts and fconstd to materialize small fp constants. 
llvm-svn: 85362
 2009-10-28 01:44:26 +00:00
Dan Gohman
00c9f3e905 Mark dead physregdefs dead immediately. This helps MachineSink and 
MachineLICM and other things which run before LiveVariables is run.

llvm-svn: 85360
 2009-10-28 01:13:53 +00:00
Dan Gohman
a9fb025f00 Allow constants of different types to share constant pool entries 
if they have compatible encodings.

llvm-svn: 85359
 2009-10-28 01:12:16 +00:00
Rafael Espindola
9cafe9e468 Add missing testcase. 
llvm-svn: 85266
 2009-10-27 17:59:03 +00:00
Bob Wilson
aadcaed95f Fix Thumb2 failures by converting them to FileCheck. 
llvm-svn: 85210
 2009-10-27 06:31:02 +00:00
Bob Wilson
cc098c98de Fix the rest of the ARM failures by converting them to FileCheck. 
llvm-svn: 85208
 2009-10-27 06:16:45 +00:00
Bob Wilson
5753a34ebb Fix some more failures by converting to FileCheck. 
llvm-svn: 85207
 2009-10-27 05:50:28 +00:00
Bob Wilson
37191c825b Convert to FileCheck, fixing failure due to tab change in the process. 
llvm-svn: 85204
 2009-10-27 05:30:47 +00:00
David Goodwin
f6199e95b0 Break anti-dependence breaking out into its own class. 
llvm-svn: 85127
 2009-10-26 16:59:04 +00:00
Dan Gohman
3d0c010ee4 Make LSR's OptimizeShadowIV ignore induction variables with negative 
strides for now, because it doesn't handle them correctly. This fixes a
miscompile of SingleSource/Benchmarks/Misc-C++/ray.

This problem was usually hidden because indvars transforms such induction
variables into negations of canonical induction variables.

llvm-svn: 85118
 2009-10-26 15:32:57 +00:00
Evan Cheng
4443642def - Revert some changes from 85044, 85045, and 85047 that broke x86_64 tests and 
bootstrapping. It's not safe to leave identity subreg_to_reg and insert_subreg
  around.
- Relax register scavenging to allow use of partially "not-live" registers. It's
  common for targets to operate on registers where the top bits are undef. e.g.
  s0 =
  d0 = insert_subreg d0<undef>, s0, 1
  ...
     = d0
  When the insert_subreg is eliminated by the coalescer, the scavenger used to
  complain. The previous fix was to keep to insert_subreg around. But that's
  brittle and it's overly conservative when we want to use the scavenger to 
  allocate registers. It's actually legal and desirable for other instructions
  to use the "undef" part of d0. e.g.
  s0 =
  d0 = insert_subreg d0<undef>, s0, 1
  ...
  s1 =
     = s1
     = d0
  We probably need add a "partial-undef" marker on machine operand so the
  machine verifier would not complain.

llvm-svn: 85091
 2009-10-26 04:56:07 +00:00
Chris Lattner
e3508acbef fix PR5295 where the .ll parser didn't reject a function after a global 
or global after a function with conflicting names.  Update some testcases
that were accidentally depending on this behavior.

llvm-svn: 85081
 2009-10-25 23:22:50 +00:00
Evan Cheng
a308ae55a5 Add a couple of ARM cross-rc coalescing tests. 
llvm-svn: 85051
 2009-10-25 08:01:41 +00:00
Evan Cheng
1c169777ca Update tests. 
llvm-svn: 85050
 2009-10-25 07:53:48 +00:00
Dan Gohman
b15fee5666 APInt-ify the gep scaling code, so that it correctly handles the case where 
the scale overflows pointer-sized arithmetic. This fixes PR5281.

llvm-svn: 84954
 2009-10-23 17:57:43 +00:00
Evan Cheng
aa03d9926d Update tests for 84931. 
llvm-svn: 84932
 2009-10-23 05:58:34 +00:00
David Goodwin
82c1dd9754 Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none. 
llvm-svn: 84911
 2009-10-22 23:19:17 +00:00