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725 Commits

Author SHA1 Message Date
Lauro Ramos Venancio
f9641d332a In Thumb mode, the frame register must be R7. 
llvm-svn: 36512
 2007-04-27 17:58:03 +00:00
Lauro Ramos Venancio
f385b56870 ARM TLS: implement "general dynamic", "initial exec" and "local exec" models. 
llvm-svn: 36506
 2007-04-27 13:54:47 +00:00
Evan Cheng
a1593a9ec6 Darwin runtime library does not have these. 
llvm-svn: 36505
 2007-04-27 08:15:43 +00:00
Evan Cheng
2da659afa3 Special handling of LEApcrel and tLEApcrel. 
llvm-svn: 36504
 2007-04-27 08:14:15 +00:00
Evan Cheng
75ed5c5cb2 Back out previous check-in. Incorrect. 
llvm-svn: 36503
 2007-04-27 07:50:02 +00:00
Evan Cheng
b54f757b65 tLEApcrel is a AddrModeTs, i.e. pc relative. 
llvm-svn: 36502
 2007-04-27 07:37:22 +00:00
Evan Cheng
eff332e3e1 Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion. 
llvm-svn: 36483
 2007-04-26 19:00:32 +00:00
Evan Cheng
7f44e880dc Match MachineFunction::UsedPhysRegs changes. 
llvm-svn: 36452
 2007-04-25 22:13:27 +00:00
Lauro Ramos Venancio
d922b8ca9b remember to emit weak reference in one more case. 
llvm-svn: 36438
 2007-04-25 14:50:40 +00:00
Evan Cheng
de9468373e Relex assertions to account for additional implicit def / use operands. 
llvm-svn: 36430
 2007-04-25 07:12:14 +00:00
Dale Johannesen
5f27e8bcc4 Make Thumb funcs containing islands 4-byte aligned. Fix bugs maintaining 
BBOffsets and BBSizes when adjusting conditional branches.

llvm-svn: 36372
 2007-04-23 20:09:04 +00:00
Dale Johannesen
f7d3443fa7 add Align field, and use when generating function alignment 
llvm-svn: 36371
 2007-04-23 20:07:25 +00:00
Dale Johannesen
9dce0dffd1 add isThumb (unused as yet) 
llvm-svn: 36370
 2007-04-23 20:04:35 +00:00
Lauro Ramos Venancio
f8b49e5ee0 Implement PIC for arm-linux. 
llvm-svn: 36324
 2007-04-22 00:04:12 +00:00
Evan Cheng
20c6a03b60 Specify S registers as D registers' sub-registers. 
llvm-svn: 36280
 2007-04-20 21:20:10 +00:00
Chris Lattner
f7ac47b4e2 add a crazy idea 
llvm-svn: 36273
 2007-04-20 20:18:43 +00:00
Lauro Ramos Venancio
5e0a3ef555 Fix a bug in getFrameRegister. 
Reported by Raul Herbster.

llvm-svn: 36262
 2007-04-19 14:09:38 +00:00
Chris Lattner
87296c2580 dag combiner just got better at pruning bits. This fixes CodeGen/ARM/rev.ll 
llvm-svn: 36222
 2007-04-17 22:39:58 +00:00
Chris Lattner
af5c203dbd add a note 
llvm-svn: 36203
 2007-04-17 18:03:00 +00:00
Anton Korobeynikov
f3e62a428a Removed tabs everywhere except autogenerated & external files. Add make 
target for tabs checking.

llvm-svn: 36146
 2007-04-16 18:10:23 +00:00
Chris Lattner
e7cab7b7a4 arm has r+r*s and r+i addr modes, but no r+i+r*s addr modes. 
llvm-svn: 35962
 2007-04-13 06:50:55 +00:00
Chris Lattner
e9a9a3f172 Fix incorrect fall-throughs in addr mode code. This fixes CodeGen/ARM/arm-negative-stride.ll 
llvm-svn: 35909
 2007-04-11 16:17:12 +00:00
Chris Lattner
3bbd376057 restore support for negative strides 
llvm-svn: 35859
 2007-04-10 03:48:29 +00:00
Chris Lattner
98199016ae remove dead target hooks 
llvm-svn: 35846
 2007-04-09 23:33:39 +00:00
Chris Lattner
ae6e2c0ee5 remove some dead target hooks, subsumed by isLegalAddressingMode 
llvm-svn: 35840
 2007-04-09 22:27:04 +00:00
Evan Cheng
44488cb676 Implement inline asm modifier P. 
llvm-svn: 35640
 2007-04-04 00:13:29 +00:00
Evan Cheng
d5956e4409 Typo. 
llvm-svn: 35639
 2007-04-04 00:06:07 +00:00
Evan Cheng
2cd9df6983 Remove unused constant pool entries. 
llvm-svn: 35635
 2007-04-03 23:39:48 +00:00
Evan Cheng
db15aa24f9 Fixed a bug that causes codegen of noop like add r0, r0, #0. 
llvm-svn: 35627
 2007-04-03 21:31:21 +00:00
Evan Cheng
16696f0ad8 Inverted logic. 
llvm-svn: 35619
 2007-04-03 06:44:25 +00:00
Chris Lattner
4d702a890c Arm supports negative strides as well, add them. This lets us compile: 
CodeGen/ARM/arm-negative-stride.ll to:

LBB1_2: @bb
        str r1, [r3, -r0, lsl #2]
        add r0, r0, #1
        cmp r0, r2
        bne LBB1_2      @bb

llvm-svn: 35609
 2007-04-03 00:13:57 +00:00
Dale Johannesen
e1c3dc7c78 fix off by 1 error in displacement computation 
llvm-svn: 35602
 2007-04-02 20:31:06 +00:00
Chris Lattner
726d461daf fix the CodeGen/ARM/2007-03-13-InstrSched.ll regression: allow IV's with scales 
to be folded into non-store instructions.

llvm-svn: 35601
 2007-04-02 18:51:18 +00:00
Chris Lattner
ff9caac83e add support for the 'w' inline asm register class. 
llvm-svn: 35598
 2007-04-02 17:24:08 +00:00
Lauro Ramos Venancio
7e21418680 - Divides the comparisons in two types: comparisons that only use N and Z 
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).

llvm-svn: 35573
 2007-04-02 01:30:03 +00:00
Evan Cheng
949a34fbad Add i16 address mode. 
llvm-svn: 35551
 2007-04-01 08:06:46 +00:00
Chris Lattner
c0405a348d implement the new addressing mode description hook. 
llvm-svn: 35521
 2007-03-30 23:15:24 +00:00
Evan Cheng
526a67c09b New entry. 
llvm-svn: 35480
 2007-03-29 21:40:13 +00:00
Evan Cheng
3a6b488265 Can't re-materialize mov r, imm in thumb since mov would clobber the condition code. 
llvm-svn: 35479
 2007-03-29 21:38:31 +00:00
Evan Cheng
bde0409264 Add support for hidden visibility to darwin/arm. 
llvm-svn: 35448
 2007-03-29 07:49:34 +00:00
Evan Cheng
a55449c051 Remove isLegalAddressImmediate. 
llvm-svn: 35406
 2007-03-28 01:53:55 +00:00
Lauro Ramos Venancio
8b2e32de5a bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK. 
llvm-svn: 35381
 2007-03-27 16:19:21 +00:00
Evan Cheng
968135bd3f findRegisterUseOperand() changed. 
llvm-svn: 35366
 2007-03-26 22:41:48 +00:00
Chris Lattner
b19069959d switch TargetLowering::getConstraintType to take the entire constraint, 
not just the first letter.  No functionality change.

llvm-svn: 35322
 2007-03-25 02:14:49 +00:00
Dale Johannesen
44c0a5d545 repair x86 performance, dejagnu problems from previous change 
llvm-svn: 35245
 2007-03-21 21:51:52 +00:00
Evan Cheng
fb9c4c2edc Updated. 
llvm-svn: 35229
 2007-03-20 22:32:39 +00:00
Dale Johannesen
3e422e3b49 do not share old induction variables when this would result in invalid 
instructions (that would have to be split later)

llvm-svn: 35227
 2007-03-20 21:54:54 +00:00
Lauro Ramos Venancio
11d7d3fcaf bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted: 
mov lr, pc
    bx lr
So, the function was not called.

llvm-svn: 35218
 2007-03-20 17:57:23 +00:00
Evan Cheng
4fec9d7228 Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool. 
llvm-svn: 35207
 2007-03-20 08:11:30 +00:00
Evan Cheng
11976abd1e New entry. 
llvm-svn: 35206
 2007-03-20 08:10:17 +00:00
Evan Cheng
41f4f032ee Added MRegisterInfo hook to re-materialize an instruction. 
llvm-svn: 35205
 2007-03-20 08:09:38 +00:00
Chris Lattner
1ed603c0d9 fix indentation 
llvm-svn: 35202
 2007-03-20 02:25:53 +00:00
Dale Johannesen
c526b970ce fix obvious comment bug 
llvm-svn: 35196
 2007-03-20 00:30:56 +00:00
Evan Cheng
8d374caead Fix naming inconsistencies. 
llvm-svn: 35163
 2007-03-19 07:48:02 +00:00
Evan Cheng
7cbf4c4582 Special LDR instructions to load from non-pc-relative constantpools. These are 
rematerializable. Only used for constant generation for now.

llvm-svn: 35162
 2007-03-19 07:20:03 +00:00
Evan Cheng
389cf8e719 Constant generation instructions are re-materializable. 
llvm-svn: 35161
 2007-03-19 07:09:02 +00:00
Lauro Ramos Venancio
f756184c5e Only ARMv6 has BSWAP. 
Fix MultiSource/Applications/aha test.

llvm-svn: 35128
 2007-03-16 22:54:16 +00:00
Evan Cheng
4858c6f781 Added isLegalAddressExpression(). Only allows X +/- C for now. 
llvm-svn: 35122
 2007-03-16 08:43:56 +00:00
Evan Cheng
7cbde8351a AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2] 
llvm-svn: 35088
 2007-03-13 21:05:54 +00:00
Evan Cheng
7b24b3e474 Zero is always a legal AM immediate. 
llvm-svn: 35087
 2007-03-13 20:37:59 +00:00
Evan Cheng
92712d4884 Implement getTargetLowering() or else LSR won't be using ARM specific hooks. 
llvm-svn: 35077
 2007-03-13 01:20:42 +00:00
Evan Cheng
7767159f08 Updated TargetLowering LSR addressing mode hooks for ARM and Thumb. 
llvm-svn: 35075
 2007-03-12 23:30:29 +00:00
Evan Cheng
a4e410aa9c Minor stuff. 
llvm-svn: 35049
 2007-03-09 19:46:06 +00:00
Evan Cheng
d7201d12af Add comments about LSR / ARM. 
llvm-svn: 35048
 2007-03-09 19:35:33 +00:00
Evan Cheng
2e6f19d8c8 Unfinished work and ideas related to register scavenger. 
llvm-svn: 35047
 2007-03-09 19:34:51 +00:00
Dale Johannesen
10a05b538d apply comments from review of last patch 
llvm-svn: 35045
 2007-03-09 19:18:59 +00:00
Dale Johannesen
23c2498e23 Add some observations from CoreGraphics benchmark. Remove register 
scavenging todo item, since it is now implemented.

llvm-svn: 35044
 2007-03-09 17:58:17 +00:00
Evan Cheng
7ef8db2fb5 Implement inline asm modifier c. 
llvm-svn: 35035
 2007-03-08 22:42:46 +00:00
Evan Cheng
6445ce2423 Fix a typo. 
llvm-svn: 35030
 2007-03-08 21:59:30 +00:00
Evan Cheng
7d528d089c Putting more constants which do not contain relocations into .literal{4|8|16} 
llvm-svn: 35026
 2007-03-08 08:31:54 +00:00
Evan Cheng
393fd04eb4 Change register allocation order to Dale's suggestion. 
llvm-svn: 35021
 2007-03-08 02:56:40 +00:00
Evan Cheng
2c3e4ab3a6 Bug fix. Not advancing the register scavenger iterator correctly. 
llvm-svn: 35020
 2007-03-08 02:55:08 +00:00
Evan Cheng
c79408b032 For Darwin, put constant data into .const, .const_data, .literal{4|8|16} 
sections.

llvm-svn: 35017
 2007-03-08 01:25:25 +00:00
Evan Cheng
51c3e53eb7 Only safe to use a call-clobbered or spilled callee-saved register as scratch register. 
llvm-svn: 35010
 2007-03-07 20:30:36 +00:00
Anton Korobeynikov
85d6c1ebad Refactoring of formal parameter flags. Enable properly use of 
zext/sext/aext stuff.

llvm-svn: 35008
 2007-03-07 16:25:09 +00:00
Evan Cheng
493960579f ARM always use register scavenger. No longer reserves R12. 
llvm-svn: 34999
 2007-03-07 02:46:23 +00:00
Evan Cheng
4e01b11512 Fix some brittle code. Watch out for cases where register scavenger is pointing to deleted instructions. 
llvm-svn: 34998
 2007-03-07 02:38:05 +00:00
Evan Cheng
9839628fd1 Fix one more Thumb eliminateFrameIndex bug. 
llvm-svn: 34990
 2007-03-07 00:12:18 +00:00
Evan Cheng
63ffd3e17f Register scavenging is now on by default for ARM. 
llvm-svn: 34987
 2007-03-06 22:02:53 +00:00
Evan Cheng
6453ad00d2 Make load / store optimizer use register scavenger. 
llvm-svn: 34986
 2007-03-06 21:59:20 +00:00
Evan Cheng
228403bfcb Code clean up. Prepare to use register scavenger. 
llvm-svn: 34976
 2007-03-06 18:02:41 +00:00
Evan Cheng
7c90fb2d67 Scavenge a register using the register scavenger when needed. 
llvm-svn: 34966
 2007-03-06 10:03:56 +00:00
Anton Korobeynikov
6da6c8c48b Use new SDIselParamAttr enumeration. This removes "magick" constants 
from formal attributes' flags processing.

llvm-svn: 34963
 2007-03-06 08:12:33 +00:00
Lauro Ramos Venancio
3f855f6a54 Use init_array/fini_array sections for static contructors/destructors when the ABI is AAPCS. 
Fix SingleSource/Regression/C/ConstructorDestructorAttributes test on arm-linux-gnueabi.

llvm-svn: 34931
 2007-03-05 17:59:58 +00:00
Dale Johannesen
a6003a9eb6 eliminate unnecessary reset of SP in epilog on darwin 
llvm-svn: 34824
 2007-03-02 01:17:17 +00:00
Evan Cheng
07dcde8ba2 Use a spilled free callee-saved register as scratch register. 
llvm-svn: 34785
 2007-03-01 08:57:52 +00:00
Evan Cheng
8d3d4155e5 - Track which callee-saved registers are spilled. 
- Some code clean up.

llvm-svn: 34783
 2007-03-01 08:26:31 +00:00
Evan Cheng
f771a323c2 Switch from std::vector<bool> to BitVector. 
llvm-svn: 34781
 2007-03-01 07:52:44 +00:00
Bill Wendling
2aabf75e82 Get rid of verboten <iostream> include. 
llvm-svn: 34777
 2007-03-01 06:05:39 +00:00
Dale Johannesen
f38e3d7085 Changes requested in review of last pass. Also pulled isThumb into a 
member, instead of resetting in every function that uses it.

llvm-svn: 34764
 2007-02-28 23:20:38 +00:00
Evan Cheng
5dc0ece7cb Doh. ARM::PC is obvious a reserved register. 
llvm-svn: 34763
 2007-02-28 23:12:34 +00:00
Dale Johannesen
5ec68034ee Add intelligence about where to break large blocks. 
llvm-svn: 34755
 2007-02-28 18:41:23 +00:00
Evan Cheng
db591ecaa8 Make requiresRegisterScavenging determination on a per MachineFunction basis. 
llvm-svn: 34711
 2007-02-28 00:59:19 +00:00
Evan Cheng
cfb0f8cfc6 Temporary: make R12 available in ARM mode if RegScavenger is being used. 
llvm-svn: 34709
 2007-02-28 00:22:44 +00:00
Evan Cheng
fa23d8e51f Start making use of RegScavenger. 
llvm-svn: 34708
 2007-02-28 00:21:58 +00:00
Evan Cheng
116f97f2c7 PEI now passes a RegScavenger ptr to eliminateFrameIndex. 
llvm-svn: 34707
 2007-02-28 00:21:17 +00:00
Evan Cheng
4357509984 Minor tweak. Allocate r0 to r3 in reverse order, r3 is least likely to be livein to a function. 
llvm-svn: 34701
 2007-02-27 23:03:55 +00:00
Evan Cheng
a19dd6f388 Let MRegisterInfo now owns RegScavenger; eliminateFrameIndex must preserve register kill info. 
llvm-svn: 34692
 2007-02-27 21:12:35 +00:00
Dale Johannesen
f6f34ec2e0 cosmetic changes from review of last patch. obvious 
llvm-svn: 34598
 2007-02-25 18:31:31 +00:00
Dale Johannesen
6e366a1006 remove crediting of Evan Cheng and me. 
llvm-svn: 34568
 2007-02-25 01:42:36 +00:00
Dale Johannesen
ccecc12da5 Removed WaterListOffset, inserted BBOffsets. Remove TODO item about this 
from README.
When no water available, use end of block if in range.  (More to do here.)

llvm-svn: 34563
 2007-02-25 00:47:03 +00:00
Lauro Ramos Venancio
19040a3f0d bugfix: SP wasn't updated for varargs when frame pointer was eliminated. 
llvm-svn: 34537
 2007-02-23 21:53:48 +00:00
Lauro Ramos Venancio
7c2f17b629 Fix stack alignment in functions with varargs. 
llvm-svn: 34532
 2007-02-23 20:32:57 +00:00
Dale Johannesen
544968d665 rewrite of constant islands 
llvm-svn: 34523
 2007-02-23 05:02:36 +00:00
Evan Cheng
2d4b1cb0ca Added -march=thumb; removed -enable-thumb. 
llvm-svn: 34521
 2007-02-23 03:14:31 +00:00
Evan Cheng
bd3219f5bf Add option to turn on register scavenger; By default, spills kills the register being stored. 
llvm-svn: 34514
 2007-02-23 01:09:11 +00:00
Jim Laskey
b57ee1fc37 Simplify lowering and selection of exception ops. 
llvm-svn: 34488
 2007-02-22 14:56:36 +00:00
Jim Laskey
6a937ad320 Support to provide exception and selector registers. 
llvm-svn: 34482
 2007-02-21 22:54:50 +00:00
Evan Cheng
e4ab9c032b Re-apply my liveintervalanalysis changes. Now with PR1207 fixes. 
llvm-svn: 34428
 2007-02-19 21:49:54 +00:00
Reid Spencer
b27fcf3482 For PR1207: 
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.

llvm-svn: 34399
 2007-02-19 03:20:00 +00:00
Evan Cheng
8c2508f1ac Added getReservedRegs(). 
llvm-svn: 34376
 2007-02-17 11:06:00 +00:00
Chris Lattner
5cece73ec8 Generalize TargetData strings, to support more interesting forms of data. 
Patch by Scott Michel.

llvm-svn: 34266
 2007-02-14 05:52:17 +00:00
Lauro Ramos Venancio
81f86314e6 Add space between // and the comment. 
llvm-svn: 34246
 2007-02-13 20:06:15 +00:00
Lauro Ramos Venancio
ff9f78e230 Add ABI information to ARM subtarget. 
llvm-svn: 34245
 2007-02-13 19:52:28 +00:00
Lauro Ramos Venancio
02ba8f20e3 According to ARM EABI, 8-bytes function arguments must be 8-bytes aligned. 
llvm-svn: 34241
 2007-02-13 14:07:13 +00:00
Evan Cheng
af3b119b29 These vectors are frequently large. Use std::vector instead. 
llvm-svn: 34109
 2007-02-09 23:59:14 +00:00
Evan Cheng
5e8eb0c198 Add reference counting to constantpool entries. Delete the unused ones. 
llvm-svn: 34105
 2007-02-09 20:54:44 +00:00
Evan Cheng
dc15bc54a4 isLowRegister() expects input is a physical register. 
llvm-svn: 34013
 2007-02-07 21:44:33 +00:00
Evan Cheng
03ffd4a6d5 Rename. 
llvm-svn: 34011
 2007-02-07 21:24:09 +00:00
Evan Cheng
2bbe03a4df If sp offset will be materialized in a register. Clear the offset field of str / ldr. 
llvm-svn: 34010
 2007-02-07 21:19:58 +00:00
Evan Cheng
fe7242e9bb Get rid of references to iostream. 
llvm-svn: 34009
 2007-02-07 21:18:32 +00:00
Evan Cheng
808cf2b6a1 New entry. 
llvm-svn: 34000
 2007-02-07 09:22:15 +00:00
Evan Cheng
d5921e8a32 In thumb mode, R3 is reserved, but it can be live in to the function. If 
that is the case, whenever we use it as a scratch register, save it to R12
first and then restore it after the use.
This is a temporary and truly horrible workaround!

llvm-svn: 33999
 2007-02-07 09:17:36 +00:00
Evan Cheng
8f5c613d03 Update 
llvm-svn: 33998
 2007-02-07 08:37:57 +00:00
Evan Cheng
efeb81a8c4 - If fp (r7) is used to reference stack objects, use [r, r] address mode. 
- If there is a dynamic alloca, in the epilogue, restore the value of sp
  using r7 - offset.
- Other bug fixes.

llvm-svn: 33997
 2007-02-07 08:37:31 +00:00
Evan Cheng
b6cdeca59d eliminateFrameIndex() is even more complicated if frame ptr is used instead of SP when there are dynamic alloca's. 
llvm-svn: 33975
 2007-02-07 02:44:23 +00:00
Evan Cheng
60bde0ebb1 Spill / restore should avoid modifying the condition register. 
llvm-svn: 33971
 2007-02-07 00:06:56 +00:00
Evan Cheng
b3ff5f65d4 Select add FI, c correctly. 
llvm-svn: 33960
 2007-02-06 09:11:20 +00:00
Evan Cheng
1f1a01403a foldMemoryOperand() cannot fold tMOVrr sp into load / store in thumb mode. tLDRspi / tSTRspi cannot target / store high registers. 
llvm-svn: 33958
 2007-02-06 06:13:29 +00:00
Evan Cheng
119b5e3558 eliminateFrameIndex() bug when frame pointer is used as base register. 
llvm-svn: 33945
 2007-02-06 00:23:31 +00:00
Evan Cheng
c4ba711e91 - Store val, [sp, c] must be selected to tSTRsp. 
- If c does not fit in the offset field, materialize sp + c into a register
  using tADDhirr.

llvm-svn: 33944
 2007-02-06 00:22:06 +00:00
Evan Cheng
bf4ca3b491 ARM callseq_end should have a input flag operand so it would be scheduled right after the call. 
llvm-svn: 33832
 2007-02-03 09:11:58 +00:00
Evan Cheng
ece3d334c2 Fix comments. 
llvm-svn: 33831
 2007-02-03 08:53:01 +00:00
Evan Cheng
b4c6dfa3e7 - Branch max. displacement calculation bug. 
- Add debugging info.

llvm-svn: 33811
 2007-02-03 02:08:34 +00:00
Lauro Ramos Venancio
1b8a04e036 bugfix: SP isn't resetted when function has FP and there is no spills. 
llvm-svn: 33800
 2007-02-02 23:08:40 +00:00
Evan Cheng
d308af8c1f Another thumb large stack offset codegen bug. 
llvm-svn: 33795
 2007-02-02 21:08:39 +00:00
Evan Cheng
496c67ee3e Use MBB.empty() instead of MBB.size() for speed. 
llvm-svn: 33789
 2007-02-02 19:09:19 +00:00
Evan Cheng
6a428320d6 Watch out for empty BB. 
llvm-svn: 33788
 2007-02-02 18:49:02 +00:00
Evan Cheng
e450d1bfa4 Ugh. Only meant to do this in thumb mode. 
llvm-svn: 33780
 2007-02-02 08:58:48 +00:00
Chris Lattner
63479262b4 add a note 
llvm-svn: 33778
 2007-02-02 04:36:46 +00:00
Evan Cheng
689b0a4a62 Fix a bug in getARMCMP (which translate CondCode to ARM specific CC) when the RHS is a constant. 
llvm-svn: 33775
 2007-02-02 01:53:26 +00:00
Evan Cheng
73975a6076 Thumb does not have clz. 
llvm-svn: 33773
 2007-02-01 23:34:03 +00:00
Lauro Ramos Venancio
5765bcd825 Define PrivateGlobalPrefix for ARM Linux. (Fix CodeGen/ARM/large_stack.ll) 
llvm-svn: 33763
 2007-02-01 21:43:53 +00:00
Evan Cheng
3d9b702988 Pasto. Lots of it. 
llvm-svn: 33762
 2007-02-01 20:44:52 +00:00
Lauro Ramos Venancio
5781691b22 Fix .thumb_func directive on linux. 
llvm-svn: 33759
 2007-02-01 18:25:34 +00:00
Evan Cheng
88b703eec4 - Off by one bugs in maximum displacement calculation / testing. 
- In thumb mode, a new constpool island BB size should be 4 + 2 to
  compensate for the potential padding due to alignment requirement.

llvm-svn: 33753
 2007-02-01 10:16:15 +00:00
Evan Cheng
d3dc2eefc2 .set pc relative displacement bug: label should be moved down one instruction 
to just before the add r1, pc:

Before:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

Now:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
        mov r1, #PCRELV0
LPCRELL0:
        add r1, pc

llvm-svn: 33744
 2007-02-01 03:04:49 +00:00
Evan Cheng
eafe1f7bd9 Add a note. 
llvm-svn: 33743
 2007-02-01 02:46:20 +00:00
Evan Cheng
9f177f9058 Also set alignment of stack-based structs to 4 in thumb mode. 
llvm-svn: 33741
 2007-02-01 02:18:36 +00:00
Evan Cheng
439dcbedba Special epilogue for vararg functions. We cannot do a pop to pc because 
there follows a sp increment for the va register save region. Instead issue
a separate pop to another register, increment sp, and then return:
        pop {r4, r5, r6, r7}
        pop {r3}
        add sp, #3 * 4
        bx r3

llvm-svn: 33739
 2007-02-01 01:49:46 +00:00
Evan Cheng
9f87fca49c Pessmistically assume the .align 2 before the first constpool entry adds 
two bytes padding.

llvm-svn: 33734
 2007-02-01 01:09:47 +00:00
Evan Cheng
3d8d381600 Possible JT improvements. 
llvm-svn: 33733
 2007-02-01 01:07:48 +00:00
Evan Cheng
54a1324bae Don't emit unnecessary .align directive. 
llvm-svn: 33729
 2007-01-31 23:39:39 +00:00
Evan Cheng
765de99fac Handle an interesting corner case: the constpool_entry being reference is two 
instructions away, i.e. its address is equal to PC.
        %r0 = tLDRpci <cp#0>
        bx
        CONSTPOOL_ENTRY 0 <cp#0>, 4

llvm-svn: 33728
 2007-01-31 23:35:18 +00:00
Evan Cheng
082e441207 Don't want to add FramePtr to callee save spill list twice. 
llvm-svn: 33727
 2007-01-31 23:17:29 +00:00
Evan Cheng
457d429cab Darwin ABI requires FP to point to stack slot of prev FP. 
llvm-svn: 33724
 2007-01-31 22:25:33 +00:00
Evan Cheng
0ce094c7a8 Add entry. 
llvm-svn: 33723
 2007-01-31 22:11:38 +00:00
Evan Cheng
41bee13a0e Thumb add sp, #imm requires the immediate value be multiple of 4. For now, 
change preferred alignment of short, byte, bool to 4.

llvm-svn: 33722
 2007-01-31 22:08:40 +00:00
Evan Cheng
476cd5c2d1 Update comment. 
llvm-svn: 33721
 2007-01-31 22:06:44 +00:00
Evan Cheng
a08ef111bb Thumb asm syntax does not want 's' suffix for flag setting opcodes. 
llvm-svn: 33717
 2007-01-31 20:12:31 +00:00
Evan Cheng
1df8529721 When determining whether a pc relative branch / load displacement fits in the 
instruction field, adjust it for PC value (4 for thumb, 8 for arm).

llvm-svn: 33711
 2007-01-31 19:57:44 +00:00
Evan Cheng
f6e0e6cada Some comments. 
llvm-svn: 33707
 2007-01-31 18:29:27 +00:00
Evan Cheng
16edf4f9bf ConstPool island bug: watch out for cases where UserMI is the last MI of the BB. 
llvm-svn: 33706
 2007-01-31 18:19:07 +00:00
Lauro Ramos Venancio
e22bc8635e ARM fix: Miscompilation when frame pointer can't be eliminated. Uninitialized frame pointer register is used. 
llvm-svn: 33703
 2007-01-31 13:12:46 +00:00
Evan Cheng
608ad034b0 Specify the right CC for comparison libcalls. 
llvm-svn: 33702
 2007-01-31 09:30:58 +00:00
Evan Cheng
e5f5439313 Observe -soft-float. 
llvm-svn: 33699
 2007-01-31 08:40:13 +00:00
Evan Cheng
0ee9a27976 - Added Thumb constpool island support. 
- Islands are inserted right after the user MI since thumb LDR cannot encode
  negative offset.

llvm-svn: 33690
 2007-01-31 02:22:22 +00:00
Evan Cheng
26ee4f882b During PEI, if the immediate value of sp + offset is too large (i.e. something 
that would require > 3 instructions to materialize), load the immediate from a
constpool entry.

llvm-svn: 33667
 2007-01-30 23:01:46 +00:00
Evan Cheng
0f07707270 - Fix codegen for pc relative constant (e.g. JT) in thumb mode: 
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

- In thumb mode, it's not possible to use .set generate a pc relative stub
  address. The stub is ARM code which is in a different section from the thumb
  code. Load the value from a constpool instead.
- Some asm printing clean up.

llvm-svn: 33664
 2007-01-30 20:37:08 +00:00
Reid Spencer
19af04a142 For PR1136: Rename GlobalVariable::isExternal as isDeclaration to avoid 
confusion with external linkage types.

llvm-svn: 33663
 2007-01-30 20:08:39 +00:00
Evan Cheng
5e0f0364d0 Copy and paste bug. 
llvm-svn: 33658
 2007-01-30 08:22:33 +00:00
Evan Cheng
3f02e5b1e7 Darwin -static should codegen static ctors / dtors to .constructor / .destructor sections. 
llvm-svn: 33657
 2007-01-30 08:04:53 +00:00
Evan Cheng
78628c7f32 Misseed thumb jumptable branch. 
llvm-svn: 33656
 2007-01-30 08:03:06 +00:00
Evan Cheng
d0ed3f753b In thumb mode, round up stack frame size to multiple of 4 since add/sub 
sp, imm instructions implicitly multiply the offset by 4.

llvm-svn: 33653
 2007-01-30 02:57:02 +00:00
Evan Cheng
36f03730d0 Thumb eliminateFrameIndex fixes. 
llvm-svn: 33652
 2007-01-30 02:36:01 +00:00
Evan Cheng
99a2f7d598 Change the operand orders to t_addrmode_s* to make it easier to morph 
instructions that use these address modes to instructions that use
t_addrmode_sp.

llvm-svn: 33651
 2007-01-30 02:35:32 +00:00
Evan Cheng
91ad06dd75 - In thumb mode, if size of MachineFunction is >= 2048, force LR to be 
spilled (if it is not already).
- If LR is spilled, use BL to implement far jumps. LR is not used as a GPR
  in thumb mode so it can be clobbered if it is properly spilled / restored
  in prologue / epilogue.
- If LR is force spilled but no far jump has been emitted, try undo'ing the
  spill by:
  push lr -> delete
  pop pc -> bx lr

llvm-svn: 33650
 2007-01-30 01:18:38 +00:00
Evan Cheng
a16118a6cf Use BL to implement Thumb far jumps. 
llvm-svn: 33649
 2007-01-30 01:13:37 +00:00
Evan Cheng
171943e26e Factor GetInstSize() out of constpool island pass. 
llvm-svn: 33644
 2007-01-29 23:45:17 +00:00
Nate Begeman
dc46021355 Finish off bug 680, allowing targets to custom lower frame and return 
address nodes.

llvm-svn: 33636
 2007-01-29 22:58:52 +00:00
Evan Cheng
903e98b477 Comment. 
llvm-svn: 33633
 2007-01-29 22:23:02 +00:00
Evan Cheng
fe602cabee Remember if LR register has been spilled in this function. 
llvm-svn: 33632
 2007-01-29 22:22:24 +00:00
Anton Korobeynikov
611d5e2eda Propagate changes from my local tree. This patch includes: 
1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.

NOTEs: 1. Documentation will be updated soon.
       2. llvm-upgrade should be improved to translate csret => sret.
          Before this, there will be some unexpected test fails.
llvm-svn: 33597
 2007-01-28 13:31:35 +00:00
Evan Cheng
e0dc07a83f New entry. 
llvm-svn: 33569
 2007-01-27 02:33:22 +00:00
Evan Cheng
4618d3131c Thumb jumptable support. 
llvm-svn: 33568
 2007-01-27 02:29:45 +00:00
Evan Cheng
9805b66063 Thumb add / sub with carry. 
llvm-svn: 33562
 2007-01-27 00:07:15 +00:00
Lauro Ramos Venancio
f1f9f05230 Some asm directives fixes for ELF. 
Now we can compile llvm-gcc on arm-linux-gnueabi!

llvm-svn: 33558
 2007-01-26 23:24:43 +00:00
Evan Cheng
55455f0532 Represent tADDspi and tSUBspi as two-address instructions. 
llvm-svn: 33551
 2007-01-26 21:33:19 +00:00
Jim Laskey
64f4242072 Change the MachineDebugInfo to MachineModuleInfo to better reflect usage 
for debugging and exception handling.

llvm-svn: 33550
 2007-01-26 21:22:28 +00:00
Lauro Ramos Venancio
762787bed7 Fix Data16bitsDirective for ELF. 
llvm-svn: 33549
 2007-01-26 21:20:45 +00:00
Evan Cheng
2b4f267d57 Conditional branch being fixed up is not the last MI in the BB, there is a 
unconditional branch following it. Simply invert the condition and swap
destinations if the conditional branch can reach the destination of the
unconditional branch:
beq L1
b   L2
=>
bne L2
b   L1

llvm-svn: 33548
 2007-01-26 20:38:26 +00:00
Lauro Ramos Venancio
ea815a6137 If the constant pool value is a extern weak symbol, emit the weak reference. 
llvm-svn: 33543
 2007-01-26 19:51:32 +00:00
Evan Cheng
d0c39ef1ca extload -> zextload 
llvm-svn: 33542
 2007-01-26 19:13:16 +00:00
Jim Laskey
23ed7d2625 Make LABEL a builtin opcode. 
llvm-svn: 33537
 2007-01-26 14:34:52 +00:00
Evan Cheng
c81bceda82 SplitBlockBeforeInstr() insert a unconditional branch to the next BB. This 
is unnecessary when we are fixing up a conditional branch since we will be
adding a unconditional branch to the destination of the original branch.

llvm-svn: 33517
 2007-01-26 02:02:39 +00:00
Evan Cheng
c5a454b111 Need to scan the function for branches even if there aren't any constants. 
llvm-svn: 33515
 2007-01-26 01:04:44 +00:00
Evan Cheng
6a46a78547 Forgot to update this. 
llvm-svn: 33512
 2007-01-25 23:31:04 +00:00
Evan Cheng
a229bc12be Add comment, fix typo, reduce memory usage, etc. 
llvm-svn: 33510
 2007-01-25 23:18:59 +00:00
Evan Cheng
a47f2cc065 I am an idiot. 
llvm-svn: 33509
 2007-01-25 23:18:16 +00:00
Lauro Ramos Venancio
a3788dc56b Fix elf object definition. 
llvm-svn: 33502
 2007-01-25 20:11:04 +00:00
Evan Cheng
7dccb7be86 Doh. Skip JT branches. 
llvm-svn: 33501
 2007-01-25 19:43:52 +00:00
Evan Cheng
d7c809c7be Added (preliminary) branch shortening capability to constantpool island pass. 
llvm-svn: 33497
 2007-01-25 03:12:46 +00:00
Evan Cheng
9d937d1065 Getting rid uses of evil std::set<> 
llvm-svn: 33496
 2007-01-25 03:07:27 +00:00
Evan Cheng
c6db78ab84 Use PC relative ldr to load from a constantpool in Thumb mode. 
llvm-svn: 33484
 2007-01-24 08:53:17 +00:00
Evan Cheng
1630c86beb Allow [ fi#c, imm ] as ARM load / store addresses. 
llvm-svn: 33474
 2007-01-24 02:45:25 +00:00
Evan Cheng
fa613cdd06 Various Thumb mode load / store isel bug fixes. 
llvm-svn: 33472
 2007-01-24 02:21:22 +00:00
Evan Cheng
5f947e4e2f - Reorg Thumb load / store instructions. Combine each rr and ri pair of 
instructions into one (e.g. tLDRrr, tLDRri -> tLDR).
- Thumb ldrsb and ldrsh only have the [reg, reg] address format. If the
  address is not an add, materialize a 0 immediate into a register and use
  it as the offset field.

llvm-svn: 33470
 2007-01-23 22:59:13 +00:00
Evan Cheng
dc97533dd3 Darwin HiddenDirective is .private_extern. 
llvm-svn: 33465
 2007-01-23 19:06:03 +00:00
Evan Cheng
b6a4a7f72a PEI is now responsible for adding MaxCallFrameSize to frame size and align the stack. Each target can further adjust the frame size if necessary. 
llvm-svn: 33460
 2007-01-23 09:38:11 +00:00
Evan Cheng
d9d93832b0 hasFP() is now a virtual method of MRegisterInfo. 
llvm-svn: 33455
 2007-01-23 00:57:47 +00:00
Evan Cheng
25584afca7 ARM AAPCS abi (Linux, etc.) requires 8-byte double / long alignment; Mac 
requires 4-bytes alignment.

llvm-svn: 33448
 2007-01-22 23:13:01 +00:00
Evan Cheng
b55dabdc80 Double and Long preferred alignment is 4 for Darwin, 8 for Linux. 
llvm-svn: 33440
 2007-01-22 21:24:13 +00:00
Evan Cheng
30ef170ddf Use bl to call Thumb fuctions directly. 
llvm-svn: 33433
 2007-01-22 19:40:10 +00:00
Evan Cheng
6271410520 Round up stack to multiple of alignment only if it's a leaf function without alloca. 
llvm-svn: 33401
 2007-01-20 10:22:33 +00:00
Evan Cheng
5ea6a8d9e4 Prologue and epilogue bugs for non-Darwin targets. 
llvm-svn: 33390
 2007-01-20 03:24:07 +00:00
Evan Cheng
a6803554ab Clean up ARM PEI code. 
llvm-svn: 33389
 2007-01-20 02:09:25 +00:00
Evan Cheng
5d0be572b5 Code clean up. Use def : pat instead of defining new instructions. 
llvm-svn: 33368
 2007-01-19 20:27:35 +00:00
Evan Cheng
51292f4863 isDarwin -> isTargetDarwin 
llvm-svn: 33366
 2007-01-19 19:28:01 +00:00
Evan Cheng
99725bd310 Restructure code a bit to make use of continue (simplifying things). Generalize 
the .zerofill directive emission to not be darwin-specific.

llvm-svn: 33365
 2007-01-19 19:25:36 +00:00
Evan Cheng
025816f18c Darwin doesn't support .bss, but it does have .zerofill 
llvm-svn: 33364
 2007-01-19 19:23:47 +00:00
Evan Cheng
b1a4190523 Introduce TargetType's ELF and Darwin. 
llvm-svn: 33363
 2007-01-19 19:22:40 +00:00
Evan Cheng
9203bd4339 Modify emission of jump tables on darwin to emit an extra "l" label that 
delimits the boundaries of jump tables.  This lets the linker's dead code
stripping optimization do a better job.

llvm-svn: 33362
 2007-01-19 18:59:56 +00:00
Lauro Ramos Venancio
f53f62b91d Fix section definition. 
llvm-svn: 33359
 2007-01-19 17:33:22 +00:00
Evan Cheng
c6e1d453d3 ARM backend contribution from Apple. 
llvm-svn: 33353
 2007-01-19 07:51:42 +00:00
Lauro Ramos Venancio
14cf9f2c03 Don't add or sub zero to sp. 
llvm-svn: 33142
 2007-01-12 20:52:27 +00:00
Lauro Ramos Venancio
97e120a71c Build constants using instructions mov/orr or mvn/eor. 
llvm-svn: 33141
 2007-01-12 20:35:49 +00:00
Lauro Ramos Venancio
078b85bdaa Expand SELECT (f32/f64) and FCOPYSIGN (f32/f64). 
llvm-svn: 32870
 2007-01-04 14:01:38 +00:00
Evan Cheng
bd6a333b52 Fix naming inconsistency. 
llvm-svn: 32823
 2007-01-02 21:33:40 +00:00
Rafael Espindola
d1baea3471 implement missing compares 
patch by Lauro
bug fixed by me

llvm-svn: 32795
 2006-12-31 18:52:39 +00:00
Reid Spencer
dda168599d For PR950: 
Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
   type of an function parameter was used to determine whether it should
   be sign extended or zero extended before the call. This information is
   now communicated via the function type's parameter attributes.
3. The interface to LowerCallTo had to be changed in order to accommodate
   the parameter attribute information. Although it would have been
   convenient to pass in the FunctionType itself, there isn't always one
   present in the caller. Consequently, a signedness indication for the
   result type and for each parameter was provided for in the interface
   to this method. All implementations were changed to make the adjustment
   necessary.

llvm-svn: 32788
 2006-12-31 05:55:36 +00:00
Rafael Espindola
16af307d42 fix comment 
llvm-svn: 32767
 2006-12-29 14:28:12 +00:00
Lauro Ramos Venancio
c87ce8ee4b Define StaticCtorsSection and StaticDtorsSection for ARM. 
llvm-svn: 32763
 2006-12-28 13:13:00 +00:00
Lauro Ramos Venancio
7bfe536783 Implement SELECT_CC (f32/f64) for ARM. 
llvm-svn: 32762
 2006-12-28 13:11:14 +00:00
Rafael Espindola
da5b9584ce remove duplicated line 
bug noticed by Lauro

llvm-svn: 32761
 2006-12-28 12:51:40 +00:00
Lauro Ramos Venancio
2cde823f98 This patch defines extloadi1 and fixes an internal compiler error on 
arm.

llvm-svn: 32760
 2006-12-26 19:30:42 +00:00
Chris Lattner
fd16bf61d8 Fix for ARM weak symbols, patch by Lauro Ramos Venancio! 
llvm-svn: 32740
 2006-12-21 22:59:58 +00:00
Chris Lattner
8896b6cb46 eliminate static ctors for Statistic objects. 
llvm-svn: 32703
 2006-12-19 22:59:26 +00:00
Rafael Espindola
05b3447706 macros -> Inline functions 
Lauros's patch

llvm-svn: 32656
 2006-12-18 11:07:09 +00:00
Rafael Espindola
08c0825f18 move ExtWeakSymbols to AsmPrinter 
llvm-svn: 32648
 2006-12-18 03:37:18 +00:00
Rafael Espindola
d19ea53887 avoid using a constant table when a constant can be used inline 
llvm-svn: 32580
 2006-12-14 18:58:37 +00:00
Rafael Espindola
0d92ae76fb Avoid creating invalid sub/add instructions on the prolog/epilog 
patch by Lauro

llvm-svn: 32577
 2006-12-14 13:31:27 +00:00
Rafael Espindola
7c4245c4e3 more general matching of the MVN instruction 
llvm-svn: 32484
 2006-12-12 17:10:13 +00:00
Rafael Espindola
a65fd68f23 don't use "ordinary" addressing mode 1 when mvn is appropriate 
llvm-svn: 32482
 2006-12-12 14:03:29 +00:00
Rafael Espindola
d29cb12dfc use MVN to handle small negative constants 
llvm-svn: 32459
 2006-12-12 01:03:11 +00:00
Rafael Espindola
b8163fd828 add mvn 
llvm-svn: 32454
 2006-12-12 00:37:38 +00:00
Rafael Espindola
e3aafd29a9 add note 
llvm-svn: 32452
 2006-12-11 23:56:10 +00:00
Rafael Espindola
9fe91fc84f .align is in bits 
.comm is in bytes
:-(

llvm-svn: 32408
 2006-12-10 02:53:14 +00:00
Rafael Espindola
620b3430c8 %progbits not @progbits 
llvm-svn: 32376
 2006-12-08 22:06:02 +00:00
Rafael Espindola
7e99603152 add \"aw\",@progbits" to ctors and dtors 
llvm-svn: 32373
 2006-12-08 21:24:58 +00:00
Rafael Espindola
514fcabb29 fix truncstorei1 
llvm-svn: 32364
 2006-12-08 18:41:21 +00:00
Rafael Espindola
bb753d7121 fix alignment 
llvm-svn: 32337
 2006-12-07 22:38:06 +00:00
Bill Wendling
f13d78d3b8 What should be the last unnecessary <iostream>s in the library. 
llvm-svn: 32333
 2006-12-07 22:21:48 +00:00
Rafael Espindola
a908b2dfd9 make sure that we don't use a common symbol if a section was specified 
llvm-svn: 32310
 2006-12-07 18:33:58 +00:00
Chris Lattner
a531ce882e Detemplatize the Statistic class. The only type it is instantiated with 
is 'unsigned'.

llvm-svn: 32279
 2006-12-06 17:46:33 +00:00
Rafael Espindola
7ad537568f print weak references 
llvm-svn: 32276
 2006-12-06 13:35:10 +00:00
Chris Lattner
fd152e4ed6 These asm printers shouldn't use assembly/writer.h 
llvm-svn: 32262
 2006-12-06 06:13:25 +00:00
Rafael Espindola
5e8a6ca4c0 expand memmove and memcpy 
llvm-svn: 32226
 2006-12-05 17:57:23 +00:00
Rafael Espindola
38062acebb add support for the "r" asm constraint 
patch by Lauro Ramos Venancio

llvm-svn: 32224
 2006-12-05 17:37:31 +00:00
Rafael Espindola
da1fffc4e1 add support for weak linkage 
llvm-svn: 32222
 2006-12-05 17:00:17 +00:00
Evan Cheng
98fa7ab4d7 Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 
of opcode and number of operands.

llvm-svn: 31947
 2006-11-27 23:37:22 +00:00
Rafael Espindola
5daebfdae0 implement load effective address similar to the alpha backend 
remove lea_addri and the now unused memri addressing mode

llvm-svn: 31592
 2006-11-09 13:58:55 +00:00
Evan Cheng
736a8eb3cd Match tblegen changes. 
llvm-svn: 31571
 2006-11-08 20:34:28 +00:00
Rafael Espindola
f7b898d497 initial implementation of addressing mode 2 
TODO: fix lea_addri

llvm-svn: 31552
 2006-11-08 17:07:32 +00:00
Chris Lattner
7c265ad682 remove dead/redundant vars 
llvm-svn: 31435
 2006-11-03 23:48:56 +00:00
Rafael Espindola
3459a4b85b revert previous patch 
llvm-svn: 31411
 2006-11-03 03:08:28 +00:00
Rafael Espindola
5cfe91aaca add createCFGSimplificationPass to ARMTargetMachine::addInstSelector 
llvm-svn: 31400
 2006-11-03 01:39:25 +00:00
Rafael Espindola
04afe6eb37 move ARMCondCodeToString to ARMAsmPrinter.cpp 
remove unused variables from lowerCall

llvm-svn: 31378
 2006-11-02 15:00:02 +00:00
Rafael Espindola
3ae2b33d17 print null values in bss 
llvm-svn: 31349
 2006-11-01 14:26:44 +00:00
Rafael Espindola
a52f709418 implement zextload bool and truncstore bool 
llvm-svn: 31348
 2006-11-01 14:13:27 +00:00
Rafael Espindola
ba8771a3db add support for calling functions when the caller has variable sized objects 
llvm-svn: 31312
 2006-10-31 13:03:26 +00:00
Evan Cheng
5766dd6455 All targets expand BR_JT for now. 
llvm-svn: 31294
 2006-10-30 08:02:39 +00:00
Rafael Espindola
99322ef58c initial support for frame pointers 
llvm-svn: 31197
 2006-10-26 13:31:26 +00:00
Rafael Espindola
a962656c07 expand ISD::VACOPY 
llvm-svn: 31170
 2006-10-24 20:15:21 +00:00
Rafael Espindola
2259fab5cf fix warning about missing newline at end of file 
llvm-svn: 31162
 2006-10-24 17:07:11 +00:00
Chris Lattner
71dc932fcb implement uncond branch insertion, mark branches with isBranch. 
llvm-svn: 31160
 2006-10-24 16:47:57 +00:00
Rafael Espindola
70f01d5cc0 implement STRB and STRH 
llvm-svn: 31138
 2006-10-23 20:34:27 +00:00
Rafael Espindola
357f151d9d expand ISD::MEMSET 
llvm-svn: 31137
 2006-10-23 20:08:22 +00:00
Reid Spencer
d414793dbc For PR950: 
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.

llvm-svn: 31063
 2006-10-20 07:07:24 +00:00
Rafael Espindola
c08546401b use Pat to implement extloadi8 and extloadi16 
llvm-svn: 31052
 2006-10-19 17:05:03 +00:00
Rafael Espindola
35e92188e0 implement undef 
llvm-svn: 31049
 2006-10-19 13:45:00 +00:00
Rafael Espindola
f7a41f3ddd print common symbols 
llvm-svn: 31048
 2006-10-19 13:30:40 +00:00
Rafael Espindola
722266845b implement extloadi8 and extloadi16 
llvm-svn: 31047
 2006-10-19 12:45:04 +00:00
Rafael Espindola
17544c1c1d expand SIGN_EXTEND_INREG 
llvm-svn: 31046
 2006-10-19 12:06:50 +00:00
Rafael Espindola
6cc20c7950 expand brind so that we don't have to implement jump tables right now 
llvm-svn: 31045
 2006-10-19 10:56:43 +00:00
Rafael Espindola
1220d18e11 add blx 
llvm-svn: 31037
 2006-10-18 16:21:43 +00:00
Rafael Espindola
73e8f41749 add isTerminatortto b and bcond 
llvm-svn: 31036
 2006-10-18 16:20:57 +00:00
Rafael Espindola
80c7461ada implement CallingConv::Fast as CallingConv::C 
llvm-svn: 31034
 2006-10-18 12:03:07 +00:00
Rafael Espindola
58233f9db2 expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM 
llvm-svn: 31014
 2006-10-17 21:05:33 +00:00
Rafael Espindola
4e8824608e add the FPUnaryOp and DFPUnaryOp classes 
llvm-svn: 31013
 2006-10-17 20:45:22 +00:00
Rafael Espindola
fe0a9a6fe2 add FABSS and FABSD 
llvm-svn: 31012
 2006-10-17 20:33:13 +00:00
Rafael Espindola
64f93033bc remove extra [] in stores 
llvm-svn: 31008
 2006-10-17 18:29:14 +00:00
Rafael Espindola
47970f96ac initial implementation of addressing mode 5 
llvm-svn: 31002
 2006-10-17 18:04:53 +00:00
Rafael Espindola
d5a6eaec14 add the immediate to the Offset in eliminateFrameIndex 
llvm-svn: 30998
 2006-10-17 14:34:02 +00:00
Rafael Espindola
31f59f5b94 add FSTD and FSTS 
llvm-svn: 30996
 2006-10-17 13:36:07 +00:00
Rafael Espindola
01400015fc add FCPYS and FCPYD 
llvm-svn: 30995
 2006-10-17 13:13:23 +00:00
Rafael Espindola
a156538e34 add fdivs e fdivd 
llvm-svn: 30988
 2006-10-16 21:50:04 +00:00
Rafael Espindola
4f61431679 expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS 
llvm-svn: 30987
 2006-10-16 21:10:32 +00:00
Rafael Espindola
25fbeb5ec2 define the DFPBinOp class 
llvm-svn: 30981
 2006-10-16 18:39:22 +00:00
Rafael Espindola
57dc40a3a8 add the FPBinOp class 
llvm-svn: 30980
 2006-10-16 18:32:36 +00:00
Rafael Espindola
8a40de94f2 define the Addr1BinOp class 
llvm-svn: 30979
 2006-10-16 18:18:14 +00:00
Rafael Espindola
6554b1014d define the IntBinOp class and use it to implement the multiply instructions 
llvm-svn: 30978
 2006-10-16 17:57:20 +00:00
Rafael Espindola
71ae8c3d4a fix assembly syntax 
llvm-svn: 30977
 2006-10-16 17:38:12 +00:00
Rafael Espindola
d255bfb09b implement LDRB, LDRSB, LDRH and LDRSH 
llvm-svn: 30976
 2006-10-16 17:17:22 +00:00
Rafael Espindola
93359fa883 implement smull and umull 
llvm-svn: 30975
 2006-10-16 16:33:29 +00:00
Rafael Espindola
c426cede28 expand ISD::BRCOND 
llvm-svn: 30963
 2006-10-14 17:59:54 +00:00
Rafael Espindola
38c602f658 fix some fp condition codes 
use non trapping comparison instructions

llvm-svn: 30962
 2006-10-14 13:42:53 +00:00
Evan Cheng
fe5bb5dbe6 Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. 
llvm-svn: 30945
 2006-10-13 21:14:26 +00:00
Rafael Espindola
1f85e7a2a1 add FNEGS and FNEGD 
llvm-svn: 30932
 2006-10-13 17:37:35 +00:00
Rafael Espindola
042e61af25 add SBCS and SUBS 
llvm-svn: 30930
 2006-10-13 17:19:20 +00:00
Rafael Espindola
24d7976d1d implement calls to functions that return long 
llvm-svn: 30929
 2006-10-13 16:47:22 +00:00
Rafael Espindola
bd50a4d757 implement unordered floating point compares 
llvm-svn: 30928
 2006-10-13 13:14:59 +00:00
Chris Lattner
b7ff3d59f7 mark call adjustments as modifying the SP 
llvm-svn: 30911
 2006-10-12 18:00:26 +00:00
Evan Cheng
ca66f49574 Add properties to ComplexPattern. 
llvm-svn: 30891
 2006-10-11 21:03:53 +00:00
Rafael Espindola
46e7aceb1d uint <-> double conversion 
llvm-svn: 30862
 2006-10-10 20:38:57 +00:00
Rafael Espindola
0112351e9a add fp sub 
llvm-svn: 30859
 2006-10-10 19:35:01 +00:00
Rafael Espindola
27d68a3c22 add double <-> int conversion 
llvm-svn: 30858
 2006-10-10 18:55:14 +00:00
Rafael Espindola
413aa20bc8 compare doubles 
llvm-svn: 30856
 2006-10-10 16:33:47 +00:00
Rafael Espindola
b0719f1374 initial support for fp compares. Unordered compares not implemented yet 
llvm-svn: 30854
 2006-10-10 12:56:00 +00:00
Evan Cheng
d22f3dd3ed Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. 
llvm-svn: 30844
 2006-10-09 20:57:25 +00:00
Rafael Espindola
bae07b25d6 add float -> double and double -> float conversion 
llvm-svn: 30835
 2006-10-09 17:50:29 +00:00
Rafael Espindola
f917f096e2 add ADDS and ADCS 
llvm-svn: 30830
 2006-10-09 17:18:28 +00:00
Rafael Espindola
319b5e9c95 expand ISD::SELECT 
llvm-svn: 30829
 2006-10-09 16:28:33 +00:00
Rafael Espindola
fed11f040c add a note 
llvm-svn: 30828
 2006-10-09 14:18:33 +00:00
Rafael Espindola
aaeadcb6f5 expand ISD::EXTLOAD 
llvm-svn: 30827
 2006-10-09 14:13:40 +00:00
Rafael Espindola
1e16a7e972 most ARM targets are little endian 
llvm-svn: 30826
 2006-10-09 14:12:15 +00:00
Rafael Espindola
38e9e2e01d implement FUITOS and FUITOD 
llvm-svn: 30803
 2006-10-07 14:24:52 +00:00
Rafael Espindola
90a24709fb implement FLDD 
llvm-svn: 30802
 2006-10-07 14:03:39 +00:00
Rafael Espindola
b8ce0f8bbd implement fadds, faddd, fmuls and fmuld 
llvm-svn: 30801
 2006-10-07 13:46:42 +00:00
Rafael Espindola
a96c205e12 add optional input flag to FMRRD 
llvm-svn: 30774
 2006-10-06 20:33:26 +00:00
Rafael Espindola
54301ca490 add support for calling functions that return double 
llvm-svn: 30771
 2006-10-06 19:10:05 +00:00
Rafael Espindola
d870b158b3 fix some bugs affecting functions with no arguments 
llvm-svn: 30767
 2006-10-06 17:26:30 +00:00
Rafael Espindola
f35563ff66 fix the stack alignment 
llvm-svn: 30766
 2006-10-06 14:29:47 +00:00
Rafael Espindola
f679bdf121 add support for calling functions that have double arguments 
llvm-svn: 30765
 2006-10-06 12:50:22 +00:00
Evan Cheng
275825195a Make use of getStore(). 
llvm-svn: 30759
 2006-10-05 23:01:46 +00:00
Rafael Espindola
2e4743b6d1 use a const ref for passing the vector to ArgumentLayout 
llvm-svn: 30756
 2006-10-05 17:46:48 +00:00
Rafael Espindola
f0e4950ef4 implement a ArgumentLayout class to factor code common to LowerFORMAL_ARGUMENTS and LowerCALL 
implement FMDRR
add support for f64 function arguments

llvm-svn: 30754
 2006-10-05 16:48:49 +00:00
Chris Lattner
068190eb91 Pass the MachineFunction into EmitJumpTableInfo. 
llvm-svn: 30742
 2006-10-05 03:01:21 +00:00
Chris Lattner
cc21d20348 Use getSectionForFunction. 
llvm-svn: 30740
 2006-10-05 02:49:23 +00:00
Rafael Espindola
b77754ce4d Implement floating point constants 
llvm-svn: 30704
 2006-10-03 17:27:58 +00:00
Rafael Espindola
36c3e0028b fix the names of the 64bit fp register 
initial support for returning 64bit floating point numbers

llvm-svn: 30692
 2006-10-02 19:30:56 +00:00
Rafael Espindola
1b39270c95 add floating point registers 
implement SINT_TO_FP

llvm-svn: 30673
 2006-09-29 21:20:16 +00:00
Rafael Espindola
9cfd72a3d1 add a note 
llvm-svn: 30581
 2006-09-22 11:36:17 +00:00
Rafael Espindola
a51ec7153c more condition codes 
llvm-svn: 30567
 2006-09-21 13:06:26 +00:00
Rafael Espindola
4de4f87be5 if a constant can't be an immediate, add it to the constant pool 
llvm-svn: 30566
 2006-09-21 11:29:52 +00:00
Rafael Espindola
cd52f85028 fix header 
add comments
untabify

llvm-svn: 30486
 2006-09-19 16:41:40 +00:00
Rafael Espindola
6c7627e002 Implement a MachineFunctionPass to fix the mul instruction 
llvm-svn: 30485
 2006-09-19 15:49:25 +00:00
Rafael Espindola
1a3020bfcf add shifts to addressing mode 1 
llvm-svn: 30291
 2006-09-13 12:09:43 +00:00
Evan Cheng
dd52a60189 Reflects MachineConstantPoolEntry changes. 
llvm-svn: 30279
 2006-09-12 21:04:05 +00:00
Rafael Espindola
7722bae67e implement SRL and MUL 
llvm-svn: 30262
 2006-09-11 19:24:19 +00:00
Rafael Espindola
d8b1142d79 add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1 
llvm-svn: 30261
 2006-09-11 19:23:32 +00:00