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llvm-mirror/lib/Target/ARM/ARMInstrInfo.td

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ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
added a skeleton of the ARM backend llvm-svn: 28301
2006-05-15 00:18:28 +02:00
//
Update the file headers across all of the LLVM projects in the monorepo to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2019-01-19 09:50:56 +01:00
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
added a skeleton of the ARM backend llvm-svn: 28301
2006-05-15 00:18:28 +02:00
//
//===----------------------------------------------------------------------===//
//
// This file describes the ARM instructions in TableGen format.
//
//===----------------------------------------------------------------------===//
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
//===----------------------------------------------------------------------===//
// ARM specific DAG Nodes.
//
// Type profiles.
Add extra operand to CALLSEQ_START to keep frame part set up previously Using arguments with attribute inalloca creates problems for verification of machine representation. This attribute instructs the backend that the argument is prepared in stack prior to CALLSEQ_START..CALLSEQ_END sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size stored in CALLSEQ_START in this case does not count the size of this argument. However CALLSEQ_END still keeps total frame size, as caller can be responsible for cleanup of entire frame. So CALLSEQ_START and CALLSEQ_END keep different frame size and the difference is treated by MachineVerifier as stack error. Currently there is no way to distinguish this case from actual errors. This patch adds additional argument to CALLSEQ_START and its target-specific counterparts to keep size of stack that is set up prior to the call frame sequence. This argument allows MachineVerifier to calculate actual frame size associated with frame setup instruction and correctly process the case of inalloca arguments. The changes made by the patch are: - Frame setup instructions get the second mandatory argument. It affects all targets that use frame pseudo instructions and touched many files although the changes are uniform. - Access to frame properties are implemented using special instructions rather than calls getOperand(N).getImm(). For X86 and ARM such replacement was made previously. - Changes that reflect appearance of additional argument of frame setup instruction. These involve proper instruction initialization and methods that access instruction arguments. - MachineVerifier retrieves frame size using method, which reports sum of frame parts initialized inside frame instruction pair and outside it. The patch implements approach proposed by Quentin Colombet in https://bugs.llvm.org/show_bug.cgi?id=27481#c1. It fixes 9 tests failed with machine verifier enabled and listed in PR27481. Differential Revision: https://reviews.llvm.org/D32394 llvm-svn: 302527
2017-05-09 15:35:13 +02:00
def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
SDTCisVT<1, i32> ]>;
Unifacalize the CALLSEQ{START,END} stuff. llvm-svn: 44045
2007-11-13 10:19:02 +01:00
def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
ARM: properly handle alignment for struct byval. Factor out the expansion code into a function. This change is to be enabled in clang. rdar://9877866 llvm-svn: 157830
2012-06-01 21:33:18 +02:00
def SDT_ARMStructByVal : SDTypeProfile<0, 4,
ARM: support struct byval in llvm We handle struct byval by inserting a pseudo op, which will be expanded to a loop at ExpandISelPseudos. A separate patch for clang will be submitted to enable struct byval. rdar://9877866 llvm-svn: 157793
2012-06-01 04:44:42 +02:00
[SDTCisVT<0, i32>, SDTCisVT<1, i32>,
ARM: properly handle alignment for struct byval. Factor out the expansion code into a function. This change is to be enabled in clang. rdar://9877866 llvm-svn: 157830
2012-06-01 21:33:18 +02:00
SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
fix a bunch of partially ambiguous patterns on ARM. As an example, this: (set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin)) is ambiguous because DPR contains both f64 and v2f32. tblgen currently accidentally picks f64 because it's first in the regclass. llvm-svn: 97955
2010-03-08 19:51:21 +01:00
def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
def SDT_ARMCMov : SDTypeProfile<1, 3,
[SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
SDTCisVT<3, i32>]>;
def SDT_ARMBrcond : SDTypeProfile<0, 2,
[SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
ARM: remove custom jump table UID We were creating and propagating two separate indices for each jump table (from back in the mists of time). However, the generic index used by other backends is sufficient to emit a unique symbol so this was unneeded. llvm-svn: 237294
2015-05-13 22:28:38 +02:00
def SDT_ARMBrJT : SDTypeProfile<0, 2,
[SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
ARM: remove custom jump table UID We were creating and propagating two separate indices for each jump table (from back in the mists of time). However, the generic index used by other backends is sufficient to emit a unique symbol so this was unneeded. llvm-svn: 237294
2015-05-13 22:28:38 +02:00
def SDT_ARMBr2JT : SDTypeProfile<0, 3,
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 04:18:14 +02:00
[SDTCisPtrTy<0>, SDTCisVT<1, i32>,
ARM: remove custom jump table UID We were creating and propagating two separate indices for each jump table (from back in the mists of time). However, the generic index used by other backends is sufficient to emit a unique symbol so this was unneeded. llvm-svn: 237294
2015-05-13 22:28:38 +02:00
SDTCisVT<2, i32>]>;
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 04:18:14 +02:00
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. llvm-svn: 108258
2010-07-13 21:27:42 +02:00
def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
[SDTCisVT<0, i32>,
SDTCisVT<1, i32>, SDTCisVT<2, i32>,
SDTCisVT<3, i32>, SDTCisVT<4, i32>,
SDTCisVT<5, OtherVT>]>;
File missing from last commit. llvm-svn: 112394
2010-08-29 05:02:28 +02:00
def SDT_ARMAnd : SDTypeProfile<1, 2,
[SDTCisVT<0, i32>, SDTCisVT<1, i32>,
SDTCisVT<2, i32>]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
[ARM] Use VCMP, not VCMPE, for floating point equality comparisons When generating a floating point comparison we currently unconditionally generate VCMPE. This has the sideeffect of setting the cumulative Invalid bit in FPSCR if any of the operands are QNaN. It is expected that use of a relational predicate on a QNaN value should raise Invalid. Quoting from the C standard: The relational and equality operators support the usual mathematical relationships between numeric values. For any ordered pair of numeric values exactly one of relationships the less, greater, equal and is true. Relational operators may raise the floating-point exception when argument values are NaNs. The standard doesn't explicitly state the expectation for equality operators, but the implication and obvious expectation is that equality operators should not raise Invalid on a QNaN input, as those predicates are wholly defined on unordered inputs (to return not equal). Therefore, add a new operand to ARMISD::FPCMP and FPCMPZ indicating if QNaN should raise Invalid, and pipe that through to TableGen. llvm-svn: 294945
2017-02-13 13:32:47 +01:00
def SDT_ARMFCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>,
SDTCisVT<2, i32>]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
ARM TLS: implement "general dynamic", "initial exec" and "local exec" models. llvm-svn: 36506
2007-04-27 15:54:47 +02:00
def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
tighten up eh.setjmp sequence a bit. llvm-svn: 95603
2010-02-09 00:22:00 +01:00
def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
SDTCisInt<2>]>;
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match longjmp. llvm-svn: 104419
2010-05-22 03:06:18 +02:00
def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
Fix __builtin_setjmp in combination with sjlj exception handling. llvm.eh.sjlj.setjmp was used as part of the SjLj exception handling style but is also used in clang to implement __builtin_setjmp. The ARM backend needs to output additional dispatch tables for the SjLj exception handling style, these tables however can't be emitted if llvm.eh.sjlj.setjmp is simply used for __builtin_setjmp and no actual landing pad blocks exist. To solve this issue a new llvm.eh.sjlj.setup_dispatch intrinsic is introduced which is used instead of llvm.eh.sjlj.setjmp in the SjLj exception handling lowering, so we can differentiate between the case where we actually need to setup a dispatch table and the case where we just need the __builtin_setjmp semantic. Differential Revision: http://reviews.llvm.org/D9313 llvm-svn: 242481
2015-07-17 00:34:16 +02:00
def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>;
ARM TLS: implement "general dynamic", "initial exec" and "local exec" models. llvm-svn: 36506
2007-04-27 15:54:47 +02:00
Overhaul memory barriers in the ARM backend. Radar 8601999. There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. llvm-svn: 117756
2010-10-30 02:54:37 +02:00
def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics. llvm-svn: 91003
2009-12-10 01:11:09 +01:00
Add one more argument to the prefetch intrinsic to indicate whether it's a data or instruction cache access. Update the targets to match it and also teach autoupgrade. llvm-svn: 132976
2011-06-14 06:58:37 +02:00
def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
SDTCisInt<1>]>;
Early implementation of tail call for ARM. A temporary flag -arm-tail-calls defaults to off, so there is no functional change by default. Intrepid users may try this; simple cases work but there are bugs. llvm-svn: 105413
2010-06-03 23:09:53 +02:00
def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction and a combine pattern to use it for setting a bit-field to a constant value. More to come for non-constant stores. llvm-svn: 108570
2010-07-17 01:05:05 +02:00
def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
ARM: address WoA division limitation We now emit the compiler generated divide by zero check that was needed for the MSVC routines. We construct a psuedo-instruction for the DBZ check as the operation requires splitting up the BB. For the 64-bit operations, we need to custom expand the node as we need to insert the DBZ check and then emit the libcall to the appropriate name. Because this is target specific, it seemed better to reproduce the expansion operation from the target-agnostic type legalization rather than sink this there to avoid the duplication. The division library calls now match MSVC semantically. llvm-svn: 248561
2015-09-25 07:15:46 +02:00
def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
[ARM] Modify codegen for memcpy intrinsic to prefer LDM/STM. We were previously codegen'ing memcpy as regular load/store operations and hoping that the register allocator would allocate registers in ascending order so that we could apply an LDM/STM combine after register allocation. According to the commit that first introduced this code (r37179), we planned to teach the register allocator to allocate the registers in ascending order. This never got implemented, and up to now we've been stuck with very poor codegen. A much simpler approach for achieving better codegen is to create MEMCPY pseudo instructions, attach scratch virtual registers to them and then, post register allocation, expand the MEMCPYs into LDM/STM pairs using the scratch registers. The register allocator will have picked arbitrary registers which we sort when expanding the MEMCPY. This approach also avoids the need to repeatedly calculate offsets which ultimately ought to be eliminated pre-RA in order to decrease register pressure. Fixes PR9199 and PR23768. [This is based on Peter Collingbourne's r238473 which was reverted.] Differential Revision: http://reviews.llvm.org/D13239 Change-Id: I727543c2e94136e0f80b8e22d5642d7b9ee5b458 Author: Peter Collingbourne <peter@pcc.me.uk> llvm-svn: 249322
2015-10-05 16:49:54 +02:00
def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
SDTCisVT<2, i32>, SDTCisVT<3, i32>,
SDTCisVT<4, i32>]>;
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
[SDTCisSameAs<0, 2>,
SDTCisSameAs<0, 3>,
SDTCisInt<0>, SDTCisVT<1, i32>]>;
// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
[SDTCisSameAs<0, 2>,
SDTCisSameAs<0, 3>,
SDTCisInt<0>,
SDTCisVT<1, i32>,
SDTCisVT<4, i32>]>;
Patch to implement UMLAL/SMLAL instructions for the ARM architecture This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 163136
2012-09-04 16:37:49 +02:00
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 09:27:11 +01:00
def SDT_LongMac : SDTypeProfile<2, 4, [SDTCisVT<0, i32>,
SDTCisSameAs<0, 1>,
SDTCisSameAs<0, 2>,
SDTCisSameAs<0, 3>,
SDTCisSameAs<0, 4>,
SDTCisSameAs<0, 5>]>;
[ARM] Add support for the MVE long shift instructions MVE adds the lsll, lsrl and asrl instructions, which perform a shift on a 64 bit value separated into two 32 bit registers. The Expand64BitShift function is modified to accept ISD::SHL, ISD::SRL and ISD::SRA and convert it into the appropriate opcode in ARMISD. An SHL is converted into an lsll, an SRL is converted into an lsrl for the immediate form and a negation and lsll for the register form, and SRA is converted into an asrl. test/CodeGen/ARM/shift_parts.ll is added to test the logic of emitting these instructions. Differential Revision: https://reviews.llvm.org/D63430 llvm-svn: 364654
2019-06-28 17:43:31 +02:00
// ARMlsll, ARMlsrl, ARMasrl
def SDT_ARMIntShiftParts : SDTypeProfile<2, 3, [SDTCisSameAs<0, 1>,
SDTCisSameAs<0, 2>,
SDTCisSameAs<0, 3>,
SDTCisInt<0>,
SDTCisInt<4>]>;
[ARM] WLS/LE Code Generation Backend changes to enable WLS/LE low-overhead loops for armv8.1-m: 1) Use TTI to communicate to the HardwareLoop pass that we should try to generate intrinsics that guard the loop entry, as well as setting the loop trip count. 2) Lower the BRCOND that uses said intrinsic to an Arm specific node: ARMWLS. 3) ISelDAGToDAG the node to a new pseudo instruction: t2WhileLoopStart. 4) Add support in ArmLowOverheadLoops to handle the new pseudo instruction. Differential Revision: https://reviews.llvm.org/D63816 llvm-svn: 364733
2019-07-01 10:21:28 +02:00
// TODO Add another operand for 'Size' so that we can re-use this node when we
// start supporting *TP versions.
def SDT_ARMWhileLoop : SDTypeProfile<0, 2, [SDTCisVT<0, i32>,
SDTCisVT<1, OtherVT>]>;
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
def ARMSmlald : SDNode<"ARMISD::SMLALD", SDT_LongMac>;
def ARMSmlaldx : SDNode<"ARMISD::SMLALDX", SDT_LongMac>;
def ARMSmlsld : SDNode<"ARMISD::SMLSLD", SDT_LongMac>;
def ARMSmlsldx : SDNode<"ARMISD::SMLSLDX", SDT_LongMac>;
[ARM] Add codegen for SMMULR, SMMLAR and SMMLSR This patch teaches the Arm back-end to generate the SMMULR, SMMLAR and SMMLSR instructions from equivalent IR patterns. Differential Revision: https://reviews.llvm.org/D41775 llvm-svn: 322361
2018-01-12 10:24:41 +01:00
def SDT_MulHSR : SDTypeProfile<1, 3, [SDTCisVT<0,i32>,
SDTCisSameAs<0, 1>,
SDTCisSameAs<0, 2>,
SDTCisSameAs<0, 3>]>;
def ARMsmmlar : SDNode<"ARMISD::SMMLAR", SDT_MulHSR>;
def ARMsmmlsr : SDNode<"ARMISD::SMMLSR", SDT_MulHSR>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// Node definitions.
def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
Sorry, several patches in one. TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. llvm-svn: 123905
2011-01-20 09:34:58 +01:00
def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
ARM: remove custom jump table UID We were creating and propagating two separate indices for each jump table (from back in the mists of time). However, the generic index used by other backends is sufficient to emit a unique symbol so this was unneeded. llvm-svn: 237294
2015-05-13 22:28:38 +02:00
def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Unifacalize the CALLSEQ{START,END} stuff. llvm-svn: 44045
2007-11-13 10:19:02 +01:00
def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
Add missing SDNPSideEffect flags. llvm-svn: 162557
2012-08-24 16:43:27 +02:00
[SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
Unifacalize the CALLSEQ{START,END} stuff. llvm-svn: 44045
2007-11-13 10:19:02 +01:00
def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
Add missing SDNPSideEffect flags. llvm-svn: 162557
2012-08-24 16:43:27 +02:00
[SDNPHasChain, SDNPSideEffect,
SDNPOptInGlue, SDNPOutGlue]>;
ARM: support struct byval in llvm We handle struct byval by inserting a pseudo op, which will be expanded to a loop at ExpandISelPseudos. A separate patch for clang will be submitted to enable struct byval. rdar://9877866 llvm-svn: 157793
2012-06-01 04:44:42 +02:00
def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
SDT_ARMStructByVal,
[SDNPHasChain, SDNPInGlue, SDNPOutGlue,
SDNPMayStore, SDNPMayLoad]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-23 19:28:41 +01:00
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
set SDNPVariadic on nodes throughout the rest of the targets that need them. llvm-svn: 98937
2010-03-19 06:33:51 +01:00
SDNPVariadic]>;
Allow predicated immediate ARM to ARM calls. llvm-svn: 37659
2007-06-19 23:05:09 +02:00
def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-23 19:28:41 +01:00
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
set SDNPVariadic on nodes throughout the rest of the targets that need them. llvm-svn: 98937
2010-03-19 06:33:51 +01:00
SDNPVariadic]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-23 19:28:41 +01:00
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
set SDNPVariadic on nodes throughout the rest of the targets that need them. llvm-svn: 98937
2010-03-19 06:33:51 +01:00
SDNPVariadic]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
rename SDTRet -> SDTNone. Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td. llvm-svn: 46017
2008-01-15 23:02:54 +01:00
def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
Move MRI liveouts to ARM return instructions. llvm-svn: 174406
2013-02-05 19:08:40 +01:00
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
ARM: support interrupt attribute This function-attribute modifies the callee-saved register list and function epilogue (specifically the return instruction) so that a routine is suitable for use as an interrupt-handler of the specified type without disrupting user-mode applications. rdar://problem/14207019 llvm-svn: 191766
2013-10-01 16:33:28 +02:00
def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-23 19:28:41 +01:00
[SDNPInGlue]>;
ARM: use target-specific SUBS node when combining cmp with cmov. This has two positive effects. First, using a custom node prevents recombination leading to an infinite loop since the output DAG is notionally a little more complex than the input one. Using a flag-setting instruction also allows the subtraction to be folded with the related comparison more easily. https://reviews.llvm.org/D53190 llvm-svn: 348122
2018-12-03 12:16:21 +01:00
def ARMsubs : SDNode<"ARMISD::SUBS", SDTIntBinOp, [SDNPOutGlue]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
[ARM] Lower (select_cc k k (select_cc ~k ~k x)) into (SSAT l_k x) Summary: SSAT saturates an integer, making sure that its value lies within an interval [-k, k]. Since the constant is given to SSAT as the number of bytes set to one, k + 1 must be a power of 2, otherwise the optimization is not possible. Also, the select_cc must use < and > respectively so that they define an interval. Reviewers: mcrosier, jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D21372 llvm-svn: 273581
2016-06-23 18:53:49 +02:00
def ARMssatnoshift : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>;
[ARM] Lower unsigned saturation to USAT Summary: Implement lower of unsigned saturation on an interval [0, k] where k + 1 is a power of two using USAT instruction in a similar way to how [~k, k] is lowered using SSAT on ARM models that supports it. Patch by Marten Svanfeldt Reviewers: t.p.northover, pbarrio, eastig, SjoerdMeijer, javed.absar, fhahn Reviewed By: fhahn Subscribers: fhahn, aemerson, javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D41348 llvm-svn: 321164
2017-12-20 12:13:57 +01:00
def ARMusatnoshift : SDNode<"ARMISD::USAT", SDTIntSatNoShOp, []>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-23 19:28:41 +01:00
[SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
[SDNPHasChain]>;
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. llvm-svn: 77422
2009-07-29 04:18:14 +02:00
def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
[SDNPHasChain]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. llvm-svn: 108258
2010-07-13 21:27:42 +02:00
def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
[SDNPHasChain]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-23 19:28:41 +01:00
[SDNPOutGlue]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Re-enable the CMN instruction. We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> llvm-svn: 158302
2012-06-11 10:07:26 +02:00
def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
[SDNPOutGlue]>;
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative. llvm-svn: 74423
2009-06-29 17:33:01 +02:00
def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-23 19:28:41 +01:00
[SDNPOutGlue, SDNPCommutative]>;
- Divides the comparisons in two types: comparisons that only use N and Z flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP). - Defines the instructions: TST, TEQ (ARM) and TST (Thumb). llvm-svn: 35573
2007-04-02 03:30:03 +02:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
[ARM] Add support for the MVE long shift instructions MVE adds the lsll, lsrl and asrl instructions, which perform a shift on a 64 bit value separated into two 32 bit registers. The Expand64BitShift function is modified to accept ISD::SHL, ISD::SRL and ISD::SRA and convert it into the appropriate opcode in ARMISD. An SHL is converted into an lsll, an SRL is converted into an lsrl for the immediate form and a negation and lsll for the register form, and SRA is converted into an asrl. test/CodeGen/ARM/shift_parts.ll is added to test the logic of emitting these instructions. Differential Revision: https://reviews.llvm.org/D63430 llvm-svn: 364654
2019-06-28 17:43:31 +02:00
def ARMasrl : SDNode<"ARMISD::ASRL", SDT_ARMIntShiftParts, []>;
def ARMlsrl : SDNode<"ARMISD::LSRL", SDT_ARMIntShiftParts, []>;
def ARMlsll : SDNode<"ARMISD::LSLL", SDT_ARMIntShiftParts, []>;
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-23 19:28:41 +01:00
def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
[SDNPCommutative]>;
def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
ARM TLS: implement "general dynamic", "initial exec" and "local exec" models. llvm-svn: 36506
2007-04-27 15:54:47 +02:00
def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in ISD::. No functional change. llvm-svn: 104734
2010-05-26 22:22:18 +02:00
def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
Add missing SDNPSideEffect flags. llvm-svn: 162557
2012-08-24 16:43:27 +02:00
SDT_ARMEH_SJLJ_Setjmp,
[SDNPHasChain, SDNPSideEffect]>;
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match longjmp. llvm-svn: 104419
2010-05-22 03:06:18 +02:00
def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
Add missing SDNPSideEffect flags. llvm-svn: 162557
2012-08-24 16:43:27 +02:00
SDT_ARMEH_SJLJ_Longjmp,
[SDNPHasChain, SDNPSideEffect]>;
Fix __builtin_setjmp in combination with sjlj exception handling. llvm.eh.sjlj.setjmp was used as part of the SjLj exception handling style but is also used in clang to implement __builtin_setjmp. The ARM backend needs to output additional dispatch tables for the SjLj exception handling style, these tables however can't be emitted if llvm.eh.sjlj.setjmp is simply used for __builtin_setjmp and no actual landing pad blocks exist. To solve this issue a new llvm.eh.sjlj.setup_dispatch intrinsic is introduced which is used instead of llvm.eh.sjlj.setjmp in the SjLj exception handling lowering, so we can differentiate between the case where we actually need to setup a dispatch table and the case where we just need the __builtin_setjmp semantic. Differential Revision: http://reviews.llvm.org/D9313 llvm-svn: 242481
2015-07-17 00:34:16 +02:00
def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH",
SDT_ARMEH_SJLJ_SetupDispatch,
[SDNPHasChain, SDNPSideEffect]>;
ARM TLS: implement "general dynamic", "initial exec" and "local exec" models. llvm-svn: 36506
2007-04-27 15:54:47 +02:00
Overhaul memory barriers in the ARM backend. Radar 8601999. There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. llvm-svn: 117756
2010-10-30 02:54:37 +02:00
def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
Add missing SDNPSideEffect flags. llvm-svn: 162557
2012-08-24 16:43:27 +02:00
[SDNPHasChain, SDNPSideEffect]>;
Add one more argument to the prefetch intrinsic to indicate whether it's a data or instruction cache access. Update the targets to match it and also teach autoupgrade. llvm-svn: 132976
2011-06-14 06:58:37 +02:00
def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. llvm-svn: 118160
2010-11-03 07:34:55 +01:00
[SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics. llvm-svn: 91003
2009-12-10 01:11:09 +01:00
Trailing whitespace. llvm-svn: 117188
2010-10-23 01:48:29 +02:00
def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
Flag -> Glue, the ongoing saga llvm-svn: 122513
2010-12-23 19:28:41 +01:00
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
Early implementation of tail call for ARM. A temporary flag -arm-tail-calls defaults to off, so there is no functional change by default. Intrepid users may try this; simple cases work but there are bugs. llvm-svn: 105413
2010-06-03 23:09:53 +02:00
Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction and a combine pattern to use it for setting a bit-field to a constant value. More to come for non-constant stores. llvm-svn: 108570
2010-07-17 01:05:05 +02:00
def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
[ARM] Modify codegen for memcpy intrinsic to prefer LDM/STM. We were previously codegen'ing memcpy as regular load/store operations and hoping that the register allocator would allocate registers in ascending order so that we could apply an LDM/STM combine after register allocation. According to the commit that first introduced this code (r37179), we planned to teach the register allocator to allocate the registers in ascending order. This never got implemented, and up to now we've been stuck with very poor codegen. A much simpler approach for achieving better codegen is to create MEMCPY pseudo instructions, attach scratch virtual registers to them and then, post register allocation, expand the MEMCPYs into LDM/STM pairs using the scratch registers. The register allocator will have picked arbitrary registers which we sort when expanding the MEMCPY. This approach also avoids the need to repeatedly calculate offsets which ultimately ought to be eliminated pre-RA in order to decrease register pressure. Fixes PR9199 and PR23768. [This is based on Peter Collingbourne's r238473 which was reverted.] Differential Revision: http://reviews.llvm.org/D13239 Change-Id: I727543c2e94136e0f80b8e22d5642d7b9ee5b458 Author: Peter Collingbourne <peter@pcc.me.uk> llvm-svn: 249322
2015-10-05 16:49:54 +02:00
def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY,
[SDNPHasChain, SDNPInGlue, SDNPOutGlue,
SDNPMayStore, SDNPMayLoad]>;
[ARM] Move SMULW[B|T] isel to DAG Combine Create nodes for smulwb and smulwt and move their selection from DAGToDAG to DAG combine. smlawb and smlawt can then be selected using tablegen. Added some helper functions to detect shift patterns as well as a wrapper around SimplifyDemandBits. Added a couple of extra tests. Differential Revision: https://reviews.llvm.org/D30708 llvm-svn: 297716
2017-03-14 10:13:22 +01:00
def ARMsmulwb : SDNode<"ARMISD::SMULWB", SDTIntBinOp, []>;
def ARMsmulwt : SDNode<"ARMISD::SMULWT", SDTIntBinOp, []>;
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 09:27:11 +01:00
def ARMsmlalbb : SDNode<"ARMISD::SMLALBB", SDT_LongMac, []>;
def ARMsmlalbt : SDNode<"ARMISD::SMLALBT", SDT_LongMac, []>;
def ARMsmlaltb : SDNode<"ARMISD::SMLALTB", SDT_LongMac, []>;
def ARMsmlaltt : SDNode<"ARMISD::SMLALTT", SDT_LongMac, []>;
[ARM] Move SMULW[B|T] isel to DAG Combine Create nodes for smulwb and smulwt and move their selection from DAGToDAG to DAG combine. smlawb and smlawt can then be selected using tablegen. Added some helper functions to detect shift patterns as well as a wrapper around SimplifyDemandBits. Added a couple of extra tests. Differential Revision: https://reviews.llvm.org/D30708 llvm-svn: 297716
2017-03-14 10:13:22 +01:00
[ARM] MVE vector shuffles This patch adds necessary shuffle vector and buildvector support for ARM MVE. It essentially adds support for VDUP, VREVs and some VMOVs, which are often required by other code (like upcoming patches). This mostly uses the same code from Neon that already generated NEONvdup/NEONvduplane/NEONvrev's. These have been renamed to ARMvdup/etc and moved to ARMInstrInfo as they are common to both architectures. Most of the selection code seems to be applicable to both, but NEON does have some more instructions making some parts specific. Most code originally by David Sherwood. Differential Revision: https://reviews.llvm.org/D63567 llvm-svn: 364626
2019-06-28 09:08:42 +02:00
// Vector operations shared between NEON and MVE
def ARMvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
// VDUPLANE can produce a quad-register result from a double-register source,
// so the result is not constrained to match the source.
def ARMvduplane : SDNode<"ARMISD::VDUPLANE",
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
SDTCisVT<2, i32>]>>;
def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
def ARMvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
def ARMvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
def ARMvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
SDTCisVT<2, i32>]>;
def ARMvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
def ARMvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
[ARM] MVE VMOV immediate handling This adds some handling for VMOVimm, using the same method that NEON uses. We create VMOVIMM/VMVNIMM/VMOVFPIMM nodes based on the immediate, and select them using the now renamed ARMvmovImm/etc. There is also an extra 64bit immediate mode that I have not yet added here. Code by David Sherwood Differential Revision: https://reviews.llvm.org/D63884 llvm-svn: 365178
2019-07-05 12:02:43 +02:00
def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
def ARMvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
def ARMvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
def ARMvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>;
[ARM] MVE Vector Shifts This adds basic lowering for MVE shifts. There are many shifts in MVE, but the instructions handled here are: VSHL (imm) VSHRu (imm) VSHRs (imm) VSHL (vector) VSHL (register) MVE, like NEON before it, doesn't have shift right by a vector (or register). We instead have to negate the amount and shift in the opposite direction. This means we have to convert any SHR's into a form of SHL (that is still signed or unsigned) with a negated condition and selecting from there. MVE still does have shifting by an immediate for SHL, ASR and LSR. This adds lowering for these and for register forms, which work well for shift lefts but may require an extra fold of neg(vdup(x)) -> vdup(neg(x)) to potentially work optimally for right shifts. Differential Revision: https://reviews.llvm.org/D64212 llvm-svn: 366056
2019-07-15 13:35:39 +02:00
def SDTARMVSHIMM : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
SDTCisVT<2, i32>]>;
def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
SDTCisSameAs<0, 2>,]>;
def ARMvshlImm : SDNode<"ARMISD::VSHLIMM", SDTARMVSHIMM>;
def ARMvshrsImm : SDNode<"ARMISD::VSHRsIMM", SDTARMVSHIMM>;
def ARMvshruImm : SDNode<"ARMISD::VSHRuIMM", SDTARMVSHIMM>;
def ARMvshls : SDNode<"ARMISD::VSHLs", SDTARMVSH>;
def ARMvshlu : SDNode<"ARMISD::VSHLu", SDTARMVSH>;
[ARM] WLS/LE Code Generation Backend changes to enable WLS/LE low-overhead loops for armv8.1-m: 1) Use TTI to communicate to the HardwareLoop pass that we should try to generate intrinsics that guard the loop entry, as well as setting the loop trip count. 2) Lower the BRCOND that uses said intrinsic to an Arm specific node: ARMWLS. 3) ISelDAGToDAG the node to a new pseudo instruction: t2WhileLoopStart. 4) Add support in ArmLowOverheadLoops to handle the new pseudo instruction. Differential Revision: https://reviews.llvm.org/D63816 llvm-svn: 364733
2019-07-01 10:21:28 +02:00
def ARMWLS : SDNode<"ARMISD::WLS", SDT_ARMWhileLoop,
[SDNPHasChain]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
//===----------------------------------------------------------------------===//
// ARM Flag Definitions.
class RegConstraint<string C> {
string Constraints = C;
partial implementation of the ARM Addressing Mode 1 llvm-svn: 30252
2006-09-11 19:25:40 +02:00
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
//===----------------------------------------------------------------------===//
// ARM specific transformation functions and pattern fragments.
//
Fix a miscompilation caused by a typo. When turning a adde with negative value into a sbc with a positive number, the immediate should be complemented, not negated. Also added a missing pattern for ARM codegen. rdar://12559385 llvm-svn: 166613
2012-10-24 21:53:01 +02:00
// imm_neg_XFORM - Return the negation of an i32 immediate value.
(sub X, imm) gets canonicalized to (add X, -imm) There are patterns to handle immediates when they fit in the immediate field. e.g. %sub = add i32 %x, -123 => sub r0, r0, #123 Add patterns to catch immediates that do not fit but should be materialized with a single movw instruction rather than movw + movt pair. e.g. %sub = add i32 %x, -65535 => movw r1, #65535 sub r0, r0, r1 rdar://11726136 llvm-svn: 159057
2012-06-23 02:29:06 +02:00
def imm_neg_XFORM : SDNodeXForm<imm, [{
Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes" [DebugInfo] Add debug locations to constant SD nodes This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235989
2015-04-28 16:05:47 +02:00
return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32);
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
}]>;
Fix a miscompilation caused by a typo. When turning a adde with negative value into a sbc with a positive number, the immediate should be complemented, not negated. Also added a missing pattern for ARM codegen. rdar://12559385 llvm-svn: 166613
2012-10-24 21:53:01 +02:00
// imm_not_XFORM - Return the complement of a i32 immediate value.
def imm_not_XFORM : SDNodeXForm<imm, [{
Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes" [DebugInfo] Add debug locations to constant SD nodes This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235989
2015-04-28 16:05:47 +02:00
return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32);
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
}]>;
/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
Let the immediate leaf pattern take transforms and switch the signed immediate patterns in arm to using the pattern. Handles rdar://9299434 llvm-svn: 130386
2011-04-28 07:49:04 +02:00
def imm16_31 : ImmLeaf<i32, [{
return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
}]>;
// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
def sext_16_node : PatLeaf<(i32 GPR:$a), [{
[ARM] Add missing patterns for DSP muls Using a PatLeaf for sext_16_node allowed matching smulbb and smlabb instructions once the operands had been sign extended. But we also need to use sext_inreg operands along with sext_16_node to catch a few more cases that enable use to remove the unnecessary sxth. Differential Revision: https://reviews.llvm.org/D55992 llvm-svn: 350613
2019-01-08 11:12:36 +01:00
return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
}]>;
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 14:44:27 +02:00
[ARM] Add missing patterns for DSP muls Using a PatLeaf for sext_16_node allowed matching smulbb and smlabb instructions once the operands had been sign extended. But we also need to use sext_inreg operands along with sext_16_node to catch a few more cases that enable use to remove the unnecessary sxth. Differential Revision: https://reviews.llvm.org/D55992 llvm-svn: 350613
2019-01-08 11:12:36 +01:00
def sext_bottom_16 : PatFrag<(ops node:$a),
(sext_inreg node:$a, i16)>;
def sext_top_16 : PatFrag<(ops node:$a),
(i32 (sra node:$a, (i32 16)))>;
[ARM] Improve smul* and smla* isel for Thumb2 Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to simplify some pattern matching. This has allowed several patterns for smul* and smla* to be removed as well as making it easier to add the matching for the corresponding instructions for Thumb2 targets. Also added two Pat classes that are predicated on Thumb2 with the hasDSP flag and UseMulOps flags. Updated the smul codegen test with the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets. Differential Revision: https://reviews.llvm.org/D22908 llvm-svn: 277450
2016-08-02 14:44:27 +02:00
[ARM] Add missing patterns for DSP muls Using a PatLeaf for sext_16_node allowed matching smulbb and smlabb instructions once the operands had been sign extended. But we also need to use sext_inreg operands along with sext_16_node to catch a few more cases that enable use to remove the unnecessary sxth. Differential Revision: https://reviews.llvm.org/D55992 llvm-svn: 350613
2019-01-08 11:12:36 +01:00
def bb_mul : PatFrag<(ops node:$a, node:$b),
(mul (sext_bottom_16 node:$a), (sext_bottom_16 node:$b))>;
def bt_mul : PatFrag<(ops node:$a, node:$b),
(mul (sext_bottom_16 node:$a), (sra node:$b, (i32 16)))>;
def tb_mul : PatFrag<(ops node:$a, node:$b),
(mul (sra node:$a, (i32 16)), (sext_bottom_16 node:$b))>;
def tt_mul : PatFrag<(ops node:$a, node:$b),
(mul (sra node:$a, (i32 16)), (sra node:$b, (i32 16)))>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. This should be better than single load from constpool. llvm-svn: 82948
2009-09-28 01:52:58 +02:00
/// Split a 32-bit immediate into two 16 bit parts.
def hi16 : SDNodeXForm<imm, [{
Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes" [DebugInfo] Add debug locations to constant SD nodes This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235989
2015-04-28 16:05:47 +02:00
return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N),
MVT::i32);
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. This should be better than single load from constpool. llvm-svn: 82948
2009-09-28 01:52:58 +02:00
}]>;
def lo16AllZero : PatLeaf<(i32 imm), [{
// Returns true if all low 16-bits are 0.
return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
Materialize global addresses via movt/movw pair, this is always better than doing the same via constpool: 1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2. 2. Load from constpool might stall up to 300 cycles due to cache miss. 3. Movt/movw does not use load/store unit. 4. Less constpool entries => better compiler performance. This is only enabled on ELF systems, since darwin does not have needed relocations (yet). llvm-svn: 89720
2009-11-24 01:44:37 +01:00
}], hi16>;
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. This should be better than single load from constpool. llvm-svn: 82948
2009-09-28 01:52:58 +02:00
Refactor ARM instruction format definitions into a separate file. No functionality changes. llvm-svn: 55518
2008-08-29 01:39:26 +02:00
class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 llvm-svn: 119548
2010-11-17 21:13:28 +01:00
// An 'and' node with a single use.
def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
return N->hasOneUse();
}]>;
// An 'xor' node with a single use.
def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
return N->hasOneUse();
}]>;
Making use of VFP / NEON floating point multiply-accumulate / subtraction is difficult on current ARM implementations for a few reasons. 1. Even though a single vmla has latency that is one cycle shorter than a pair of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause additional pipeline stall. So it's frequently better to single codegen vmul + vadd. 2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to stall for 4 cycles. We need to schedule them apart. 3. A vmla followed vmla is a special case. Obvious issuing back to back RAW vmla + vmla is very bad. But this isn't ideal either: vmul vadd vmla Instead, we want to expand the second vmla: vmla vmul vadd Even with the 4 cycle vmul stall, the second sequence is still 2 cycles faster. Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough but it isn't the optimial solution. This patch attempts to make it possible to use vmla / vmls in cases where it is profitable. A. Add missing isel predicates which cause vmla to be codegen'ed. B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to compute a fmul and a fmla. C. Add additional isel checks for vmla, avoid cases where vmla is feeding into fp instructions (except for the #3 exceptional case). D. Add ARM hazard recognizer to model the vmla / vmls hazards. E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the vmla / vmls will trigger one of the special hazards. Work in progress, only A+B are enabled. llvm-svn: 120960
2010-12-05 23:04:16 +01:00
// An 'fmul' node with a single use.
def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
return N->hasOneUse();
}]>;
// An 'fadd' node which checks for single non-hazardous use.
def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
return hasNoVMLxHazardUse(N);
}]>;
// An 'fsub' node which checks for single non-hazardous use.
def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
return hasNoVMLxHazardUse(N);
}]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
//===----------------------------------------------------------------------===//
// Operand Definitions.
//
ARM refactor simple immediate asm operand render methods. These immediate operands all use the same simple logic for rendering to MCInst, so have them share the method for doing so. llvm-svn: 144439
2011-11-12 01:58:43 +01:00
// Immediate operands with a shared generic asm render method.
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
class ImmAsmOperand<int Low, int High> : AsmOperandClass {
let RenderMethod = "addImmOperands";
let PredicateMethod = "isImmediate<" # Low # "," # High # ">";
[ARM, Asm] Change grammar of immediate operand diagnostics Currently, our diagnostics for assembly operands are not consistent. Some start with (for example) "immediate operand must be ...", and some with "operand must be an immediate ...". I think the latter form is preferable for a few reasons: * It's unambiguous that it is referring to the expected type of operand, not the type the user provided. For example, the user could provide an register operand, and get a message taking about an operand is if it is already an immediate, just not in the accepted range. * It allows us to have a consistent style once we add diagnostics for operands that could take two forms, for example a label or pc-relative memory operand. Differential revision: https://reviews.llvm.org/D36689 llvm-svn: 314887
2017-10-04 11:18:07 +02:00
let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]";
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
}
class ImmAsmOperandMinusOne<int Low, int High> : AsmOperandClass {
let PredicateMethod = "isImmediate<" # Low # "," # High # ">";
let DiagnosticType = "ImmRange" # Low # "_" # High;
[ARM, Asm] Change grammar of immediate operand diagnostics Currently, our diagnostics for assembly operands are not consistent. Some start with (for example) "immediate operand must be ...", and some with "operand must be an immediate ...". I think the latter form is preferable for a few reasons: * It's unambiguous that it is referring to the expected type of operand, not the type the user provided. For example, the user could provide an register operand, and get a message taking about an operand is if it is already an immediate, just not in the accepted range. * It allows us to have a consistent style once we add diagnostics for operands that could take two forms, for example a label or pc-relative memory operand. Differential revision: https://reviews.llvm.org/D36689 llvm-svn: 314887
2017-10-04 11:18:07 +02:00
let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]";
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
}
ARM refactor simple immediate asm operand render methods. These immediate operands all use the same simple logic for rendering to MCInst, so have them share the method for doing so. llvm-svn: 144439
2011-11-12 01:58:43 +01:00
[ARM] Mark a bunch of .td Operands with type _MEMORY. This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
2015-04-07 22:31:16 +02:00
// Operands that are part of a memory addressing mode.
class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; }
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// Branch target.
Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps. (yes, this is different from R_ARM_CALL) - Adds a new method getARMBranchTargetOpValue() which handles the necessary distinction between the conditional and unconditional br/bl needed for ARM/ELF At least for ARM mode, the needed fixup for conditional versus unconditional br/bl is identical, but the ARM docs and existing ARM tools expect this reloc type... Added a few FIXME's for future naming fixups in ARMInstrInfo.td llvm-svn: 124895
2011-02-04 20:47:15 +01:00
// FIXME: rename brtarget to t2_brtarget
Encoding of destination fixup for ARM branch and conditional branch instructions. llvm-svn: 118801
2010-11-11 19:04:49 +01:00
def brtarget : Operand<OtherVT> {
add fields to the .td files unconditionally, simplifying tblgen a bit. Switch the ARM backend to use 'let' instead of 'set' with this change. llvm-svn: 119120
2010-11-15 06:19:05 +01:00
let EncoderMethod = "getBranchTargetOpValue";
Port operand types for ARM and X86 over from EDIS to the .td files. llvm-svn: 135198
2011-07-14 23:47:22 +02:00
let OperandType = "OPERAND_PCREL";
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeT2BROperand";
Encoding of destination fixup for ARM branch and conditional branch instructions. llvm-svn: 118801
2010-11-11 19:04:49 +01:00
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
ARM: validate immediate branch targets in AsmParser. Immediate branch targets aren't commonly used, but if they are we should make sure they can actually be encoded. This means they must be divisible by 2 when targeting Thumb mode, and by 4 when targeting ARM mode. Also do a little naming cleanup while I was changing everything around anyway. llvm-svn: 275116
2016-07-12 00:29:37 +02:00
// Branches targeting ARM-mode must be divisible by 4 if they're a raw
// immediate.
def ARMBranchTarget : AsmOperandClass {
let Name = "ARMBranchTarget";
In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise equivalence, provide encoding and fixup support for it. llvm-svn: 121710
2010-12-13 20:31:11 +01:00
}
ARM: validate immediate branch targets in AsmParser. Immediate branch targets aren't commonly used, but if they are we should make sure they can actually be encoded. This means they must be divisible by 2 when targeting Thumb mode, and by 4 when targeting ARM mode. Also do a little naming cleanup while I was changing everything around anyway. llvm-svn: 275116
2016-07-12 00:29:37 +02:00
// Branches targeting Thumb-mode must be divisible by 2 if they're a raw
// immediate.
def ThumbBranchTarget : AsmOperandClass {
let Name = "ThumbBranchTarget";
Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps. (yes, this is different from R_ARM_CALL) - Adds a new method getARMBranchTargetOpValue() which handles the necessary distinction between the conditional and unconditional br/bl needed for ARM/ELF At least for ARM mode, the needed fixup for conditional versus unconditional br/bl is identical, but the ARM docs and existing ARM tools expect this reloc type... Added a few FIXME's for future naming fixups in ARMInstrInfo.td llvm-svn: 124895
2011-02-04 20:47:15 +01:00
}
ARM: validate immediate branch targets in AsmParser. Immediate branch targets aren't commonly used, but if they are we should make sure they can actually be encoded. This means they must be divisible by 2 when targeting Thumb mode, and by 4 when targeting ARM mode. Also do a little naming cleanup while I was changing everything around anyway. llvm-svn: 275116
2016-07-12 00:29:37 +02:00
def arm_br_target : Operand<OtherVT> {
let ParserMatchClass = ARMBranchTarget;
let EncoderMethod = "getARMBranchTargetOpValue";
Port operand types for ARM and X86 over from EDIS to the .td files. llvm-svn: 135198
2011-07-14 23:47:22 +02:00
let OperandType = "OPERAND_PCREL";
ARM fixup encoding for direct call instructions (BL). llvm-svn: 118829
2010-11-11 21:05:40 +01:00
}
Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps. (yes, this is different from R_ARM_CALL) - Adds a new method getARMBranchTargetOpValue() which handles the necessary distinction between the conditional and unconditional br/bl needed for ARM/ELF At least for ARM mode, the needed fixup for conditional versus unconditional br/bl is identical, but the ARM docs and existing ARM tools expect this reloc type... Added a few FIXME's for future naming fixups in ARMInstrInfo.td llvm-svn: 124895
2011-02-04 20:47:15 +01:00
// Call target for ARM. Handles conditional/unconditional
// FIXME: rename bl_target to t2_bltarget?
ARM: validate immediate branch targets in AsmParser. Immediate branch targets aren't commonly used, but if they are we should make sure they can actually be encoded. This means they must be divisible by 2 when targeting Thumb mode, and by 4 when targeting ARM mode. Also do a little naming cleanup while I was changing everything around anyway. llvm-svn: 275116
2016-07-12 00:29:37 +02:00
def arm_bl_target : Operand<i32> {
let ParserMatchClass = ARMBranchTarget;
ARM BL/BLX instruction fixups should use relocations. We on the linker to resolve calls to the appropriate BL/BLX instruction to make interworking function correctly. It uses the symbol in the relocation to do that, so we need to be careful about being too clever. To enable this for ARM mode, split the BL/BLX fixup kind off from the unconditional-branch fixups. rdar://10927209 llvm-svn: 151571
2012-02-27 22:36:23 +01:00
let EncoderMethod = "getARMBLTargetOpValue";
Port operand types for ARM and X86 over from EDIS to the .td files. llvm-svn: 135198
2011-07-14 23:47:22 +02:00
let OperandType = "OPERAND_PCREL";
Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps. (yes, this is different from R_ARM_CALL) - Adds a new method getARMBranchTargetOpValue() which handles the necessary distinction between the conditional and unconditional br/bl needed for ARM/ELF At least for ARM mode, the needed fixup for conditional versus unconditional br/bl is identical, but the ARM docs and existing ARM tools expect this reloc type... Added a few FIXME's for future naming fixups in ARMInstrInfo.td llvm-svn: 124895
2011-02-04 20:47:15 +01:00
}
ARM: validate immediate branch targets in AsmParser. Immediate branch targets aren't commonly used, but if they are we should make sure they can actually be encoded. This means they must be divisible by 2 when targeting Thumb mode, and by 4 when targeting ARM mode. Also do a little naming cleanup while I was changing everything around anyway. llvm-svn: 275116
2016-07-12 00:29:37 +02:00
// Target for BLX *from* ARM mode.
def arm_blx_target : Operand<i32> {
let ParserMatchClass = ThumbBranchTarget;
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. llvm-svn: 138675
2011-08-27 01:32:08 +02:00
let EncoderMethod = "getARMBLXTargetOpValue";
let OperandType = "OPERAND_PCREL";
}
Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps. (yes, this is different from R_ARM_CALL) - Adds a new method getARMBranchTargetOpValue() which handles the necessary distinction between the conditional and unconditional br/bl needed for ARM/ELF At least for ARM mode, the needed fixup for conditional versus unconditional br/bl is identical, but the ARM docs and existing ARM tools expect this reloc type... Added a few FIXME's for future naming fixups in ARMInstrInfo.td llvm-svn: 124895
2011-02-04 20:47:15 +01:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// A list of registers separated by comma. Used by load/store multiple.
Tidy up formatting. Remove some inititalizers that are the same as the default, move defs next to their (singular) uses and generally simplify some formatting of asm operand definitions. llvm-svn: 135946
2011-07-25 22:06:30 +02:00
def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
Minor cleanups: - Get the opcode once. - Add a ParserMatchClass to reglist. llvm-svn: 118997
2010-11-13 11:40:19 +01:00
def reglist : Operand<i32> {
add fields to the .td files unconditionally, simplifying tblgen a bit. Switch the ARM backend to use 'let' instead of 'set' with this change. llvm-svn: 119120
2010-11-15 06:19:05 +01:00
let EncoderMethod = "getRegisterListOpValue";
Minor cleanups: - Get the opcode once. - Add a ParserMatchClass to reglist. llvm-svn: 118997
2010-11-13 11:40:19 +01:00
let ParserMatchClass = RegListAsmOperand;
let PrintMethod = "printRegisterList";
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeRegListOperand";
Minor cleanups: - Get the opcode once. - Add a ParserMatchClass to reglist. llvm-svn: 118997
2010-11-13 11:40:19 +01:00
}
[ARM] Add the non-MVE instructions in Arm v8.1-M. This adds support for the new family of conditional selection / increment / negation instructions; the low-overhead branch instructions (e.g. BF, WLS, DLS); the CLRM instruction to zero a whole list of registers at once; the new VMRS/VMSR and VLDR/VSTR instructions to get data in and out of 8.1-M system registers, particularly including the new VPR register used by MVE vector predication. To support this, we also add a register name 'zr' (used by the CSEL family to force one of the inputs to the constant 0), and operand types for lists of registers that are also allowed to include APSR or VPR (used by CLRM). The VLDR/VSTR instructions also need a new addressing mode. The low-overhead branch instructions exist in their own separate architecture extension, which we treat as enabled by default, but you can say -mattr=-lob or equivalent to turn it off. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Reviewed By: samparker Subscribers: miyuki, javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62667 llvm-svn: 363039
2019-06-11 11:29:18 +02:00
// A list of general purpose registers and APSR separated by comma.
// Used by CLRM
def RegListWithAPSRAsmOperand : AsmOperandClass { let Name = "RegListWithAPSR"; }
def reglist_with_apsr : Operand<i32> {
let EncoderMethod = "getRegisterListOpValue";
let ParserMatchClass = RegListWithAPSRAsmOperand;
let PrintMethod = "printRegisterList";
let DecoderMethod = "DecodeRegListOperand";
}
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
[ARM] Add diagnostics for SPR/DPR lists Differential revision: https://reviews.llvm.org/D39195 llvm-svn: 318766
2017-11-21 16:06:01 +01:00
def DPRRegListAsmOperand : AsmOperandClass {
let Name = "DPRRegList";
let DiagnosticType = "DPR_RegList";
}
Proper encoding for VLDM and VSTM instructions. The register lists for these instructions have to distinguish between lists of single- and double-precision registers in order for the ASM matcher to do a proper job. In all other respects, a list of single- or double-precision registers are the same as a list of GPR registers. llvm-svn: 119460
2010-11-17 05:32:08 +01:00
def dpr_reglist : Operand<i32> {
let EncoderMethod = "getRegisterListOpValue";
let ParserMatchClass = DPRRegListAsmOperand;
let PrintMethod = "printRegisterList";
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeDPRRegListOperand";
Proper encoding for VLDM and VSTM instructions. The register lists for these instructions have to distinguish between lists of single- and double-precision registers in order for the ASM matcher to do a proper job. In all other respects, a list of single- or double-precision registers are the same as a list of GPR registers. llvm-svn: 119460
2010-11-17 05:32:08 +01:00
}
[ARM] Add diagnostics for SPR/DPR lists Differential revision: https://reviews.llvm.org/D39195 llvm-svn: 318766
2017-11-21 16:06:01 +01:00
def SPRRegListAsmOperand : AsmOperandClass {
let Name = "SPRRegList";
let DiagnosticString = "operand must be a list of registers in range [s0, s31]";
}
Proper encoding for VLDM and VSTM instructions. The register lists for these instructions have to distinguish between lists of single- and double-precision registers in order for the ASM matcher to do a proper job. In all other respects, a list of single- or double-precision registers are the same as a list of GPR registers. llvm-svn: 119460
2010-11-17 05:32:08 +01:00
def spr_reglist : Operand<i32> {
let EncoderMethod = "getRegisterListOpValue";
let ParserMatchClass = SPRRegListAsmOperand;
let PrintMethod = "printRegisterList";
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeSPRRegListOperand";
Proper encoding for VLDM and VSTM instructions. The register lists for these instructions have to distinguish between lists of single- and double-precision registers in order for the ASM matcher to do a proper job. In all other respects, a list of single- or double-precision registers are the same as a list of GPR registers. llvm-svn: 119460
2010-11-17 05:32:08 +01:00
}
[ARM] Add the non-MVE instructions in Arm v8.1-M. This adds support for the new family of conditional selection / increment / negation instructions; the low-overhead branch instructions (e.g. BF, WLS, DLS); the CLRM instruction to zero a whole list of registers at once; the new VMRS/VMSR and VLDR/VSTR instructions to get data in and out of 8.1-M system registers, particularly including the new VPR register used by MVE vector predication. To support this, we also add a register name 'zr' (used by the CSEL family to force one of the inputs to the constant 0), and operand types for lists of registers that are also allowed to include APSR or VPR (used by CLRM). The VLDR/VSTR instructions also need a new addressing mode. The low-overhead branch instructions exist in their own separate architecture extension, which we treat as enabled by default, but you can say -mattr=-lob or equivalent to turn it off. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Reviewed By: samparker Subscribers: miyuki, javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62667 llvm-svn: 363039
2019-06-11 11:29:18 +02:00
def FPSRegListWithVPRAsmOperand : AsmOperandClass { let Name =
"FPSRegListWithVPR"; }
def fp_sreglist_with_vpr : Operand<i32> {
let EncoderMethod = "getRegisterListOpValue";
let ParserMatchClass = FPSRegListWithVPRAsmOperand;
let PrintMethod = "printRegisterList";
}
def FPDRegListWithVPRAsmOperand : AsmOperandClass { let Name =
"FPDRegListWithVPR"; }
def fp_dreglist_with_vpr : Operand<i32> {
let EncoderMethod = "getRegisterListOpValue";
let ParserMatchClass = FPDRegListWithVPRAsmOperand;
let PrintMethod = "printRegisterList";
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// An operand for the CONSTPOOL_ENTRY pseudo-instruction.
def cpinst_operand : Operand<i32> {
let PrintMethod = "printCPInstOperand";
}
// Local PC labels.
def pclabel : Operand<i32> {
let PrintMethod = "printPCLabel";
}
Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR instruction at MC lowering. Add binary encoding information for the ADR, including fixup data for the label operand. llvm-svn: 120594
2010-12-01 20:47:31 +01:00
// ADR instruction labels.
Fix #13241, a bug around shift immediate operand for ARM instruction ADR. llvm-svn: 161159
2012-08-02 10:13:13 +02:00
def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR instruction at MC lowering. Add binary encoding information for the ADR, including fixup data for the label operand. llvm-svn: 120594
2010-12-01 20:47:31 +01:00
def adrlabel : Operand<i32> {
let EncoderMethod = "getAdrLabelOpValue";
Fix #13241, a bug around shift immediate operand for ARM instruction ADR. llvm-svn: 161159
2012-08-02 10:13:13 +02:00
let ParserMatchClass = AdrLabelAsmOperand;
This corrects the implementation of Thumb ADR instruction. There are three issues: 1. it should accept only 4-byte aligned addresses 2. the maximum offset should be 1020 3. it should be encoded with the offset scaled by two bits llvm-svn: 185528
2013-07-03 11:21:44 +02:00
let PrintMethod = "printAdrLabelOperand<0>";
Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR instruction at MC lowering. Add binary encoding information for the ADR, including fixup data for the label operand. llvm-svn: 120594
2010-12-01 20:47:31 +01:00
}
Provide correct encodings for NEON vcvt, which has its own special immediate encoding for specifying fractional bits for fixed point conversions. llvm-svn: 117501
2010-10-28 00:49:00 +02:00
def neon_vcvt_imm32 : Operand<i32> {
add fields to the .td files unconditionally, simplifying tblgen a bit. Switch the ARM backend to use 'let' instead of 'set' with this change. llvm-svn: 119120
2010-11-15 06:19:05 +01:00
let EncoderMethod = "getNEONVcvtImm32OpValue";
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeVCVTImmOperand";
Provide correct encodings for NEON vcvt, which has its own special immediate encoding for specifying fractional bits for fixed point conversions. llvm-svn: 117501
2010-10-28 00:49:00 +02:00
}
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions. llvm-svn: 116421
2010-10-13 21:56:10 +02:00
// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
ARM cleanup of rot_imm encoding. Start of cleaning this up a bit. First step is to remove the encoder hook by storing the operand as the bits it'll actually encode to so it can just be directly used. Map it to the assembly source values 8/16/24 when we print it. llvm-svn: 136152
2011-07-26 23:28:43 +02:00
def rot_imm_XFORM: SDNodeXForm<imm, [{
switch (N->getZExtValue()){
Replace some assert(0)'s with llvm_unreachable. llvm-svn: 211141
2014-06-18 07:05:13 +02:00
default: llvm_unreachable(nullptr);
Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes" [DebugInfo] Add debug locations to constant SD nodes This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235989
2015-04-28 16:05:47 +02:00
case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32);
case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32);
case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32);
ARM cleanup of rot_imm encoding. Start of cleaning this up a bit. First step is to remove the encoder hook by storing the operand as the bits it'll actually encode to so it can just be directly used. Map it to the assembly source values 8/16/24 when we print it. llvm-svn: 136152
2011-07-26 23:28:43 +02:00
}
}]>;
ARM assembly parsing and encoding for extend instructions. Assembly parser handling for extend instruction rotate operands. Add tests for the sign extend instructions. llvm-svn: 136252
2011-07-27 22:15:40 +02:00
def RotImmAsmOperand : AsmOperandClass {
let Name = "RotImm";
let ParserMethod = "parseRotImm";
}
ARM cleanup of rot_imm encoding. Start of cleaning this up a bit. First step is to remove the encoder hook by storing the operand as the bits it'll actually encode to so it can just be directly used. Map it to the assembly source values 8/16/24 when we print it. llvm-svn: 136152
2011-07-26 23:28:43 +02:00
def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
int32_t v = N->getZExtValue();
return v == 8 || v == 16 || v == 24; }],
rot_imm_XFORM> {
let PrintMethod = "printRotImmOperand";
ARM assembly parsing and encoding for extend instructions. Assembly parser handling for extend instruction rotate operands. Add tests for the sign extend instructions. llvm-svn: 136252
2011-07-27 22:15:40 +02:00
let ParserMatchClass = RotImmAsmOperand;
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions. llvm-svn: 116421
2010-10-13 21:56:10 +02:00
}
[ARM] Add MVE vector instructions that take a scalar input. This adds the `MVE_qDest_rSrc` superclass and all its instances, plus a few other instructions that also take a scalar input register or two. I've also belatedly added custom diagnostic messages to the operand classes for odd- and even-numbered GPRs, which required matching changes in two of the existing MVE assembly test files. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62678 llvm-svn: 364040
2019-06-21 15:17:08 +02:00
// Power-of-two operand for MVE VIDUP and friends, which encode
// {1,2,4,8} as its log to base 2, i.e. as {0,1,2,3} respectively
def MVE_VIDUP_imm_asmoperand : AsmOperandClass {
let Name = "VIDUP_imm";
let PredicateMethod = "isPowerTwoInRange<1,8>";
let RenderMethod = "addPowerTwoOperands";
let DiagnosticString = "vector increment immediate must be 1, 2, 4 or 8";
}
def MVE_VIDUP_imm : Operand<i32> {
let EncoderMethod = "getPowerTwoOpValue";
let DecoderMethod = "DecodePowerTwoOperand<0,3>";
let ParserMatchClass = MVE_VIDUP_imm_asmoperand;
}
[ARM] Add MVE 64-bit GPR <-> vector move instructions. These instructions let you load half a vector register at once from two general-purpose registers, or vice versa. The assembly syntax for these instructions mentions the vector register name twice. For the move _into_ a vector register, the MC operand list also has to mention the register name twice (once as the output, and once as an input to represent where the unchanged half of the output register comes from). So we can conveniently assign one of the two asm operands to be the output $Qd, and the other $QdSrc, which avoids confusing the auto-generated AsmMatcher too much. For the move _from_ a vector register, there's no way to get round the fact that both instances of that register name have to be inputs, so we need a custom AsmMatchConverter to avoid generating two separate output MC operands. (And even that wouldn't have worked if it hadn't been for D60695.) Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62679 llvm-svn: 364041
2019-06-21 15:17:23 +02:00
// Pair vector indexing
class MVEPairVectorIndexOperand<string start, string end> : AsmOperandClass {
let Name = "MVEPairVectorIndex"#start;
let RenderMethod = "addMVEPairVectorIndexOperands";
let PredicateMethod = "isMVEPairVectorIndex<"#start#", "#end#">";
}
class MVEPairVectorIndex<string opval> : Operand<i32> {
let PrintMethod = "printVectorIndex";
let EncoderMethod = "getMVEPairVectorIndexOpValue<"#opval#">";
let DecoderMethod = "DecodeMVEPairVectorIndexOperand<"#opval#">";
let MIOperandInfo = (ops i32imm);
}
def MVEPairVectorIndex0 : MVEPairVectorIndex<"0"> {
let ParserMatchClass = MVEPairVectorIndexOperand<"0", "1">;
}
def MVEPairVectorIndex2 : MVEPairVectorIndex<"2"> {
let ParserMatchClass = MVEPairVectorIndexOperand<"2", "3">;
}
[ARM] Add MVE vector bit-operations (register inputs). This includes all the obvious bitwise operations (AND, OR, BIC, ORN, MVN) in register-to-register forms, and the immediate forms of AND/OR/BIC/ORN; byte-order reverse instructions; and the VMOVs that access a single lane of a vector. Some of those VMOVs (specifically, the ones that access a 32-bit lane) share an encoding with existing instructions that were disassembled as accessing half of a d-register (e.g. `vmov.32 r0, d1[0]`), but in 8.1-M they're now written as accessing a quarter of a q-register (e.g. `vmov.32 r0, q0[2]`). The older syntax is still accepted by the assembler. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62673 llvm-svn: 363838
2019-06-19 18:43:53 +02:00
// Vector indexing
class MVEVectorIndexOperand<int NumLanes> : AsmOperandClass {
let Name = "MVEVectorIndex"#NumLanes;
let RenderMethod = "addMVEVectorIndexOperands";
let PredicateMethod = "isVectorIndexInRange<"#NumLanes#">";
}
class MVEVectorIndex<int NumLanes> : Operand<i32> {
let PrintMethod = "printVectorIndex";
let ParserMatchClass = MVEVectorIndexOperand<NumLanes>;
let MIOperandInfo = (ops i32imm);
}
Rename sat_shift operand to shift_imm, in preparation for using it for other instructions besides saturate instructions. No functional changes. llvm-svn: 111168
2010-08-16 20:27:34 +02:00
// shift_imm: An integer that encodes a shift amount and the type of shift
ARM assembly parsing and encoding for SSAT instruction. Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the shift operand to correctly handle the allowed shift types and immediate ranges and issue meaningful diagnostics when an illegal value or shift type is specified. Add aliases to parse an ommitted shift operand (default value of 'lsl #0'). Add tests for diagnostics and proper encoding. llvm-svn: 135990
2011-07-26 00:20:28 +02:00
// (asr or lsl). The 6-bit immediate encodes as:
// {5} 0 ==> lsl
// 1 asr
// {4-0} imm5 shift amount.
// asr #32 encoded as imm5 == 0.
def ShifterImmAsmOperand : AsmOperandClass {
let Name = "ShifterImm";
let ParserMethod = "parseShifterImm";
}
Rename sat_shift operand to shift_imm, in preparation for using it for other instructions besides saturate instructions. No functional changes. llvm-svn: 111168
2010-08-16 20:27:34 +02:00
def shift_imm : Operand<i32> {
let PrintMethod = "printShiftImmOperand";
ARM assembly parsing and encoding for SSAT instruction. Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the shift operand to correctly handle the allowed shift types and immediate ranges and issue meaningful diagnostics when an illegal value or shift type is specified. Add aliases to parse an ommitted shift operand (default value of 'lsl #0'). Add tests for diagnostics and proper encoding. llvm-svn: 135990
2011-07-26 00:20:28 +02:00
let ParserMatchClass = ShifterImmAsmOperand;
Rename sat_shift operand to shift_imm, in preparation for using it for other instructions besides saturate instructions. No functional changes. llvm-svn: 111168
2010-08-16 20:27:34 +02:00
}
[ARM] Cleanup so_imm* tblgen defintions No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
2015-01-06 16:55:09 +01:00
// shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm.
ARM asm operand renaming. Make things a bit more explicit. llvm-svn: 135959
2011-07-25 22:49:51 +02:00
def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
def so_reg_reg : Operand<i32>, // reg reg imm
ComplexPattern<i32, 3, "SelectRegShifterOperand",
[shl, srl, sra, rotr]> {
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. llvm-svn: 135722
2011-07-22 01:38:37 +02:00
let EncoderMethod = "getSORegRegOpValue";
let PrintMethod = "printSORegRegOperand";
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeSORegRegOperand";
Flesh out ARM Parser support for shifted-register operands. Now works for parsing register shifted register and register shifted immediate arithmetic instructions, including the 'rrx' rotate with extend. llvm-svn: 135049
2011-07-13 19:50:29 +02:00
let ParserMatchClass = ShiftedRegAsmOperand;
Tighten operand checking of register-shifted-register operands. llvm-svn: 137180
2011-08-10 01:33:27 +02:00
let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
}
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
ARM asm operand renaming. Make things a bit more explicit. llvm-svn: 135959
2011-07-25 22:49:51 +02:00
def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
def so_reg_imm : Operand<i32>, // reg imm
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. llvm-svn: 135722
2011-07-22 01:38:37 +02:00
ComplexPattern<i32, 2, "SelectImmShifterOperand",
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
[shl, srl, sra, rotr]> {
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. llvm-svn: 135722
2011-07-22 01:38:37 +02:00
let EncoderMethod = "getSORegImmOpValue";
let PrintMethod = "printSORegImmOperand";
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeSORegImmOperand";
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
let ParserMatchClass = ShiftedImmAsmOperand;
Simply ARM so_reg MIOperandInfo definitions. The shift immediate encoding, printing, etc. is handled directly by the enclosing operand definition, so it should be a vanilla immediate, not a nested complex operand (shift_imm). llvm-svn: 135968
2011-07-25 23:04:58 +02:00
let MIOperandInfo = (ops GPR, i32imm);
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
}
Flesh out ARM Parser support for shifted-register operands. Now works for parsing register shifted register and register shifted immediate arithmetic instructions, including the 'rrx' rotate with extend. llvm-svn: 135049
2011-07-13 19:50:29 +02:00
// FIXME: Does this need to be distinct from so_reg?
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. llvm-svn: 135722
2011-07-22 01:38:37 +02:00
def shift_so_reg_reg : Operand<i32>, // reg reg imm
ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
Shifter ops are not always free. Do not fold them (especially to form complex load / store addressing mode) when they have higher cost and when they have more than one use. llvm-svn: 117509
2010-10-28 01:41:30 +02:00
[shl,srl,sra,rotr]> {
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. llvm-svn: 135722
2011-07-22 01:38:37 +02:00
let EncoderMethod = "getSORegRegOpValue";
let PrintMethod = "printSORegRegOperand";
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeSORegRegOperand";
ARM assembly parsing for shifted register operands for MOV instruction. llvm-svn: 144837
2011-11-16 22:50:05 +01:00
let ParserMatchClass = ShiftedRegAsmOperand;
Simply ARM so_reg MIOperandInfo definitions. The shift immediate encoding, printing, etc. is handled directly by the enclosing operand definition, so it should be a vanilla immediate, not a nested complex operand (shift_imm). llvm-svn: 135968
2011-07-25 23:04:58 +02:00
let MIOperandInfo = (ops GPR, GPR, i32imm);
Shifter ops are not always free. Do not fold them (especially to form complex load / store addressing mode) when they have higher cost and when they have more than one use. llvm-svn: 117509
2010-10-28 01:41:30 +02:00
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. llvm-svn: 135722
2011-07-22 01:38:37 +02:00
// FIXME: Does this need to be distinct from so_reg?
def shift_so_reg_imm : Operand<i32>, // reg reg imm
ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
[shl,srl,sra,rotr]> {
let EncoderMethod = "getSORegImmOpValue";
let PrintMethod = "printSORegImmOperand";
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeSORegImmOperand";
ARM assembly parsing for shifted register operands for MOV instruction. llvm-svn: 144837
2011-11-16 22:50:05 +01:00
let ParserMatchClass = ShiftedImmAsmOperand;
Simply ARM so_reg MIOperandInfo definitions. The shift immediate encoding, printing, etc. is handled directly by the enclosing operand definition, so it should be a vanilla immediate, not a nested complex operand (shift_imm). llvm-svn: 135968
2011-07-25 23:04:58 +02:00
let MIOperandInfo = (ops GPR, i32imm);
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. llvm-svn: 135722
2011-07-22 01:38:37 +02:00
}
[ARM] Cleanup so_imm* tblgen defintions No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
2015-01-06 16:55:09 +01:00
// mod_imm: match a 32-bit immediate operand, which can be encoded into
// a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM
// - "Modified Immediate Constants"). Within the MC layer we keep this
// immediate in its encoded form.
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
def ModImmAsmOperand: AsmOperandClass {
let Name = "ModImm";
let ParserMethod = "parseModImm";
}
def mod_imm : Operand<i32>, ImmLeaf<i32, [{
return ARM_AM::getSOImmVal(Imm) != -1;
}]> {
let EncoderMethod = "getModImmOpValue";
let PrintMethod = "printModImmOperand";
let ParserMatchClass = ModImmAsmOperand;
}
[ARM] Cleanup so_imm* tblgen defintions No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
2015-01-06 16:55:09 +01:00
// Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder
// method and such, as they are only used on aliases (Pat<> and InstAlias<>).
// The actual parsing, encoding, decoding are handled by the destination
// instructions, which use mod_imm.
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; }
def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{
return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
}], imm_not_XFORM> {
let ParserMatchClass = ModImmNotAsmOperand;
}
def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; }
def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{
unsigned Value = -(unsigned)N->getZExtValue();
return Value && ARM_AM::getSOImmVal(Value) != -1;
}], imm_neg_XFORM> {
let ParserMatchClass = ModImmNegAsmOperand;
}
[ARM] Cleanup so_imm* tblgen defintions No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
2015-01-06 16:55:09 +01:00
/// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal()
[ARM GlobalISel] Make arm_i32imm an IntImmLeaf This gets rid of some duplication in the TableGen definition, but it forces us to keep both a pointer and a reference to the subtarget in the ARMInstructionSelector. That is pretty ugly but it might be a reasonable trade-off, since the TableGen descriptions should outlive the code in the selector (or in the worst case we can update to use just the reference when we get rid of DAGISel). Differential Revision: https://reviews.llvm.org/D58031 llvm-svn: 355083
2019-02-28 12:13:05 +01:00
def arm_i32imm : IntImmLeaf<i32, [{
[ARM] Add OptMinSize to ARMSubtarget In many places in the backend, we like to know whether we're optimising for code size and this is performed by checking the current machine function attributes. A subtarget is created on a per-function basis, so it's possible to know when we're compiling for code size on construction so record this in the new object. Differential Revision: https://reviews.llvm.org/D57812 llvm-svn: 353501
2019-02-08 08:57:42 +01:00
if (Subtarget->useMovt())
For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled with movi + orr. llvm-svn: 118945
2010-11-13 00:46:13 +01:00
return true;
[ARM GlobalISel] Make arm_i32imm an IntImmLeaf This gets rid of some duplication in the TableGen definition, but it forces us to keep both a pointer and a reference to the subtarget in the ARMInstructionSelector. That is pretty ugly but it might be a reasonable trade-off, since the TableGen descriptions should outlive the code in the selector (or in the worst case we can update to use just the reference when we get rid of DAGISel). Differential Revision: https://reviews.llvm.org/D58031 llvm-svn: 355083
2019-02-28 12:13:05 +01:00
return ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue());
}]>;
Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool. llvm-svn: 35207
2007-03-20 09:11:30 +01:00
ARM NEON VEXT aliases for data type suffices. llvm-svn: 145726
2011-12-03 00:34:39 +01:00
/// imm0_1 predicate - Immediate in the range [0,1].
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
def Imm0_1AsmOperand: ImmAsmOperand<0,1> { let Name = "Imm0_1"; }
ARM NEON VEXT aliases for data type suffices. llvm-svn: 145726
2011-12-03 00:34:39 +01:00
def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
/// imm0_3 predicate - Immediate in the range [0,3].
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
def Imm0_3AsmOperand: ImmAsmOperand<0,3> { let Name = "Imm0_3"; }
ARM NEON VEXT aliases for data type suffices. llvm-svn: 145726
2011-12-03 00:34:39 +01:00
def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
Fix comments. llvm-svn: 136655
2011-08-01 23:55:12 +02:00
/// imm0_7 predicate - Immediate in the range [0,7].
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
def Imm0_7AsmOperand: ImmAsmOperand<0,7> {
let Name = "Imm0_7";
}
Range checking for CDP[2] immediates. llvm-svn: 135092
2011-07-14 00:01:08 +02:00
def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
return Imm >= 0 && Imm < 8;
}]> {
let ParserMatchClass = Imm0_7AsmOperand;
}
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
/// imm8_255 predicate - Immediate in the range [8,255].
def Imm8_255AsmOperand: ImmAsmOperand<8,255> { let Name = "Imm8_255"; }
def imm8_255 : Operand<i32>, ImmLeaf<i32, [{
return Imm >= 8 && Imm < 256;
}]> {
let ParserMatchClass = Imm8_255AsmOperand;
}
ARM: NEON SHLL instruction immediate operand range checking. llvm-svn: 146003
2011-12-07 02:07:24 +01:00
/// imm8 predicate - Immediate is exactly 8.
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
def Imm8AsmOperand: ImmAsmOperand<8,8> { let Name = "Imm8"; }
ARM: NEON SHLL instruction immediate operand range checking. llvm-svn: 146003
2011-12-07 02:07:24 +01:00
def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
let ParserMatchClass = Imm8AsmOperand;
}
/// imm16 predicate - Immediate is exactly 16.
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
def Imm16AsmOperand: ImmAsmOperand<16,16> { let Name = "Imm16"; }
ARM: NEON SHLL instruction immediate operand range checking. llvm-svn: 146003
2011-12-07 02:07:24 +01:00
def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
let ParserMatchClass = Imm16AsmOperand;
}
/// imm32 predicate - Immediate is exactly 32.
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
def Imm32AsmOperand: ImmAsmOperand<32,32> { let Name = "Imm32"; }
ARM: NEON SHLL instruction immediate operand range checking. llvm-svn: 146003
2011-12-07 02:07:24 +01:00
def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
let ParserMatchClass = Imm32AsmOperand;
}
ARM: add patterns for [su]xta[bh] from just a shift. Although the final shifter operand is a rotate, this actually only matters for the half-word extends when the amount == 24. Otherwise folding a shift in is just as good. llvm-svn: 213753
2014-07-23 15:59:07 +02:00
def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>;
ARM: NEON SHLL instruction immediate operand range checking. llvm-svn: 146003
2011-12-07 02:07:24 +01:00
/// imm1_7 predicate - Immediate in the range [1,7].
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
def Imm1_7AsmOperand: ImmAsmOperand<1,7> { let Name = "Imm1_7"; }
ARM: NEON SHLL instruction immediate operand range checking. llvm-svn: 146003
2011-12-07 02:07:24 +01:00
def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
let ParserMatchClass = Imm1_7AsmOperand;
}
/// imm1_15 predicate - Immediate in the range [1,15].
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
def Imm1_15AsmOperand: ImmAsmOperand<1,15> { let Name = "Imm1_15"; }
ARM: NEON SHLL instruction immediate operand range checking. llvm-svn: 146003
2011-12-07 02:07:24 +01:00
def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
let ParserMatchClass = Imm1_15AsmOperand;
}
/// imm1_31 predicate - Immediate in the range [1,31].
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
def Imm1_31AsmOperand: ImmAsmOperand<1,31> { let Name = "Imm1_31"; }
ARM: NEON SHLL instruction immediate operand range checking. llvm-svn: 146003
2011-12-07 02:07:24 +01:00
def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
let ParserMatchClass = Imm1_31AsmOperand;
}
Fix comments. llvm-svn: 136655
2011-08-01 23:55:12 +02:00
/// imm0_15 predicate - Immediate in the range [0,15].
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
def Imm0_15AsmOperand: ImmAsmOperand<0,15> {
ARM: Add a better diagnostic for some out of range immediates. As an example of how the custom DiagnosticType can be used to provide better operand-mismatch diagnostics, add a custom diagnostic for the imm0_15 operand class used for several system instructions. Update the tests to expect the improved diagnostic. rdar://8987109 llvm-svn: 159051
2012-06-23 01:56:48 +02:00
let Name = "Imm0_15";
}
Range checking for CDP[2] immediates. llvm-svn: 135092
2011-07-14 00:01:08 +02:00
def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
return Imm >= 0 && Imm < 16;
}]> {
let ParserMatchClass = Imm0_15AsmOperand;
}
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. llvm-svn: 84009
2009-10-13 20:59:48 +02:00
/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
def Imm0_31AsmOperand: ImmAsmOperand<0,31> { let Name = "Imm0_31"; }
Let the immediate leaf pattern take transforms and switch the signed immediate patterns in arm to using the pattern. Handles rdar://9299434 llvm-svn: 130386
2011-04-28 07:49:04 +02:00
def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
return Imm >= 0 && Imm < 32;
ARM fix asm parsing range check for [0,31] immediates. llvm-svn: 136091
2011-07-26 18:44:05 +02:00
}]> {
let ParserMatchClass = Imm0_31AsmOperand;
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
ARM assembly parsing for LSR/LSL/ROR(immediate). More of rdar://9704684 llvm-svn: 144301
2011-11-10 20:18:01 +01:00
/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
def Imm0_32AsmOperand: ImmAsmOperand<0,32> { let Name = "Imm0_32"; }
ARM assembly parsing for LSR/LSL/ROR(immediate). More of rdar://9704684 llvm-svn: 144301
2011-11-10 20:18:01 +01:00
def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
return Imm >= 0 && Imm < 33;
ARM assembly parsing for LSR/LSL/ROR(immediate). More of rdar://9704684 llvm-svn: 144301
2011-11-10 20:18:01 +01:00
}]> {
let ParserMatchClass = Imm0_32AsmOperand;
}
ARM NEON two-operand aliases for VSHL(immediate). llvm-svn: 146125
2011-12-08 02:30:04 +01:00
/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
def Imm0_63AsmOperand: ImmAsmOperand<0,63> { let Name = "Imm0_63"; }
ARM NEON two-operand aliases for VSHL(immediate). llvm-svn: 146125
2011-12-08 02:30:04 +01:00
def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
return Imm >= 0 && Imm < 64;
}]> {
let ParserMatchClass = Imm0_63AsmOperand;
}
Make ARM hint ranges consistent, and add tests for these ranges llvm-svn: 193238
2013-10-23 12:14:40 +02:00
/// imm0_239 predicate - Immediate in the range [0,239].
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
def Imm0_239AsmOperand : ImmAsmOperand<0,239> {
Make ARM hint ranges consistent, and add tests for these ranges llvm-svn: 193238
2013-10-23 12:14:40 +02:00
let Name = "Imm0_239";
}
def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
let ParserMatchClass = Imm0_239AsmOperand;
}
Move imm0_255 to ARMInstrInfo.td with the other immediate predicates. llvm-svn: 136656
2011-08-02 00:02:20 +02:00
/// imm0_255 predicate - Immediate in the range [0,255].
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
def Imm0_255AsmOperand : ImmAsmOperand<0,255> { let Name = "Imm0_255"; }
Move imm0_255 to ARMInstrInfo.td with the other immediate predicates. llvm-svn: 136656
2011-08-02 00:02:20 +02:00
def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
let ParserMatchClass = Imm0_255AsmOperand;
}
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
/// imm0_65535 - An immediate is in the range [0,65535].
def Imm0_65535AsmOperand: ImmAsmOperand<0,65535> { let Name = "Imm0_65535"; }
ARM refactor simple immediate asm operand render methods. These immediate operands all use the same simple logic for rendering to MCInst, so have them share the method for doing so. llvm-svn: 144439
2011-11-12 01:58:43 +01:00
def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
return Imm >= 0 && Imm < 65536;
}]> {
let ParserMatchClass = Imm0_65535AsmOperand;
}
(sub X, imm) gets canonicalized to (add X, -imm) There are patterns to handle immediates when they fit in the immediate field. e.g. %sub = add i32 %x, -123 => sub r0, r0, #123 Add patterns to catch immediates that do not fit but should be materialized with a single movw instruction rather than movw + movt pair. e.g. %sub = add i32 %x, -65535 => movw r1, #65535 sub r0, r0, r1 rdar://11726136 llvm-svn: 159057
2012-06-23 02:29:06 +02:00
// imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
return -Imm >= 0 && -Imm < 65536;
}]>;
ARM assembly parsing for MOV (immediate). Add range checking for the immediate operand and handle the "mov" mnemonic choosing between encodings based on the value of the immediate. Add tests for fixups, encoding choice and values, and diagnostic for out of range values. llvm-svn: 135500
2011-07-19 21:13:28 +02:00
// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
// a relocatable expression.
Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM. Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired. Existing tests cover this update. llvm-svn: 119760
2010-11-19 00:37:15 +01:00
//
ARM assembly parsing for MOV (immediate). Add range checking for the immediate operand and handle the "mov" mnemonic choosing between encodings based on the value of the immediate. Add tests for fixups, encoding choice and values, and diagnostic for out of range values. llvm-svn: 135500
2011-07-19 21:13:28 +02:00
// FIXME: This really needs a Thumb version separate from the ARM version.
// While the range is the same, and can thus use the same match class,
// the encoding is different so it should have a different encoder method.
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
def Imm0_65535ExprAsmOperand: AsmOperandClass {
let Name = "Imm0_65535Expr";
let RenderMethod = "addImmOperands";
[ARM] Add diag string for movw/movt immediates in assembly This adds diagnostics for invalid immediate operands to the MOVW and MOVT instructions (ARM and Thumb). Differential revision: https://reviews.llvm.org/D31879 llvm-svn: 314888
2017-10-04 11:24:54 +02:00
let DiagnosticString = "operand must be an immediate in the range [0,0xffff] or a relocatable expression";
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
}
ARM assembly parsing for MOV (immediate). Add range checking for the immediate operand and handle the "mov" mnemonic choosing between encodings based on the value of the immediate. Add tests for fixups, encoding choice and values, and diagnostic for out of range values. llvm-svn: 135500
2011-07-19 21:13:28 +02:00
def imm0_65535_expr : Operand<i32> {
Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step in the right direction. It eliminated some hacks and will unblock codegen work. But it's far from being done. It doesn't reject illegal expressions, e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all. llvm-svn: 123369
2011-01-13 08:58:56 +01:00
let EncoderMethod = "getHiLo16ImmOpValue";
ARM assembly parsing for MOV (immediate). Add range checking for the immediate operand and handle the "mov" mnemonic choosing between encodings based on the value of the immediate. Add tests for fixups, encoding choice and values, and diagnostic for out of range values. llvm-svn: 135500
2011-07-19 21:13:28 +02:00
let ParserMatchClass = Imm0_65535ExprAsmOperand;
Make "mov" work for all Thumb2 MOV encodings According to the ARM specification, "mov" is a valid mnemonic for all Thumb2 MOV encodings. To achieve this, the patch adds one instruction alias with a special range condition to avoid collision with the Thumb1 MOV. llvm-svn: 188901
2013-08-21 15:14:58 +02:00
}
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
def Imm256_65535ExprAsmOperand: ImmAsmOperand<256,65535> { let Name = "Imm256_65535Expr"; }
Make "mov" work for all Thumb2 MOV encodings According to the ARM specification, "mov" is a valid mnemonic for all Thumb2 MOV encodings. To achieve this, the patch adds one instruction alias with a special range condition to avoid collision with the Thumb1 MOV. llvm-svn: 188901
2013-08-21 15:14:58 +02:00
def imm256_65535_expr : Operand<i32> {
let ParserMatchClass = Imm256_65535ExprAsmOperand;
Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM. Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired. Existing tests cover this update. llvm-svn: 119760
2010-11-19 00:37:15 +01:00
}
ARM parsing and encoding for SVC instruction. llvm-svn: 136090
2011-07-26 18:24:27 +02:00
/// imm24b - True if the 32-bit immediate is encodable in 24 bits.
[ARM] Use table-gen'd assembly operand diags in ARM asm parser This switches the ARM AsmParser to use assembly operand diagnostics from tablegen, rather than a switch statement on the ARMMatchResultTy. It moves the existing diagnostic strings to tablegen, but adds no new ones, so this is NFC except for one diagnostic string that had an off-by-1 error in the hand-written switch statement. Differential revision: https://reviews.llvm.org/D31607 llvm-svn: 314804
2017-10-03 16:38:52 +02:00
def Imm24bitAsmOperand: ImmAsmOperand<0,0xffffff> {
let Name = "Imm24bit";
[ARM, Asm] Change grammar of immediate operand diagnostics Currently, our diagnostics for assembly operands are not consistent. Some start with (for example) "immediate operand must be ...", and some with "operand must be an immediate ...". I think the latter form is preferable for a few reasons: * It's unambiguous that it is referring to the expected type of operand, not the type the user provided. For example, the user could provide an register operand, and get a message taking about an operand is if it is already an immediate, just not in the accepted range. * It allows us to have a consistent style once we add diagnostics for operands that could take two forms, for example a label or pc-relative memory operand. Differential revision: https://reviews.llvm.org/D36689 llvm-svn: 314887
2017-10-04 11:18:07 +02:00
let DiagnosticString = "operand must be an immediate in the range [0,0xffffff]";
[ARM] Use table-gen'd assembly operand diags in ARM asm parser This switches the ARM AsmParser to use assembly operand diagnostics from tablegen, rather than a switch statement on the ARMMatchResultTy. It moves the existing diagnostic strings to tablegen, but adds no new ones, so this is NFC except for one diagnostic string that had an off-by-1 error in the hand-written switch statement. Differential revision: https://reviews.llvm.org/D31607 llvm-svn: 314804
2017-10-03 16:38:52 +02:00
}
ARM parsing and encoding for SVC instruction. llvm-svn: 136090
2011-07-26 18:24:27 +02:00
def imm24b : Operand<i32>, ImmLeaf<i32, [{
return Imm >= 0 && Imm <= 0xffffff;
}]> {
let ParserMatchClass = Imm24bitAsmOperand;
}
(or (and (shl A, #shamt), mask), B) => ARMbfi B, A, ~mask where lsb(mask) == #shamt. rdar://8752056 llvm-svn: 121606
2010-12-11 05:11:38 +01:00
/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
/// e.g., 0xf000ffff
ARM assembly parsing and encoding for BFC and BFI. Add parsing support that handles converting the lsb+width source into the odd way we represent the instruction (an inverted bitfield mask). llvm-svn: 136399
2011-07-28 23:34:26 +02:00
def BitfieldAsmOperand : AsmOperandClass {
let Name = "Bitfield";
let ParserMethod = "parseBitfield";
}
Test Commit - add a newline llvm-svn: 153083
2012-03-20 11:50:35 +01:00
(or (and (shl A, #shamt), mask), B) => ARMbfi B, A, ~mask where lsb(mask) == #shamt. rdar://8752056 llvm-svn: 121606
2010-12-11 05:11:38 +01:00
def bf_inv_mask_imm : Operand<i32>,
PatLeaf<(imm), [{
return ARM::isBitFieldInvertedMask(N->getZExtValue());
}] > {
let EncoderMethod = "getBitfieldInvertedMaskOpValue";
let PrintMethod = "printBitfieldInvMaskImmOperand";
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeBitfieldMaskOperand";
ARM assembly parsing and encoding for BFC and BFI. Add parsing support that handles converting the lsb+width source into the odd way we represent the instruction (an inverted bitfield mask). llvm-svn: 136399
2011-07-28 23:34:26 +02:00
let ParserMatchClass = BitfieldAsmOperand;
[globalisel][tablegen] Add support for C++ predicates on PatFrags and use it to support BFC on ARM. So far, we've only handled special cases of PatFrag like ImmLeaf. This patch adds support for the remaining cases using similar mechanisms. Like most C++ code from SelectionDAG, GISel and DAGISel expect to operate on different types and representations and as such the code is not compatible between the two. It's therefore necessary to add an alternative implementation in the GISelPredicateCode field. The target test for this feature could easily be done with IntImmLeaf and this would save on a little boilerplate. The reason I've chosen to implement this using PatFrag.GISelPredicateCode and not IntImmLeaf is because I was unable to find a rule that was blocked solely by lack of support for PatFrag predicates. I found that the ones I investigated as being likely candidates for the test were further blocked by other things. llvm-svn: 334871
2018-06-16 01:13:43 +02:00
let GISelPredicateCode = [{
// There's better methods of implementing this check. IntImmLeaf<> would be
// equivalent and have less boilerplate but we need a test for C++
// predicates and this one causes new rules to be imported into GlobalISel
// without requiring additional features first.
const auto &MO = MI.getOperand(1);
if (!MO.isCImm())
return false;
return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue());
}];
(or (and (shl A, #shamt), mask), B) => ARMbfi B, A, ~mask where lsb(mask) == #shamt. rdar://8752056 llvm-svn: 121606
2010-12-11 05:11:38 +01:00
}
ARM SSAT instruction 5-bit immediate handling. The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield. Update the representation such that we store the operand as 0-31, allowing us to remove the encoder method and the special case handling in the disassembler. Update the assembly parser and the instruction printer accordingly. llvm-svn: 135823
2011-07-23 01:16:18 +02:00
def imm1_32_XFORM: SDNodeXForm<imm, [{
Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes" [DebugInfo] Add debug locations to constant SD nodes This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235989
2015-04-28 16:05:47 +02:00
return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
MVT::i32);
ARM SSAT instruction 5-bit immediate handling. The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield. Update the representation such that we store the operand as 0-31, allowing us to remove the encoder method and the special case handling in the disassembler. Update the assembly parser and the instruction printer accordingly. llvm-svn: 135823
2011-07-23 01:16:18 +02:00
}]>;
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
def Imm1_32AsmOperand: ImmAsmOperandMinusOne<1,32> {
let Name = "Imm1_32";
}
Fix predicate for imm1_32 llvm-svn: 137865
2011-08-17 23:01:11 +02:00
def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
uint64_t Imm = N->getZExtValue();
return Imm > 0 && Imm <= 32;
}],
ARM SSAT instruction 5-bit immediate handling. The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield. Update the representation such that we store the operand as 0-31, allowing us to remove the encoder method and the special case handling in the disassembler. Update the assembly parser and the instruction printer accordingly. llvm-svn: 135823
2011-07-23 01:16:18 +02:00
imm1_32_XFORM> {
ARM assembly parsing and encoding for SSAT16 instruction. llvm-svn: 136006
2011-07-26 01:09:14 +02:00
let PrintMethod = "printImmPlusOneOperand";
ARM SSAT instruction 5-bit immediate handling. The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield. Update the representation such that we store the operand as 0-31, allowing us to remove the encoder method and the special case handling in the disassembler. Update the assembly parser and the instruction printer accordingly. llvm-svn: 135823
2011-07-23 01:16:18 +02:00
let ParserMatchClass = Imm1_32AsmOperand;
Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value must be encoded decremented by one. Only add encoding tests for ssat16 because ssat can't be parsed yet. llvm-svn: 132324
2011-05-31 05:33:27 +02:00
}
ARM assembly parsing and encoding for SSAT16 instruction. llvm-svn: 136006
2011-07-26 01:09:14 +02:00
def imm1_16_XFORM: SDNodeXForm<imm, [{
Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes" [DebugInfo] Add debug locations to constant SD nodes This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235989
2015-04-28 16:05:47 +02:00
return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
MVT::i32);
ARM assembly parsing and encoding for SSAT16 instruction. llvm-svn: 136006
2011-07-26 01:09:14 +02:00
}]>;
ARMAsmParser: clean up of isImmediate functions - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
2017-04-03 16:50:04 +02:00
def Imm1_16AsmOperand: ImmAsmOperandMinusOne<1,16> { let Name = "Imm1_16"; }
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
def imm1_16 : Operand<i32>, ImmLeaf<i32, [{
return Imm > 0 && Imm <= 16;
}],
ARM assembly parsing and encoding for SSAT16 instruction. llvm-svn: 136006
2011-07-26 01:09:14 +02:00
imm1_16_XFORM> {
let PrintMethod = "printImmPlusOneOperand";
let ParserMatchClass = Imm1_16AsmOperand;
}
[ARM] Add MVE vector shift instructions. This includes saturating and non-saturating shifts, both with immediate shift count and with the shift counts given by another vector register; VSHLC (in which the bits shifted out of each active vector lane are shifted in to the next active lane); and also VMOVL, which is enough like an immediate shift that it didn't fit too badly in this category. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62672 llvm-svn: 363696
2019-06-18 18:19:59 +02:00
def MVEShiftImm1_7AsmOperand: ImmAsmOperand<1,7> {
let Name = "MVEShiftImm1_7";
// Reason we're doing this is because instruction vshll.s8 t1 encoding
// accepts 1,7 but the t2 encoding accepts 8. By doing this we can get a
// better diagnostic message if someone uses bigger immediate than the t1/t2
// encodings allow.
let DiagnosticString = "operand must be an immediate in the range [1,8]";
}
def mve_shift_imm1_7 : Operand<i32> {
let ParserMatchClass = MVEShiftImm1_7AsmOperand;
let EncoderMethod = "getMVEShiftImmOpValue";
}
def MVEShiftImm1_15AsmOperand: ImmAsmOperand<1,15> {
let Name = "MVEShiftImm1_15";
// Reason we're doing this is because instruction vshll.s16 t1 encoding
// accepts 1,15 but the t2 encoding accepts 16. By doing this we can get a
// better diagnostic message if someone uses bigger immediate than the t1/t2
// encodings allow.
let DiagnosticString = "operand must be an immediate in the range [1,16]";
}
def mve_shift_imm1_15 : Operand<i32> {
let ParserMatchClass = MVEShiftImm1_15AsmOperand;
let EncoderMethod = "getMVEShiftImmOpValue";
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// Define ARM specific addressing modes.
First part of refactoring ARM addrmode2 (load/store) instructions to be more explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
2010-10-27 00:37:02 +02:00
// addrmode_imm12 := reg +/- imm12
Add specializations of addrmode2 that allow differentiating those forms which require the use of the shifter-operand. This will be used to split the ldr/str instructions such that those versions needing the shifter operand can get a different scheduling itenerary, as in some cases, the use of the shifter can cause different scheduling than the simpler forms. llvm-svn: 115066
2010-09-29 21:03:54 +02:00
//
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
[ARM] Mark a bunch of .td Operands with type _MEMORY. This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
2015-04-07 22:31:16 +02:00
class AddrMode_Imm12 : MemOperand,
First part of refactoring ARM addrmode2 (load/store) instructions to be more explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
2010-10-27 00:37:02 +02:00
ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. llvm-svn: 117571
2010-10-28 20:34:10 +02:00
// 12-bit immediate operand. Note that instructions using this encode
// #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
// immediate values are as normal.
First part of refactoring ARM addrmode2 (load/store) instructions to be more explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
2010-10-27 00:37:02 +02:00
add fields to the .td files unconditionally, simplifying tblgen a bit. Switch the ARM backend to use 'let' instead of 'set' with this change. llvm-svn: 119120
2010-11-15 06:19:05 +01:00
let EncoderMethod = "getAddrModeImm12OpValue";
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeAddrModeImm12Operand";
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
let ParserMatchClass = MemImm12OffsetAsmOperand;
First part of refactoring ARM addrmode2 (load/store) instructions to be more explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
2010-10-27 00:37:02 +02:00
let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
Add specializations of addrmode2 that allow differentiating those forms which require the use of the shifter-operand. This will be used to split the ldr/str instructions such that those versions needing the shifter operand can get a different scheduling itenerary, as in some cases, the use of the shifter can cause different scheduling than the simpler forms. llvm-svn: 115066
2010-09-29 21:03:54 +02:00
}
ARM: Correct printing of pre-indexed operands. According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
2013-04-12 20:47:25 +02:00
def addrmode_imm12 : AddrMode_Imm12 {
let PrintMethod = "printAddrModeImm12Operand<false>";
}
def addrmode_imm12_pre : AddrMode_Imm12 {
let PrintMethod = "printAddrModeImm12Operand<true>";
}
First part of refactoring ARM addrmode2 (load/store) instructions to be more explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
2010-10-27 00:37:02 +02:00
// ldst_so_reg := reg +/- reg shop imm
Add specializations of addrmode2 that allow differentiating those forms which require the use of the shifter-operand. This will be used to split the ldr/str instructions such that those versions needing the shifter operand can get a different scheduling itenerary, as in some cases, the use of the shifter can cause different scheduling than the simpler forms. llvm-svn: 115066
2010-09-29 21:03:54 +02:00
//
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
[ARM] Mark a bunch of .td Operands with type _MEMORY. This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
2015-04-07 22:31:16 +02:00
def ldst_so_reg : MemOperand,
First part of refactoring ARM addrmode2 (load/store) instructions to be more explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
2010-10-27 00:37:02 +02:00
ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
add fields to the .td files unconditionally, simplifying tblgen a bit. Switch the ARM backend to use 'let' instead of 'set' with this change. llvm-svn: 119120
2010-11-15 06:19:05 +01:00
let EncoderMethod = "getLdStSORegOpValue";
First part of refactoring ARM addrmode2 (load/store) instructions to be more explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
2010-10-27 00:37:02 +02:00
// FIXME: Simplify the printer
Add specializations of addrmode2 that allow differentiating those forms which require the use of the shifter-operand. This will be used to split the ldr/str instructions such that those versions needing the shifter operand can get a different scheduling itenerary, as in some cases, the use of the shifter can cause different scheduling than the simpler forms. llvm-svn: 115066
2010-09-29 21:03:54 +02:00
let PrintMethod = "printAddrMode2Operand";
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeSORegMemOperand";
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
let ParserMatchClass = MemRegOffsetAsmOperand;
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. llvm-svn: 137323
2011-08-11 20:55:42 +02:00
let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
Add specializations of addrmode2 that allow differentiating those forms which require the use of the shifter-operand. This will be used to split the ldr/str instructions such that those versions needing the shifter operand can get a different scheduling itenerary, as in some cases, the use of the shifter can cause different scheduling than the simpler forms. llvm-svn: 115066
2010-09-29 21:03:54 +02:00
}
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
// postidx_imm8 := +/- [0,255]
//
// 9 bit value:
// {8} 1 is imm8 is non-negative. 0 otherwise.
// {7-0} [0,255] imm8 value.
def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
[ARM] Mark a bunch of .td Operands with type _MEMORY. This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
2015-04-07 22:31:16 +02:00
def postidx_imm8 : MemOperand {
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
let PrintMethod = "printPostIdxImm8Operand";
let ParserMatchClass = PostIdxImm8AsmOperand;
let MIOperandInfo = (ops i32imm);
}
LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them. llvm-svn: 136896
2011-08-04 20:24:14 +02:00
// postidx_imm8s4 := +/- [0,1020]
//
// 9 bit value:
// {8} 1 is imm8 is non-negative. 0 otherwise.
// {7-0} [0,255] imm8 value, scaled by 4.
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
[ARM] Mark a bunch of .td Operands with type _MEMORY. This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
2015-04-07 22:31:16 +02:00
def postidx_imm8s4 : MemOperand {
LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them. llvm-svn: 136896
2011-08-04 20:24:14 +02:00
let PrintMethod = "printPostIdxImm8s4Operand";
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
let ParserMatchClass = PostIdxImm8s4AsmOperand;
LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them. llvm-svn: 136896
2011-08-04 20:24:14 +02:00
let MIOperandInfo = (ops i32imm);
}
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
// postidx_reg := +/- reg
//
def PostIdxRegAsmOperand : AsmOperandClass {
let Name = "PostIdxReg";
let ParserMethod = "parsePostIdxReg";
}
[ARM] Mark a bunch of .td Operands with type _MEMORY. This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
2015-04-07 22:31:16 +02:00
def postidx_reg : MemOperand {
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
let EncoderMethod = "getPostIdxRegOpValue";
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodePostIdxReg";
ARM use a dedicated printer for postidx_reg operands. llvm-svn: 136968
2011-08-05 17:48:21 +02:00
let PrintMethod = "printPostIdxRegOperand";
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
let ParserMatchClass = PostIdxRegAsmOperand;
Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM llvm-svn: 153251
2012-03-22 14:24:43 +01:00
let MIOperandInfo = (ops GPRnopc, i32imm);
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
}
ARM indexed load assembly parsing and encoding. More parsing support for indexed loads. Fix pre-indexed with writeback parsing for register offsets and handle basic post-indexed offsets. llvm-svn: 136982
2011-08-05 23:28:30 +02:00
def PostIdxRegShiftedAsmOperand : AsmOperandClass {
let Name = "PostIdxRegShifted";
let ParserMethod = "parsePostIdxReg";
}
[ARM] Mark a bunch of .td Operands with type _MEMORY. This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
2015-04-07 22:31:16 +02:00
def am2offset_reg : MemOperand,
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
2011-07-26 22:54:26 +02:00
ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
fix a long standing wart: all the ComplexPattern's were being passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. llvm-svn: 114471
2010-09-21 22:31:19 +02:00
[], [SDNPWantRoot]> {
More trivial cleanup. No need to define the EncoderMethod property type. Can just assign to it. llvm-svn: 121523
2010-12-10 21:53:44 +01:00
let EncoderMethod = "getAddrMode2OffsetOpValue";
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
let PrintMethod = "printAddrMode2OffsetOperand";
ARM indexed load assembly parsing and encoding. More parsing support for indexed loads. Fix pre-indexed with writeback parsing for register offsets and handle basic post-indexed offsets. llvm-svn: 136982
2011-08-05 23:28:30 +02:00
// When using this for assembly, it's always as a post-index offset.
let ParserMatchClass = PostIdxRegShiftedAsmOperand;
Use correct register class for am2offset register operands. This pacifies machine verifier llvm-svn: 148782
2012-01-24 05:58:56 +01:00
let MIOperandInfo = (ops GPRnopc, i32imm);
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
}
partial implementation of the ARM Addressing Mode 1 llvm-svn: 30252
2006-09-11 19:25:40 +02:00
ARM assembly parsing and encoding for LDR instructions. Enhance support for LDR instruction assembly parsing for post-indexed addressing with immediate values. Add tests. llvm-svn: 136940
2011-08-05 01:01:30 +02:00
// FIXME: am2offset_imm should only need the immediate, not the GPR. Having
// the GPR is purely vestigal at this point.
def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
[ARM] Mark a bunch of .td Operands with type _MEMORY. This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
2015-04-07 22:31:16 +02:00
def am2offset_imm : MemOperand,
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
2011-07-26 22:54:26 +02:00
ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
[], [SDNPWantRoot]> {
let EncoderMethod = "getAddrMode2OffsetOpValue";
let PrintMethod = "printAddrMode2OffsetOperand";
ARM assembly parsing and encoding for LDR instructions. Enhance support for LDR instruction assembly parsing for post-indexed addressing with immediate values. Add tests. llvm-svn: 136940
2011-08-05 01:01:30 +02:00
let ParserMatchClass = AM2OffsetImmAsmOperand;
Use correct register class for am2offset register operands. This pacifies machine verifier llvm-svn: 148782
2012-01-24 05:58:56 +01:00
let MIOperandInfo = (ops GPRnopc, i32imm);
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
2011-07-26 22:54:26 +02:00
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// addrmode3 := reg +/- reg
// addrmode3 := reg +/- imm8
//
ARM LDRD(immediate) assembly parsing and encoding support. llvm-svn: 137244
2011-08-10 22:29:19 +02:00
// FIXME: split into imm vs. reg versions.
def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
[ARM] Mark a bunch of .td Operands with type _MEMORY. This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
2015-04-07 22:31:16 +02:00
class AddrMode3 : MemOperand,
ARM: Correct printing of pre-indexed operands. According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
2013-04-12 20:47:25 +02:00
ComplexPattern<i32, 3, "SelectAddrMode3", []> {
add fields to the .td files unconditionally, simplifying tblgen a bit. Switch the ARM backend to use 'let' instead of 'set' with this change. llvm-svn: 119120
2010-11-15 06:19:05 +01:00
let EncoderMethod = "getAddrMode3OpValue";
ARM LDRD(immediate) assembly parsing and encoding support. llvm-svn: 137244
2011-08-10 22:29:19 +02:00
let ParserMatchClass = AddrMode3AsmOperand;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
}
initial implementation of addressing mode 2 TODO: fix lea_addri llvm-svn: 31552
2006-11-08 18:07:32 +01:00
ARM: Correct printing of pre-indexed operands. According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
2013-04-12 20:47:25 +02:00
def addrmode3 : AddrMode3
{
let PrintMethod = "printAddrMode3Operand<false>";
}
def addrmode3_pre : AddrMode3
{
let PrintMethod = "printAddrMode3Operand<true>";
}
ARM LDRD(immediate) assembly parsing and encoding support. llvm-svn: 137244
2011-08-10 22:29:19 +02:00
// FIXME: split into imm vs. reg versions.
// FIXME: parser method to handle +/- register.
ARM LDRD(register) assembly parsing and encoding. Add support for literal encoding of #-0 along the way. llvm-svn: 137254
2011-08-10 23:56:18 +02:00
def AM3OffsetAsmOperand : AsmOperandClass {
let Name = "AM3Offset";
let ParserMethod = "parseAM3Offset";
}
[ARM] Mark a bunch of .td Operands with type _MEMORY. This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
2015-04-07 22:31:16 +02:00
def am3offset : MemOperand,
fix a long standing wart: all the ComplexPattern's were being passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. llvm-svn: 114471
2010-09-21 22:31:19 +02:00
ComplexPattern<i32, 2, "SelectAddrMode3Offset",
[], [SDNPWantRoot]> {
add fields to the .td files unconditionally, simplifying tblgen a bit. Switch the ARM backend to use 'let' instead of 'set' with this change. llvm-svn: 119120
2010-11-15 06:19:05 +01:00
let EncoderMethod = "getAddrMode3OffsetOpValue";
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
let PrintMethod = "printAddrMode3OffsetOperand";
ARM LDRD(immediate) assembly parsing and encoding support. llvm-svn: 137244
2011-08-10 22:29:19 +02:00
let ParserMatchClass = AM3OffsetAsmOperand;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
let MIOperandInfo = (ops GPR, i32imm);
}
Break ARM addrmode4 (load/store multiple base address) into its constituent parts. Represent the operation mode as an optional operand instead. rdar://8614429 llvm-svn: 118137
2010-11-03 02:01:43 +01:00
// ldstm_mode := {ia, ib, da, db}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
//
Break ARM addrmode4 (load/store multiple base address) into its constituent parts. Represent the operation mode as an optional operand instead. rdar://8614429 llvm-svn: 118137
2010-11-03 02:01:43 +01:00
def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
add fields to the .td files unconditionally, simplifying tblgen a bit. Switch the ARM backend to use 'let' instead of 'set' with this change. llvm-svn: 119120
2010-11-15 06:19:05 +01:00
let EncoderMethod = "getLdStmModeOpValue";
Break ARM addrmode4 (load/store multiple base address) into its constituent parts. Represent the operation mode as an optional operand instead. rdar://8614429 llvm-svn: 118137
2010-11-03 02:01:43 +01:00
let PrintMethod = "printLdStmModeOperand";
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
}
// addrmode5 := reg +/- imm8*4
//
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
[ARM] Mark a bunch of .td Operands with type _MEMORY. This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
2015-04-07 22:31:16 +02:00
class AddrMode5 : MemOperand,
ARM: Correct printing of pre-indexed operands. According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
2013-04-12 20:47:25 +02:00
ComplexPattern<i32, 2, "SelectAddrMode5", []> {
add fields to the .td files unconditionally, simplifying tblgen a bit. Switch the ARM backend to use 'let' instead of 'set' with this change. llvm-svn: 119120
2010-11-15 06:19:05 +01:00
let EncoderMethod = "getAddrMode5OpValue";
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeAddrMode5Operand";
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
let ParserMatchClass = AddrMode5AsmOperand;
let MIOperandInfo = (ops GPR:$base, i32imm);
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
}
ARM: Correct printing of pre-indexed operands. According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
2013-04-12 20:47:25 +02:00
def addrmode5 : AddrMode5 {
let PrintMethod = "printAddrMode5Operand<false>";
}
def addrmode5_pre : AddrMode5 {
let PrintMethod = "printAddrMode5Operand<true>";
}
[ARM] Add ARMv8.2-A FP16 scalar instructions This was originally committed as r255762, but reverted as it broke windows bots. Re-commitiing the exact same patch, as the underlying cause was fixed by r258677. ARMv8.2-A adds 16-bit floating point versions of all existing VFP floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. The assembly for these instructions uses S registers (AArch32 does not have H registers), but the instructions have ".f16" type specifiers rather than ".f32" or ".f64". The top 16 bits of each source register are ignored, and the top 16 bits of the destination register are set to zero. These instructions are mostly the same as the 32- and 64-bit versions, but they use coprocessor 9 rather than 10 and 11. Two new instructions, VMOVX and VINS, have been added to allow packing and extracting two 16-bit floats stored in the top and bottom halves of an S register. New fixup kinds have been added for the PC-relative load and store instructions, but no ELF relocations have been added as they have a range of 512 bytes. Differential Revision: http://reviews.llvm.org/D15038 llvm-svn: 258678
2016-01-25 11:26:26 +01:00
// addrmode5fp16 := reg +/- imm8*2
//
def AddrMode5FP16AsmOperand : AsmOperandClass { let Name = "AddrMode5FP16"; }
class AddrMode5FP16 : Operand<i32>,
ComplexPattern<i32, 2, "SelectAddrMode5FP16", []> {
let EncoderMethod = "getAddrMode5FP16OpValue";
let DecoderMethod = "DecodeAddrMode5FP16Operand";
let ParserMatchClass = AddrMode5FP16AsmOperand;
let MIOperandInfo = (ops GPR:$base, i32imm);
}
def addrmode5fp16 : AddrMode5FP16 {
let PrintMethod = "printAddrMode5FP16Operand<false>";
}
Fix a comment: addrmode6 no longer includes the optional writeback flag. llvm-svn: 125011
2011-02-07 18:43:09 +01:00
// addrmode6 := reg with optional alignment
Add a new addressing mode for NEON load/store instructions. llvm-svn: 74658
2009-07-02 01:16:05 +02:00
//
ARM parse alignment specifier for NEON load/store instructions. llvm-svn: 141682
2011-10-11 19:29:55 +02:00
def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
[ARM] Mark a bunch of .td Operands with type _MEMORY. This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
2015-04-07 22:31:16 +02:00
def addrmode6 : MemOperand,
Add support for alignment operands on VLD1-lane instructions. This is another part of the fix for Radar 8599955. llvm-svn: 117976
2010-11-02 00:40:51 +01:00
ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
Add a new addressing mode for NEON load/store instructions. llvm-svn: 74658
2009-07-02 01:16:05 +02:00
let PrintMethod = "printAddrMode6Operand";
Add a name to sub-operand for clarity. llvm-svn: 141590
2011-10-11 00:55:05 +02:00
let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
add fields to the .td files unconditionally, simplifying tblgen a bit. Switch the ARM backend to use 'let' instead of 'set' with this change. llvm-svn: 119120
2010-11-15 06:19:05 +01:00
let EncoderMethod = "getAddrMode6AddressOpValue";
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeAddrMode6Operand";
ARM parse alignment specifier for NEON load/store instructions. llvm-svn: 141682
2011-10-11 19:29:55 +02:00
let ParserMatchClass = AddrMode6AsmOperand;
Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6") with changes to add a separate optional register update argument. Change all the NEON instructions with address register writeback to use it. llvm-svn: 99095
2010-03-20 23:13:40 +01:00
}
[ARM] Mark a bunch of .td Operands with type _MEMORY. This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
2015-04-07 22:31:16 +02:00
def am6offset : MemOperand,
Add patterns to use post-increment addressing for Neon VST1-lane instructions. llvm-svn: 126477
2011-02-25 07:42:42 +01:00
ComplexPattern<i32, 1, "SelectAddrMode6Offset",
[], [SDNPWantRoot]> {
Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6") with changes to add a separate optional register update argument. Change all the NEON instructions with address register writeback to use it. llvm-svn: 99095
2010-03-20 23:13:40 +01:00
let PrintMethod = "printAddrMode6OffsetOperand";
let MIOperandInfo = (ops GPR);
add fields to the .td files unconditionally, simplifying tblgen a bit. Switch the ARM backend to use 'let' instead of 'set' with this change. llvm-svn: 119120
2010-11-15 06:19:05 +01:00
let EncoderMethod = "getAddrMode6OffsetOpValue";
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeGPRRegisterClass";
Add a new addressing mode for NEON load/store instructions. llvm-svn: 74658
2009-07-02 01:16:05 +02:00
}
Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32 llvm-svn: 131085
2011-05-09 19:47:27 +02:00
// Special version of addrmode6 to handle alignment encoding for VST1/VLD1
// (single element from one lane) for size 32.
[ARM] Mark a bunch of .td Operands with type _MEMORY. This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
2015-04-07 22:31:16 +02:00
def addrmode6oneL32 : MemOperand,
Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32 llvm-svn: 131085
2011-05-09 19:47:27 +02:00
ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
let PrintMethod = "printAddrMode6Operand";
let MIOperandInfo = (ops GPR:$addr, i32imm);
let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
}
For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 llvm-svn: 205986
2014-04-10 22:18:58 +02:00
// Base class for addrmode6 with specific alignment restrictions.
[ARM] Mark a bunch of .td Operands with type _MEMORY. This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
2015-04-07 22:31:16 +02:00
class AddrMode6Align : MemOperand,
For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 llvm-svn: 205986
2014-04-10 22:18:58 +02:00
ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
let PrintMethod = "printAddrMode6Operand";
let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
let EncoderMethod = "getAddrMode6AddressOpValue";
let DecoderMethod = "DecodeAddrMode6Operand";
}
// Special version of addrmode6 to handle no allowed alignment encoding for
// VLD/VST instructions and checking the alignment is not specified.
def AddrMode6AlignNoneAsmOperand : AsmOperandClass {
let Name = "AlignedMemoryNone";
[ARM] Use table-gen'd assembly operand diags in ARM asm parser This switches the ARM AsmParser to use assembly operand diagnostics from tablegen, rather than a switch statement on the ARMMatchResultTy. It moves the existing diagnostic strings to tablegen, but adds no new ones, so this is NFC except for one diagnostic string that had an off-by-1 error in the hand-written switch statement. Differential revision: https://reviews.llvm.org/D31607 llvm-svn: 314804
2017-10-03 16:38:52 +02:00
let DiagnosticString = "alignment must be omitted";
For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 llvm-svn: 205986
2014-04-10 22:18:58 +02:00
}
def addrmode6alignNone : AddrMode6Align {
// The alignment specifier can only be omitted.
let ParserMatchClass = AddrMode6AlignNoneAsmOperand;
}
// Special version of addrmode6 to handle 16-bit alignment encoding for
// VLD/VST instructions and checking the alignment value.
def AddrMode6Align16AsmOperand : AsmOperandClass {
let Name = "AlignedMemory16";
[ARM] Use table-gen'd assembly operand diags in ARM asm parser This switches the ARM AsmParser to use assembly operand diagnostics from tablegen, rather than a switch statement on the ARMMatchResultTy. It moves the existing diagnostic strings to tablegen, but adds no new ones, so this is NFC except for one diagnostic string that had an off-by-1 error in the hand-written switch statement. Differential revision: https://reviews.llvm.org/D31607 llvm-svn: 314804
2017-10-03 16:38:52 +02:00
let DiagnosticString = "alignment must be 16 or omitted";
For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 llvm-svn: 205986
2014-04-10 22:18:58 +02:00
}
def addrmode6align16 : AddrMode6Align {
// The alignment specifier can only be 16 or omitted.
let ParserMatchClass = AddrMode6Align16AsmOperand;
}
// Special version of addrmode6 to handle 32-bit alignment encoding for
// VLD/VST instructions and checking the alignment value.
def AddrMode6Align32AsmOperand : AsmOperandClass {
let Name = "AlignedMemory32";
[ARM] Use table-gen'd assembly operand diags in ARM asm parser This switches the ARM AsmParser to use assembly operand diagnostics from tablegen, rather than a switch statement on the ARMMatchResultTy. It moves the existing diagnostic strings to tablegen, but adds no new ones, so this is NFC except for one diagnostic string that had an off-by-1 error in the hand-written switch statement. Differential revision: https://reviews.llvm.org/D31607 llvm-svn: 314804
2017-10-03 16:38:52 +02:00
let DiagnosticString = "alignment must be 32 or omitted";
For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 llvm-svn: 205986
2014-04-10 22:18:58 +02:00
}
def addrmode6align32 : AddrMode6Align {
// The alignment specifier can only be 32 or omitted.
let ParserMatchClass = AddrMode6Align32AsmOperand;
}
// Special version of addrmode6 to handle 64-bit alignment encoding for
// VLD/VST instructions and checking the alignment value.
def AddrMode6Align64AsmOperand : AsmOperandClass {
let Name = "AlignedMemory64";
[ARM] Use table-gen'd assembly operand diags in ARM asm parser This switches the ARM AsmParser to use assembly operand diagnostics from tablegen, rather than a switch statement on the ARMMatchResultTy. It moves the existing diagnostic strings to tablegen, but adds no new ones, so this is NFC except for one diagnostic string that had an off-by-1 error in the hand-written switch statement. Differential revision: https://reviews.llvm.org/D31607 llvm-svn: 314804
2017-10-03 16:38:52 +02:00
let DiagnosticString = "alignment must be 64 or omitted";
For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 llvm-svn: 205986
2014-04-10 22:18:58 +02:00
}
def addrmode6align64 : AddrMode6Align {
// The alignment specifier can only be 64 or omitted.
let ParserMatchClass = AddrMode6Align64AsmOperand;
}
// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
// for VLD/VST instructions and checking the alignment value.
def AddrMode6Align64or128AsmOperand : AsmOperandClass {
let Name = "AlignedMemory64or128";
[ARM] Use table-gen'd assembly operand diags in ARM asm parser This switches the ARM AsmParser to use assembly operand diagnostics from tablegen, rather than a switch statement on the ARMMatchResultTy. It moves the existing diagnostic strings to tablegen, but adds no new ones, so this is NFC except for one diagnostic string that had an off-by-1 error in the hand-written switch statement. Differential revision: https://reviews.llvm.org/D31607 llvm-svn: 314804
2017-10-03 16:38:52 +02:00
let DiagnosticString = "alignment must be 64, 128 or omitted";
For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 llvm-svn: 205986
2014-04-10 22:18:58 +02:00
}
def addrmode6align64or128 : AddrMode6Align {
// The alignment specifier can only be 64, 128 or omitted.
let ParserMatchClass = AddrMode6Align64or128AsmOperand;
}
// Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
// encoding for VLD/VST instructions and checking the alignment value.
def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {
let Name = "AlignedMemory64or128or256";
[ARM] Use table-gen'd assembly operand diags in ARM asm parser This switches the ARM AsmParser to use assembly operand diagnostics from tablegen, rather than a switch statement on the ARMMatchResultTy. It moves the existing diagnostic strings to tablegen, but adds no new ones, so this is NFC except for one diagnostic string that had an off-by-1 error in the hand-written switch statement. Differential revision: https://reviews.llvm.org/D31607 llvm-svn: 314804
2017-10-03 16:38:52 +02:00
let DiagnosticString = "alignment must be 64, 128, 256 or omitted";
For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 llvm-svn: 205986
2014-04-10 22:18:58 +02:00
}
def addrmode6align64or128or256 : AddrMode6Align {
// The alignment specifier can only be 64, 128, 256 or omitted.
let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
}
Fix the encoding of VLD4-dup alignment. The only reasonable way I could find to do this is to provide an alternate version of the addrmode6 operand with a different encoding function. Use it for all the VLD-dup instructions for the sake of consistency. llvm-svn: 120358
2010-11-30 01:00:42 +01:00
// Special version of addrmode6 to handle alignment encoding for VLD-dup
// instructions, specifically VLD4-dup.
[ARM] Mark a bunch of .td Operands with type _MEMORY. This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
2015-04-07 22:31:16 +02:00
def addrmode6dup : MemOperand,
Fix the encoding of VLD4-dup alignment. The only reasonable way I could find to do this is to provide an alternate version of the addrmode6 operand with a different encoding function. Use it for all the VLD-dup instructions for the sake of consistency. llvm-svn: 120358
2010-11-30 01:00:42 +01:00
ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
let PrintMethod = "printAddrMode6Operand";
let MIOperandInfo = (ops GPR:$addr, i32imm);
let EncoderMethod = "getAddrMode6DupAddressOpValue";
ARM parsing aliases for VLD1 single register all lanes. llvm-svn: 145464
2011-11-30 02:09:44 +01:00
// FIXME: This is close, but not quite right. The alignment specifier is
// different.
let ParserMatchClass = AddrMode6AsmOperand;
Fix the encoding of VLD4-dup alignment. The only reasonable way I could find to do this is to provide an alternate version of the addrmode6 operand with a different encoding function. Use it for all the VLD-dup instructions for the sake of consistency. llvm-svn: 120358
2010-11-30 01:00:42 +01:00
}
For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 llvm-svn: 205986
2014-04-10 22:18:58 +02:00
// Base class for addrmode6dup with specific alignment restrictions.
[ARM] Mark a bunch of .td Operands with type _MEMORY. This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
2015-04-07 22:31:16 +02:00
class AddrMode6DupAlign : MemOperand,
For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 llvm-svn: 205986
2014-04-10 22:18:58 +02:00
ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
let PrintMethod = "printAddrMode6Operand";
let MIOperandInfo = (ops GPR:$addr, i32imm);
let EncoderMethod = "getAddrMode6DupAddressOpValue";
}
// Special version of addrmode6 to handle no allowed alignment encoding for
// VLD-dup instruction and checking the alignment is not specified.
def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {
let Name = "DupAlignedMemoryNone";
[ARM] Use table-gen'd assembly operand diags in ARM asm parser This switches the ARM AsmParser to use assembly operand diagnostics from tablegen, rather than a switch statement on the ARMMatchResultTy. It moves the existing diagnostic strings to tablegen, but adds no new ones, so this is NFC except for one diagnostic string that had an off-by-1 error in the hand-written switch statement. Differential revision: https://reviews.llvm.org/D31607 llvm-svn: 314804
2017-10-03 16:38:52 +02:00
let DiagnosticString = "alignment must be omitted";
For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 llvm-svn: 205986
2014-04-10 22:18:58 +02:00
}
def addrmode6dupalignNone : AddrMode6DupAlign {
// The alignment specifier can only be omitted.
let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
}
// Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
// instruction and checking the alignment value.
def AddrMode6dupAlign16AsmOperand : AsmOperandClass {
let Name = "DupAlignedMemory16";
[ARM] Use table-gen'd assembly operand diags in ARM asm parser This switches the ARM AsmParser to use assembly operand diagnostics from tablegen, rather than a switch statement on the ARMMatchResultTy. It moves the existing diagnostic strings to tablegen, but adds no new ones, so this is NFC except for one diagnostic string that had an off-by-1 error in the hand-written switch statement. Differential revision: https://reviews.llvm.org/D31607 llvm-svn: 314804
2017-10-03 16:38:52 +02:00
let DiagnosticString = "alignment must be 16 or omitted";
For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 llvm-svn: 205986
2014-04-10 22:18:58 +02:00
}
def addrmode6dupalign16 : AddrMode6DupAlign {
// The alignment specifier can only be 16 or omitted.
let ParserMatchClass = AddrMode6dupAlign16AsmOperand;
}
// Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
// instruction and checking the alignment value.
def AddrMode6dupAlign32AsmOperand : AsmOperandClass {
let Name = "DupAlignedMemory32";
[ARM] Use table-gen'd assembly operand diags in ARM asm parser This switches the ARM AsmParser to use assembly operand diagnostics from tablegen, rather than a switch statement on the ARMMatchResultTy. It moves the existing diagnostic strings to tablegen, but adds no new ones, so this is NFC except for one diagnostic string that had an off-by-1 error in the hand-written switch statement. Differential revision: https://reviews.llvm.org/D31607 llvm-svn: 314804
2017-10-03 16:38:52 +02:00
let DiagnosticString = "alignment must be 32 or omitted";
For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 llvm-svn: 205986
2014-04-10 22:18:58 +02:00
}
def addrmode6dupalign32 : AddrMode6DupAlign {
// The alignment specifier can only be 32 or omitted.
let ParserMatchClass = AddrMode6dupAlign32AsmOperand;
}
// Special version of addrmode6 to handle 64-bit alignment encoding for VLD
// instructions and checking the alignment value.
def AddrMode6dupAlign64AsmOperand : AsmOperandClass {
let Name = "DupAlignedMemory64";
[ARM] Use table-gen'd assembly operand diags in ARM asm parser This switches the ARM AsmParser to use assembly operand diagnostics from tablegen, rather than a switch statement on the ARMMatchResultTy. It moves the existing diagnostic strings to tablegen, but adds no new ones, so this is NFC except for one diagnostic string that had an off-by-1 error in the hand-written switch statement. Differential revision: https://reviews.llvm.org/D31607 llvm-svn: 314804
2017-10-03 16:38:52 +02:00
let DiagnosticString = "alignment must be 64 or omitted";
For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 llvm-svn: 205986
2014-04-10 22:18:58 +02:00
}
def addrmode6dupalign64 : AddrMode6DupAlign {
// The alignment specifier can only be 64 or omitted.
let ParserMatchClass = AddrMode6dupAlign64AsmOperand;
}
// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
// for VLD instructions and checking the alignment value.
def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {
let Name = "DupAlignedMemory64or128";
[ARM] Use table-gen'd assembly operand diags in ARM asm parser This switches the ARM AsmParser to use assembly operand diagnostics from tablegen, rather than a switch statement on the ARMMatchResultTy. It moves the existing diagnostic strings to tablegen, but adds no new ones, so this is NFC except for one diagnostic string that had an off-by-1 error in the hand-written switch statement. Differential revision: https://reviews.llvm.org/D31607 llvm-svn: 314804
2017-10-03 16:38:52 +02:00
let DiagnosticString = "alignment must be 64, 128 or omitted";
For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 llvm-svn: 205986
2014-04-10 22:18:58 +02:00
}
def addrmode6dupalign64or128 : AddrMode6DupAlign {
// The alignment specifier can only be 64, 128 or omitted.
let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// addrmodepc := pc + reg
//
[ARM] Mark a bunch of .td Operands with type _MEMORY. This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
2015-04-07 22:31:16 +02:00
def addrmodepc : MemOperand,
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
ComplexPattern<i32, 2, "SelectAddrModePC", []> {
let PrintMethod = "printAddrModePCOperand";
let MIOperandInfo = (ops GPR, i32imm);
}
initial implementation of addressing mode 5 llvm-svn: 31002
2006-10-17 20:04:53 +02:00
ARM: rename addrmode7 to addr_offset_none. Use a more descriptive name so the code is more self-documenting. llvm-svn: 136704
2011-08-02 20:07:32 +02:00
// addr_offset_none := reg
Add asm parsing support w/ testcases for strex/ldrex family of instructions llvm-svn: 128236
2011-03-24 22:04:58 +01:00
//
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
[ARM] Mark a bunch of .td Operands with type _MEMORY. This shouldn't affect anything in-tree, as the OperandType users are mostly smart disassemblers and such; more information is helpful there. However, on the flip side, that + the fact that this is just hinting at the meaning of operands makes this not really test-worthy or testable. Differential Revision: http://reviews.llvm.org/D8620 llvm-svn: 234350
2015-04-07 22:31:16 +02:00
def addr_offset_none : MemOperand,
ARM refactor indexed store instructions. Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
2011-08-05 22:35:44 +02:00
ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
Add asm parsing support w/ testcases for strex/ldrex family of instructions llvm-svn: 128236
2011-03-24 22:04:58 +01:00
let PrintMethod = "printAddrMode7Operand";
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeAddrMode7Operand";
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
let ParserMatchClass = MemNoOffsetAsmOperand;
let MIOperandInfo = (ops GPR:$base);
Add asm parsing support w/ testcases for strex/ldrex family of instructions llvm-svn: 128236
2011-03-24 22:04:58 +01:00
}
[ARM] Add MVE vector load/store instructions. This adds the rest of the vector memory access instructions. It includes contiguous loads/stores, with an ordinary addressing mode such as [r0,#offset] (plus writeback variants); gather loads and scatter stores with a scalar base address register and a vector of offsets from it (written [r0,q1] or similar); and gather/scatters with a vector of base addresses (written [q0,#offset], again with writeback). Additionally, some of the loads can widen each loaded value into a larger vector lane, and the corresponding stores narrow them again. To implement these, we also have to add the addressing modes they need. Also, in AsmParser, the `isMem` query function now has subqueries `isGPRMem` and `isMVEMem`, according to which kind of base register is used by a given memory access operand. I've also had to add an extra check in `checkTargetMatchPredicate` in the AsmParser, without which our last-minute check of `rGPR` register operands against SP and PC was failing an assertion because Tablegen had inserted an immediate 0 in place of one of a pair of tied register operands. (This matches the way the corresponding check for `MCK_rGPR` in `validateTargetOperandClass` is guarded.) Apparently the MVE load instructions were the first to have ever triggered this assertion, but I think only because they were the first to have a combination of the usual Arm pre/post writeback system and the `rGPR` class in particular. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62680 llvm-svn: 364291
2019-06-25 13:24:18 +02:00
// t_addr_offset_none := reg [r0-r7]
def MemNoOffsetTAsmOperand : AsmOperandClass { let Name = "MemNoOffsetT"; }
def t_addr_offset_none : MemOperand {
let PrintMethod = "printAddrMode7Operand";
let DecoderMethod = "DecodetGPRRegisterClass";
let ParserMatchClass = MemNoOffsetTAsmOperand;
let MIOperandInfo = (ops tGPR:$base);
}
Rename ARM "lane_cst" operands to "nohash_imm" since they are used for several things other than Neon vector lane numbers. For inline assembly operands with a "c" print code, check that they really are immediates. llvm-svn: 79676
2009-08-21 23:58:55 +02:00
def nohash_imm : Operand<i32> {
let PrintMethod = "printNoHashImmediate";
Use subclassing to print lane-like immediates (w/o hash) eliminating 'no_hash' modifier. Hopefully this will make Daniel happy :) llvm-svn: 78514
2009-08-09 01:10:41 +02:00
}
Remove the MCR asm parser hack and start using the custom target specific asm parsing of operands introduced in r125030. As a small note, besides using a more generic approach we can also have more descriptive output when debugging llvm-mc, example: mcr p7, #1, r5, c1, c1, #4 note: parsed instruction: ['mcr', <ARMCC::al>, <coprocessor number: 7>, 1, <register 73>, <coprocessor register: 1>, <coprocessor register: 1>, 4] llvm-svn: 125052
2011-02-07 22:41:25 +01:00
def CoprocNumAsmOperand : AsmOperandClass {
let Name = "CoprocNum";
Make assembly parser method names more consistent. llvm-svn: 135950
2011-07-25 22:14:50 +02:00
let ParserMethod = "parseCoprocNumOperand";
Remove the MCR asm parser hack and start using the custom target specific asm parsing of operands introduced in r125030. As a small note, besides using a more generic approach we can also have more descriptive output when debugging llvm-mc, example: mcr p7, #1, r5, c1, c1, #4 note: parsed instruction: ['mcr', <ARMCC::al>, <coprocessor number: 7>, 1, <register 73>, <coprocessor register: 1>, <coprocessor register: 1>, 4] llvm-svn: 125052
2011-02-07 22:41:25 +01:00
}
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
2011-01-13 22:46:02 +01:00
def p_imm : Operand<i32> {
let PrintMethod = "printPImmediate";
Remove the MCR asm parser hack and start using the custom target specific asm parsing of operands introduced in r125030. As a small note, besides using a more generic approach we can also have more descriptive output when debugging llvm-mc, example: mcr p7, #1, r5, c1, c1, #4 note: parsed instruction: ['mcr', <ARMCC::al>, <coprocessor number: 7>, 1, <register 73>, <coprocessor register: 1>, <coprocessor register: 1>, 4] llvm-svn: 125052
2011-02-07 22:41:25 +01:00
let ParserMatchClass = CoprocNumAsmOperand;
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeCoprocessor";
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
2011-01-13 22:46:02 +01:00
}
Tidy up formatting. Remove some inititalizers that are the same as the default, move defs next to their (singular) uses and generally simplify some formatting of asm operand definitions. llvm-svn: 135946
2011-07-25 22:06:30 +02:00
def CoprocRegAsmOperand : AsmOperandClass {
let Name = "CoprocReg";
Make assembly parser method names more consistent. llvm-svn: 135950
2011-07-25 22:14:50 +02:00
let ParserMethod = "parseCoprocRegOperand";
Tidy up formatting. Remove some inititalizers that are the same as the default, move defs next to their (singular) uses and generally simplify some formatting of asm operand definitions. llvm-svn: 135946
2011-07-25 22:06:30 +02:00
}
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
2011-01-13 22:46:02 +01:00
def c_imm : Operand<i32> {
let PrintMethod = "printCImmediate";
Remove the MCR asm parser hack and start using the custom target specific asm parsing of operands introduced in r125030. As a small note, besides using a more generic approach we can also have more descriptive output when debugging llvm-mc, example: mcr p7, #1, r5, c1, c1, #4 note: parsed instruction: ['mcr', <ARMCC::al>, <coprocessor number: 7>, 1, <register 73>, <coprocessor register: 1>, <coprocessor register: 1>, 4] llvm-svn: 125052
2011-02-07 22:41:25 +01:00
let ParserMatchClass = CoprocRegAsmOperand;
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
2011-01-13 22:46:02 +01:00
}
ARM parsing and encoding for the <option> form of LDC/STC instructions. llvm-svn: 141786
2011-10-12 19:34:41 +02:00
def CoprocOptionAsmOperand : AsmOperandClass {
let Name = "CoprocOption";
let ParserMethod = "parseCoprocOptionOperand";
}
def coproc_option_imm : Operand<i32> {
let PrintMethod = "printCoprocOptionImm";
let ParserMatchClass = CoprocOptionAsmOperand;
}
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
2011-01-13 22:46:02 +01:00
Initial JIT support for ARM by Raul Fernandes Herbster. llvm-svn: 40887
2007-08-07 03:37:15 +02:00
//===----------------------------------------------------------------------===//
Refactor ARM instruction format definitions into a separate file. No functionality changes. llvm-svn: 55518
2008-08-29 01:39:26 +02:00
include "ARMInstrFormats.td"
Initial JIT support for ARM by Raul Fernandes Herbster. llvm-svn: 40887
2007-08-07 03:37:15 +02:00
added a skeleton of the ARM backend llvm-svn: 28301
2006-05-15 00:18:28 +02:00
//===----------------------------------------------------------------------===//
Refactor ARM instruction format definitions into a separate file. No functionality changes. llvm-svn: 55518
2008-08-29 01:39:26 +02:00
// Multiclass helpers...
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
//
[ARM] Cleanup so_imm* tblgen defintions No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
2015-01-06 16:55:09 +01:00
/// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
/// binop that produces a value.
ARM let TableGen handle a few two-operand aliases. No need for these explicit aliases anymore. Nuke 'em. llvm-svn: 155173
2012-04-20 01:59:26 +02:00
let TwoOperandAliasConstraint = "$Rn = $Rd" in
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub. llvm-svn: 115008
2010-09-29 02:27:46 +02:00
multiclass AsI1_bin_irs<bits<4> opcod, string opc,
InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
SDPatternOperator opnode, bit Commutable = 0> {
Make ARM add rN, sp, #imm instructions rematerializable. That's how the address of locals is calculated, so this should help relieve register pressure a bit. Recalculating the local address is almost always going to be better than spilling. llvm-svn: 112503
2010-08-30 21:49:58 +02:00
// The register-immediate version is re-materializable. This is useful
// in particular for taking the address of a local.
let isReMaterializable = 1 in {
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
Add encoding information for the remainder of the generic arithmetic ARM instructions. llvm-svn: 116313
2010-10-12 19:11:26 +02:00
iii, opc, "\t$Rd, $Rn, $imm",
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
[(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 15:07:05 +02:00
Sched<[WriteALU, ReadALU]> {
Add encoding information for the remainder of the generic arithmetic ARM instructions. llvm-svn: 116313
2010-10-12 19:11:26 +02:00
bits<4> Rd;
bits<4> Rn;
Move the ARM so_imm encoding into a custom operand encoder and remove the explicit handling of the instructions referencing it from the MC code emitter. llvm-svn: 116367
2010-10-13 01:18:08 +02:00
bits<12> imm;
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan. llvm-svn: 74972
2009-07-08 01:40:25 +02:00
let Inst{25} = 1;
Add encoding information for the remainder of the generic arithmetic ARM instructions. llvm-svn: 116313
2010-10-12 19:11:26 +02:00
let Inst{19-16} = Rn;
Sort bit assignments. Cosmetic change only. llvm-svn: 118029
2010-11-02 18:59:04 +01:00
let Inst{15-12} = Rd;
Move the ARM so_imm encoding into a custom operand encoder and remove the explicit handling of the instructions referencing it from the MC code emitter. llvm-svn: 116367
2010-10-13 01:18:08 +02:00
let Inst{11-0} = imm;
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan. llvm-svn: 74972
2009-07-08 01:40:25 +02:00
}
Make ARM add rN, sp, #imm instructions rematerializable. That's how the address of locals is calculated, so this should help relieve register pressure a bit. Recalculating the local address is almost always going to be better than spilling. llvm-svn: 112503
2010-08-30 21:49:58 +02:00
}
More binary encoding stuff, taking advantage of the new "by name" operand matching in tblgen to do the predicate operand. llvm-svn: 116213
2010-10-11 20:51:51 +02:00
def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
iir, opc, "\t$Rd, $Rn, $Rm",
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 15:07:05 +02:00
[(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
Sched<[WriteALU, ReadALU, ReadALU]> {
Implement a few more binary encoding bits. Still very early stage proof-of- concept level stuff at this point, but it is generally working for those instructions that know how to map the operands. This patch fills in the register operands for add/sub/or/etc instructions and adds the conditional execution predicate encoding. llvm-svn: 116112
2010-10-08 23:45:55 +02:00
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan. llvm-svn: 74972
2009-07-08 01:40:25 +02:00
let Inst{25} = 0;
Mark a bunch of instructions commutable. llvm-svn: 74237
2009-06-26 02:19:44 +02:00
let isCommutable = Commutable;
Implement a few more binary encoding bits. Still very early stage proof-of- concept level stuff at this point, but it is generally working for those instructions that know how to map the operands. This patch fills in the register operands for add/sub/or/etc instructions and adds the conditional execution predicate encoding. llvm-svn: 116112
2010-10-08 23:45:55 +02:00
let Inst{19-16} = Rn;
Sort bit assignments. Cosmetic change only. llvm-svn: 118029
2010-11-02 18:59:04 +01:00
let Inst{15-12} = Rd;
let Inst{11-4} = 0b00000000;
let Inst{3-0} = Rm;
Mark a bunch of instructions commutable. llvm-svn: 74237
2009-06-26 02:19:44 +02:00
}
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
def rsi : AsI1<opcod, (outs GPR:$Rd),
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. llvm-svn: 135722
2011-07-22 01:38:37 +02:00
(ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
iis, opc, "\t$Rd, $Rn, $shift",
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 15:07:05 +02:00
[(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
Sched<[WriteALUsi, ReadALU]> {
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
bits<4> Rd;
bits<4> Rn;
bits<12> shift;
let Inst{25} = 0;
let Inst{19-16} = Rn;
let Inst{15-12} = Rd;
let Inst{11-5} = shift{11-5};
let Inst{4} = 0;
let Inst{3-0} = shift{3-0};
}
def rsr : AsI1<opcod, (outs GPR:$Rd),
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. llvm-svn: 135722
2011-07-22 01:38:37 +02:00
(ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
Add the rest of the ARM so_reg encoding options (register shifted register) and move to a custom operand encoder. Remove the last of the special handling stuff from ARMMCCodeEmitter::EncodeInstruction. llvm-svn: 116377
2010-10-13 01:53:58 +02:00
iis, opc, "\t$Rd, $Rn, $shift",
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 15:07:05 +02:00
[(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
Sched<[WriteALUsr, ReadALUsr]> {
MC machine encoding for simple aritmetic instructions that use a shifted register operand. llvm-svn: 116259
2010-10-12 01:16:21 +02:00
bits<4> Rd;
bits<4> Rn;
Add the rest of the ARM so_reg encoding options (register shifted register) and move to a custom operand encoder. Remove the last of the special handling stuff from ARMMCCodeEmitter::EncodeInstruction. llvm-svn: 116377
2010-10-13 01:53:58 +02:00
bits<12> shift;
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan. llvm-svn: 74972
2009-07-08 01:40:25 +02:00
let Inst{25} = 0;
MC machine encoding for simple aritmetic instructions that use a shifted register operand. llvm-svn: 116259
2010-10-12 01:16:21 +02:00
let Inst{19-16} = Rn;
Sort bit assignments. Cosmetic change only. llvm-svn: 118029
2010-11-02 18:59:04 +01:00
let Inst{15-12} = Rd;
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
let Inst{11-8} = shift{11-8};
let Inst{7} = 0;
let Inst{6-5} = shift{6-5};
let Inst{4} = 1;
let Inst{3-0} = shift{3-0};
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan. llvm-svn: 74972
2009-07-08 01:40:25 +02:00
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
}
define the IntBinOp class and use it to implement the multiply instructions llvm-svn: 30978
2006-10-16 19:57:20 +02:00
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
/// reversed. The 'rr' form is only defined for the disassembler; for codegen
/// it is equivalent to the AsI1_bin_irs counterpart.
ARM let TableGen handle a few two-operand aliases. No need for these explicit aliases anymore. Nuke 'em. llvm-svn: 155173
2012-04-20 01:59:26 +02:00
let TwoOperandAliasConstraint = "$Rn = $Rd" in
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
SDNode opnode, bit Commutable = 0> {
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
// The register-immediate version is re-materializable. This is useful
// in particular for taking the address of a local.
let isReMaterializable = 1 in {
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
iii, opc, "\t$Rd, $Rn, $imm",
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
[(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 15:07:05 +02:00
Sched<[WriteALU, ReadALU]> {
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
bits<4> Rd;
bits<4> Rn;
bits<12> imm;
let Inst{25} = 1;
let Inst{19-16} = Rn;
let Inst{15-12} = Rd;
let Inst{11-0} = imm;
}
}
def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
iir, opc, "\t$Rd, $Rn, $Rm",
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 15:07:05 +02:00
[/* pattern left blank */]>,
Sched<[WriteALU, ReadALU, ReadALU]> {
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
let Inst{11-4} = 0b00000000;
let Inst{25} = 0;
let Inst{3-0} = Rm;
let Inst{15-12} = Rd;
let Inst{19-16} = Rn;
}
def rsi : AsI1<opcod, (outs GPR:$Rd),
(ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
iis, opc, "\t$Rd, $Rn, $shift",
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 15:07:05 +02:00
[(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
Sched<[WriteALUsi, ReadALU]> {
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
bits<4> Rd;
bits<4> Rn;
bits<12> shift;
let Inst{25} = 0;
let Inst{19-16} = Rn;
let Inst{15-12} = Rd;
let Inst{11-5} = shift{11-5};
let Inst{4} = 0;
let Inst{3-0} = shift{3-0};
}
def rsr : AsI1<opcod, (outs GPR:$Rd),
(ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
iis, opc, "\t$Rd, $Rn, $shift",
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 15:07:05 +02:00
[(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
Sched<[WriteALUsr, ReadALUsr]> {
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
bits<4> Rd;
bits<4> Rn;
bits<12> shift;
let Inst{25} = 0;
let Inst{19-16} = Rn;
let Inst{15-12} = Rd;
let Inst{11-8} = shift{11-8};
let Inst{7} = 0;
let Inst{6-5} = shift{6-5};
let Inst{4} = 1;
let Inst{3-0} = shift{3-0};
}
}
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
2011-10-18 21:18:52 +02:00
/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
Lower ARM adds/subs to add/sub after adding optional CPSR operand. This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. llvm-svn: 140228
2011-09-21 04:20:46 +02:00
///
/// These opcodes will be converted to the real non-S opcodes by
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
2011-10-18 21:18:52 +02:00
/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
let hasPostISelHook = 1, Defs = [CPSR] in {
multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
InstrItinClass iis, SDNode opnode,
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
2011-10-18 21:18:52 +02:00
bit Commutable = 0> {
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
2011-10-18 21:18:52 +02:00
4, iii,
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
[(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 15:07:05 +02:00
Sched<[WriteALU, ReadALU]>;
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
2011-10-18 21:18:52 +02:00
def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
4, iir,
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 15:07:05 +02:00
[(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
Sched<[WriteALU, ReadALU, ReadALU]> {
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
2011-10-18 21:18:52 +02:00
let isCommutable = Commutable;
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
}
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
2011-10-18 21:18:52 +02:00
def rsi : ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
4, iis,
[(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 15:07:05 +02:00
so_reg_imm:$shift))]>,
Sched<[WriteALUsi, ReadALU]>;
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
2011-10-18 21:18:52 +02:00
def rsr : ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
4, iis,
[(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 15:07:05 +02:00
so_reg_reg:$shift))]>,
Sched<[WriteALUSsr, ReadALUsr]>;
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
}
}
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
2011-10-18 21:18:52 +02:00
/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
/// operands are reversed.
let hasPostISelHook = 1, Defs = [CPSR] in {
multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
InstrItinClass iis, SDNode opnode,
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
2011-10-18 21:18:52 +02:00
bit Commutable = 0> {
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
2011-10-18 21:18:52 +02:00
4, iii,
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
[(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 15:07:05 +02:00
Sched<[WriteALU, ReadALU]>;
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
2011-10-18 21:18:52 +02:00
def rsi : ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
4, iis,
[(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 15:07:05 +02:00
GPR:$Rn))]>,
Sched<[WriteALUsi, ReadALU]>;
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
2011-10-18 21:18:52 +02:00
def rsr : ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
4, iis,
[(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
ARM Scheduler Model: Add resources instructions, map resources in subtargets Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
2013-04-01 15:07:05 +02:00
GPR:$Rn))]>,
Sched<[WriteALUSsr, ReadALUsr]>;
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
}
Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. llvm-svn: 37895
2007-07-05 09:13:32 +02:00
}
[ARM] Cleanup so_imm* tblgen defintions No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
2015-01-06 16:55:09 +01:00
/// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. llvm-svn: 38501
2007-07-10 20:08:01 +02:00
/// patterns. Similar to AsI1_bin_irs except the instruction does not produce
Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. llvm-svn: 37895
2007-07-05 09:13:32 +02:00
/// a explicit result, only implicitly set CPSR.
Mark ARM compare instructions as isCompare. llvm-svn: 110761
2010-08-11 02:22:27 +02:00
let isCompare = 1, Defs = [CPSR] in {
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. llvm-svn: 115010
2010-09-29 02:49:25 +02:00
multiclass AI1_cmp_irs<bits<4> opcod, string opc,
InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
SDPatternOperator opnode, bit Commutable = 0,
string rrDecoderMethod = ""> {
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and arithmetic-with-carry-in instructions. llvm-svn: 116384
2010-10-13 02:50:27 +02:00
opc, "\t$Rn, $imm",
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
[(opnode GPR:$Rn, mod_imm:$imm)]>,
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 07:01:06 +02:00
Sched<[WriteCMP, ReadALU]> {
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and arithmetic-with-carry-in instructions. llvm-svn: 116384
2010-10-13 02:50:27 +02:00
bits<4> Rn;
bits<12> imm;
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan. llvm-svn: 74972
2009-07-08 01:40:25 +02:00
let Inst{25} = 1;
Sort bit assignments. Cosmetic change only. llvm-svn: 118029
2010-11-02 18:59:04 +01:00
let Inst{20} = 1;
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and arithmetic-with-carry-in instructions. llvm-svn: 116384
2010-10-13 02:50:27 +02:00
let Inst{19-16} = Rn;
Sort bit assignments. Cosmetic change only. llvm-svn: 118029
2010-11-02 18:59:04 +01:00
let Inst{15-12} = 0b0000;
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and arithmetic-with-carry-in instructions. llvm-svn: 116384
2010-10-13 02:50:27 +02:00
let Inst{11-0} = imm;
Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler. llvm-svn: 154999
2012-04-18 14:48:43 +02:00
let Unpredictable{15-12} = 0b1111;
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan. llvm-svn: 74972
2009-07-08 01:40:25 +02:00
}
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and arithmetic-with-carry-in instructions. llvm-svn: 116384
2010-10-13 02:50:27 +02:00
def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
opc, "\t$Rn, $Rm",
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 07:01:06 +02:00
[(opnode GPR:$Rn, GPR:$Rm)]>,
Sched<[WriteCMP, ReadALU, ReadALU]> {
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and arithmetic-with-carry-in instructions. llvm-svn: 116384
2010-10-13 02:50:27 +02:00
bits<4> Rn;
bits<4> Rm;
Mark a bunch of instructions commutable. llvm-svn: 74237
2009-06-26 02:19:44 +02:00
let isCommutable = Commutable;
Sort bit assignments. Cosmetic change only. llvm-svn: 118029
2010-11-02 18:59:04 +01:00
let Inst{25} = 0;
Add some ARM instruction encoding bits. Patch by Johnny Chen. llvm-svn: 83983
2009-10-13 19:35:30 +02:00
let Inst{20} = 1;
Sort bit assignments. Cosmetic change only. llvm-svn: 118029
2010-11-02 18:59:04 +01:00
let Inst{19-16} = Rn;
let Inst{15-12} = 0b0000;
let Inst{11-4} = 0b00000000;
let Inst{3-0} = Rm;
[ARM] Add v8.1a "Privileged Access Never" extension Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8504 llvm-svn: 235087
2015-04-16 13:34:25 +02:00
let DecoderMethod = rrDecoderMethod;
Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler. llvm-svn: 154999
2012-04-18 14:48:43 +02:00
let Unpredictable{15-12} = 0b1111;
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and arithmetic-with-carry-in instructions. llvm-svn: 116384
2010-10-13 02:50:27 +02:00
}
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
def rsi : AI1<opcod, (outs),
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. llvm-svn: 135722
2011-07-22 01:38:37 +02:00
(ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and arithmetic-with-carry-in instructions. llvm-svn: 116384
2010-10-13 02:50:27 +02:00
opc, "\t$Rn, $shift",
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 07:01:06 +02:00
[(opnode GPR:$Rn, so_reg_imm:$shift)]>,
Sched<[WriteCMPsi, ReadALU]> {
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and arithmetic-with-carry-in instructions. llvm-svn: 116384
2010-10-13 02:50:27 +02:00
bits<4> Rn;
bits<12> shift;
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan. llvm-svn: 74972
2009-07-08 01:40:25 +02:00
let Inst{25} = 0;
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and arithmetic-with-carry-in instructions. llvm-svn: 116384
2010-10-13 02:50:27 +02:00
let Inst{20} = 1;
Sort bit assignments. Cosmetic change only. llvm-svn: 118029
2010-11-02 18:59:04 +01:00
let Inst{19-16} = Rn;
let Inst{15-12} = 0b0000;
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
let Inst{11-5} = shift{11-5};
let Inst{4} = 0;
let Inst{3-0} = shift{3-0};
Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler. llvm-svn: 154999
2012-04-18 14:48:43 +02:00
let Unpredictable{15-12} = 0b1111;
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan. llvm-svn: 74972
2009-07-08 01:40:25 +02:00
}
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
def rsr : AI1<opcod, (outs),
Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler. llvm-svn: 154999
2012-04-18 14:48:43 +02:00
(ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
opc, "\t$Rn, $shift",
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 07:01:06 +02:00
[(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
Sched<[WriteCMPsr, ReadALU]> {
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
bits<4> Rn;
bits<12> shift;
let Inst{25} = 0;
let Inst{20} = 1;
let Inst{19-16} = Rn;
let Inst{15-12} = 0b0000;
let Inst{11-8} = shift{11-8};
let Inst{7} = 0;
let Inst{6-5} = shift{6-5};
let Inst{4} = 1;
let Inst{3-0} = shift{3-0};
Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler. llvm-svn: 154999
2012-04-18 14:48:43 +02:00
let Unpredictable{15-12} = 0b1111;
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
}
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
}
add the FPBinOp class llvm-svn: 30980
2006-10-16 20:32:36 +02:00
Fix zero and sign extension instructions scheduling itineraries. llvm-svn: 114780
2010-09-25 02:49:35 +02:00
/// AI_ext_rrot - A unary operation with two forms: one whose operand is a
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
/// register and one whose operand is a register rotated by 8/16/24.
Encode extend instructions; more clean up. llvm-svn: 58818
2008-11-06 23:15:19 +01:00
/// FIXME: Remove the 'r' variant. Its rot_imm is zero.
ARM extend instructions simplification. Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. llvm-svn: 136225
2011-07-27 18:47:19 +02:00
class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
: AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
ARM extend instructions simplification. Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. llvm-svn: 136225
2011-07-27 18:47:19 +02:00
IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
[(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
ARM extend instructions simplification. Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. llvm-svn: 136225
2011-07-27 18:47:19 +02:00
bits<4> Rd;
bits<4> Rm;
bits<2> rot;
let Inst{19-16} = 0b1111;
let Inst{15-12} = Rd;
let Inst{11-10} = rot;
let Inst{3-0} = Rm;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
}
ARM extend instructions simplification. Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. llvm-svn: 136225
2011-07-27 18:47:19 +02:00
class AI_ext_rrot_np<bits<8> opcod, string opc>
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
: AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
ARM extend instructions simplification. Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. llvm-svn: 136225
2011-07-27 18:47:19 +02:00
IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
ARM extend instructions simplification. Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. llvm-svn: 136225
2011-07-27 18:47:19 +02:00
bits<2> rot;
let Inst{19-16} = 0b1111;
let Inst{11-10} = rot;
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
}
Added SEL, SXTB16, SXTAB16, UXTAB16, SMMULR, SMMLAR, SMMLSR, SMUAD, and SMUSD, for disassembly only. llvm-svn: 96806
2010-02-22 22:50:40 +01:00
Fix zero and sign extension instructions scheduling itineraries. llvm-svn: 114780
2010-09-25 02:49:35 +02:00
/// AI_exta_rrot - A binary operation with two forms: one whose operand is a
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
/// register and one whose operand is a register rotated by 8/16/24.
ARM cleanup of remaining extend instructions. Refactor the rest of the extend instructions to not artificially distinguish between a rotate of zero and a rotate of any other value. Replace the by-zero versions with Pat<>'s for ISel. llvm-svn: 136226
2011-07-27 19:48:13 +02:00
class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
: AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
ARM cleanup of remaining extend instructions. Refactor the rest of the extend instructions to not artificially distinguish between a rotate of zero and a rotate of any other value. Replace the by-zero versions with Pat<>'s for ISel. llvm-svn: 136226
2011-07-27 19:48:13 +02:00
IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
[(set GPRnopc:$Rd, (opnode GPR:$Rn,
(rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
ARM cleanup of remaining extend instructions. Refactor the rest of the extend instructions to not artificially distinguish between a rotate of zero and a rotate of any other value. Replace the by-zero versions with Pat<>'s for ISel. llvm-svn: 136226
2011-07-27 19:48:13 +02:00
bits<4> Rd;
bits<4> Rm;
bits<4> Rn;
bits<2> rot;
let Inst{19-16} = Rn;
let Inst{15-12} = Rd;
let Inst{11-10} = rot;
let Inst{9-4} = 0b000111;
let Inst{3-0} = Rm;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
}
add the FPUnaryOp and DFPUnaryOp classes llvm-svn: 31013
2006-10-17 22:45:22 +02:00
ARM cleanup of remaining extend instructions. Refactor the rest of the extend instructions to not artificially distinguish between a rotate of zero and a rotate of any other value. Replace the by-zero versions with Pat<>'s for ISel. llvm-svn: 136226
2011-07-27 19:48:13 +02:00
class AI_exta_rrot_np<bits<8> opcod, string opc>
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
: AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
ARM cleanup of remaining extend instructions. Refactor the rest of the extend instructions to not artificially distinguish between a rotate of zero and a rotate of any other value. Replace the by-zero versions with Pat<>'s for ISel. llvm-svn: 136226
2011-07-27 19:48:13 +02:00
IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
ARM cleanup of remaining extend instructions. Refactor the rest of the extend instructions to not artificially distinguish between a rotate of zero and a rotate of any other value. Replace the by-zero versions with Pat<>'s for ISel. llvm-svn: 136226
2011-07-27 19:48:13 +02:00
bits<4> Rn;
bits<2> rot;
let Inst{19-16} = Rn;
let Inst{11-10} = rot;
Added SEL, SXTB16, SXTAB16, UXTAB16, SMMULR, SMMLAR, SMMLSR, SMUAD, and SMUSD, for disassembly only. llvm-svn: 96806
2010-02-22 22:50:40 +01:00
}
Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used. llvm-svn: 74228
2009-06-26 01:34:10 +02:00
/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
ARM let TableGen handle a few two-operand aliases. No need for these explicit aliases anymore. Nuke 'em. llvm-svn: 155173
2012-04-20 01:59:26 +02:00
let TwoOperandAliasConstraint = "$Rn = $Rd" in
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode,
ARM: Tidy up. Remove unused template parameters. llvm-svn: 161222
2012-08-03 00:08:27 +02:00
bit Commutable = 0> {
Restore hasPostISelHook tblgen flag. No functionality change. The hook makes it explicit which patterns require "special" handling. i.e. it self-documents tblgen deficiencies. I plan to add verification in ExpandISelPseudos and Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's too fragile. llvm-svn: 140160
2011-09-20 20:22:31 +02:00
let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
Add ARM mode operand encoding information for ADDE/SUBE instructions. llvm-svn: 116412
2010-10-13 20:00:52 +02:00
DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
[(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 07:01:06 +02:00
Requires<[IsARM]>,
Sched<[WriteALU, ReadALU]> {
Add ARM mode operand encoding information for ADDE/SUBE instructions. llvm-svn: 116412
2010-10-13 20:00:52 +02:00
bits<4> Rd;
bits<4> Rn;
bits<12> imm;
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan. llvm-svn: 74972
2009-07-08 01:40:25 +02:00
let Inst{25} = 1;
Add ARM mode operand encoding information for ADDE/SUBE instructions. llvm-svn: 116412
2010-10-13 20:00:52 +02:00
let Inst{15-12} = Rd;
let Inst{19-16} = Rn;
let Inst{11-0} = imm;
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan. llvm-svn: 74972
2009-07-08 01:40:25 +02:00
}
Add ARM mode operand encoding information for ADDE/SUBE instructions. llvm-svn: 116412
2010-10-13 20:00:52 +02:00
def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
[(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 07:01:06 +02:00
Requires<[IsARM]>,
Sched<[WriteALU, ReadALU, ReadALU]> {
Add ARM mode operand encoding information for ADDE/SUBE instructions. llvm-svn: 116412
2010-10-13 20:00:52 +02:00
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
My previous patch (r84124) for setting the encoding bits 4 and 7 of DPSoRegFrm was wrong and too aggressive in the sense that DPSoRegFrm includes both constant shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and Inst{7} = 0). The 'rr' fragment of the multiclass definitions actually means register/register with no shift, see A8-11. llvm-svn: 86319
2009-11-07 01:54:36 +01:00
let Inst{11-4} = 0b00000000;
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan. llvm-svn: 74972
2009-07-08 01:40:25 +02:00
let Inst{25} = 0;
Add ARM mode operand encoding information for ADDE/SUBE instructions. llvm-svn: 116412
2010-10-13 20:00:52 +02:00
let isCommutable = Commutable;
let Inst{3-0} = Rm;
let Inst{15-12} = Rd;
let Inst{19-16} = Rn;
Mark a bunch of instructions commutable. llvm-svn: 74237
2009-06-26 02:19:44 +02:00
}
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
def rsi : AsI1<opcod, (outs GPR:$Rd),
(ins GPR:$Rn, so_reg_imm:$shift),
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. llvm-svn: 135722
2011-07-22 01:38:37 +02:00
DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
[(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 07:01:06 +02:00
Requires<[IsARM]>,
Sched<[WriteALUsi, ReadALU]> {
Add ARM mode operand encoding information for ADDE/SUBE instructions. llvm-svn: 116412
2010-10-13 20:00:52 +02:00
bits<4> Rd;
bits<4> Rn;
bits<12> shift;
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan. llvm-svn: 74972
2009-07-08 01:40:25 +02:00
let Inst{25} = 0;
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
let Inst{19-16} = Rn;
Add ARM mode operand encoding information for ADDE/SUBE instructions. llvm-svn: 116412
2010-10-13 20:00:52 +02:00
let Inst{15-12} = Rd;
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
let Inst{11-5} = shift{11-5};
let Inst{4} = 0;
let Inst{3-0} = shift{3-0};
}
Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions. llvm-svn: 154101
2012-04-05 18:19:29 +02:00
def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
(ins GPRnopc:$Rn, so_reg_reg:$shift),
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. llvm-svn: 135722
2011-07-22 01:38:37 +02:00
DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
Tidy up. 80 columns, whitespace, et. al. llvm-svn: 155399
2012-04-24 00:04:10 +02:00
[(set GPRnopc:$Rd, CPSR,
(opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 07:01:06 +02:00
Requires<[IsARM]>,
Sched<[WriteALUsr, ReadALUsr]> {
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
bits<4> Rd;
bits<4> Rn;
bits<12> shift;
let Inst{25} = 0;
Add ARM mode operand encoding information for ADDE/SUBE instructions. llvm-svn: 116412
2010-10-13 20:00:52 +02:00
let Inst{19-16} = Rn;
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
let Inst{15-12} = Rd;
let Inst{11-8} = shift{11-8};
let Inst{7} = 0;
let Inst{6-5} = shift{6-5};
let Inst{4} = 1;
let Inst{3-0} = shift{3-0};
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan. llvm-svn: 74972
2009-07-08 01:40:25 +02:00
}
Destination register operand is optional for ADC and SBC ARM. llvm-svn: 135052
2011-07-13 19:57:17 +02:00
}
Fix another using-CPSR-twice bug in my ADCS/SBCS cleanups, and make proper use of the Commutable bit. llvm-svn: 129294
2011-04-11 22:12:19 +02:00
}
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
/// AI1_rsc_irs - Define instructions and patterns for rsc
ARM let TableGen handle a few two-operand aliases. No need for these explicit aliases anymore. Nuke 'em. llvm-svn: 155173
2012-04-20 01:59:26 +02:00
let TwoOperandAliasConstraint = "$Rn = $Rd" in
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
multiclass AI1_rsc_irs<bits<4> opcod, string opc, SDNode opnode> {
Restore hasPostISelHook tblgen flag. No functionality change. The hook makes it explicit which patterns require "special" handling. i.e. it self-documents tblgen deficiencies. I plan to add verification in ExpandISelPseudos and Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's too fragile. llvm-svn: 140160
2011-09-20 20:22:31 +02:00
let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
[(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 07:01:06 +02:00
Requires<[IsARM]>,
Sched<[WriteALU, ReadALU]> {
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
bits<4> Rd;
bits<4> Rn;
bits<12> imm;
let Inst{25} = 1;
let Inst{15-12} = Rd;
let Inst{19-16} = Rn;
let Inst{11-0} = imm;
Fix another using-CPSR-twice bug in my ADCS/SBCS cleanups, and make proper use of the Commutable bit. llvm-svn: 129294
2011-04-11 22:12:19 +02:00
}
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 07:01:06 +02:00
[/* pattern left blank */]>,
Sched<[WriteALU, ReadALU, ReadALU]> {
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
let Inst{11-4} = 0b00000000;
let Inst{25} = 0;
let Inst{3-0} = Rm;
let Inst{15-12} = Rd;
let Inst{19-16} = Rn;
}
def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
[(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 07:01:06 +02:00
Requires<[IsARM]>,
Sched<[WriteALUsi, ReadALU]> {
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
bits<4> Rd;
bits<4> Rn;
bits<12> shift;
let Inst{25} = 0;
let Inst{19-16} = Rn;
let Inst{15-12} = Rd;
let Inst{11-5} = shift{11-5};
let Inst{4} = 0;
let Inst{3-0} = shift{3-0};
}
def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
[(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 07:01:06 +02:00
Requires<[IsARM]>,
Sched<[WriteALUsr, ReadALUsr]> {
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
bits<4> Rd;
bits<4> Rn;
bits<12> shift;
let Inst{25} = 0;
let Inst{19-16} = Rn;
let Inst{15-12} = Rd;
let Inst{11-8} = shift{11-8};
let Inst{7} = 0;
let Inst{6-5} = shift{6-5};
let Inst{4} = 1;
let Inst{3-0} = shift{3-0};
}
}
Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. llvm-svn: 37895
2007-07-05 09:13:32 +02:00
}
First part of refactoring ARM addrmode2 (load/store) instructions to be more explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
2010-10-27 00:37:02 +02:00
let canFoldAsLoad = 1, isReMaterializable = 1 in {
More ARM load/store indexed refactoring. Also fix an incorrect IndexMode flag for the LDRT/STRT family instructions as a side effect. llvm-svn: 118955
2010-11-13 01:35:48 +01:00
multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
First part of refactoring ARM addrmode2 (load/store) instructions to be more explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
2010-10-27 00:37:02 +02:00
InstrItinClass iir, PatFrag opnode> {
// Note: We use the complex addrmode_imm12 rather than just an input
// GPR and a constrained immediate so that we can use this to match
// frame index references and avoid matching constant pool references.
Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes. llvm-svn: 119840
2010-11-19 22:07:51 +01:00
def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
First part of refactoring ARM addrmode2 (load/store) instructions to be more explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
2010-10-27 00:37:02 +02:00
AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
[(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
The MC code couldn't handle ARM LDR instructions with negative offsets: vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. llvm-svn: 118144
2010-11-03 02:49:29 +01:00
bits<4> Rt;
bits<17> addr;
let Inst{23} = addr{12}; // U (add = ('U' == 1))
let Inst{19-16} = addr{16-13}; // Rn
First part of refactoring ARM addrmode2 (load/store) instructions to be more explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
2010-10-27 00:37:02 +02:00
let Inst{15-12} = Rt;
let Inst{11-0} = addr{11-0}; // imm12
}
Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes. llvm-svn: 119840
2010-11-19 22:07:51 +01:00
def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
First part of refactoring ARM addrmode2 (load/store) instructions to be more explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
2010-10-27 00:37:02 +02:00
AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
[(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
The MC code couldn't handle ARM LDR instructions with negative offsets: vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. llvm-svn: 118144
2010-11-03 02:49:29 +01:00
bits<4> Rt;
bits<17> shift;
Fix single word and unsigned byte data transfer instruction encodings so that Inst{4} = 0. rdar://problem/9213022 llvm-svn: 128662
2011-03-31 21:28:35 +02:00
let shift{4} = 0; // Inst{4} = 0
The MC code couldn't handle ARM LDR instructions with negative offsets: vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. llvm-svn: 118144
2010-11-03 02:49:29 +01:00
let Inst{23} = shift{12}; // U (add = ('U' == 1))
let Inst{19-16} = shift{16-13}; // Rn
Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding. llvm-svn: 118600
2010-11-09 19:43:54 +01:00
let Inst{15-12} = Rt;
First part of refactoring ARM addrmode2 (load/store) instructions to be more explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
2010-10-27 00:37:02 +02:00
let Inst{11-0} = shift{11-0};
}
}
}
Continue to tighten decoding by performing more operand validation. llvm-svn: 137340
2011-08-11 22:21:46 +02:00
let canFoldAsLoad = 1, isReMaterializable = 1 in {
multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
InstrItinClass iir, PatFrag opnode> {
// Note: We use the complex addrmode_imm12 rather than just an input
// GPR and a constrained immediate so that we can use this to match
// frame index references and avoid matching constant pool references.
Tidy up. 80 columns, whitespace, et. al. llvm-svn: 155399
2012-04-24 00:04:10 +02:00
def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
(ins addrmode_imm12:$addr),
Continue to tighten decoding by performing more operand validation. llvm-svn: 137340
2011-08-11 22:21:46 +02:00
AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
Tidy up. 80 columns, whitespace, et. al. llvm-svn: 155399
2012-04-24 00:04:10 +02:00
[(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
Continue to tighten decoding by performing more operand validation. llvm-svn: 137340
2011-08-11 22:21:46 +02:00
bits<4> Rt;
bits<17> addr;
let Inst{23} = addr{12}; // U (add = ('U' == 1))
let Inst{19-16} = addr{16-13}; // Rn
let Inst{15-12} = Rt;
let Inst{11-0} = addr{11-0}; // imm12
}
Tidy up. 80 columns, whitespace, et. al. llvm-svn: 155399
2012-04-24 00:04:10 +02:00
def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
(ins ldst_so_reg:$shift),
AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
[(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
Continue to tighten decoding by performing more operand validation. llvm-svn: 137340
2011-08-11 22:21:46 +02:00
bits<4> Rt;
bits<17> shift;
let shift{4} = 0; // Inst{4} = 0
let Inst{23} = shift{12}; // U (add = ('U' == 1))
let Inst{19-16} = shift{16-13}; // Rn
let Inst{15-12} = Rt;
let Inst{11-0} = shift{11-0};
}
}
}
More ARM load/store indexed refactoring. Also fix an incorrect IndexMode flag for the LDRT/STRT family instructions as a side effect. llvm-svn: 118955
2010-11-13 01:35:48 +01:00
multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 llvm-svn: 117505
2010-10-28 01:12:14 +02:00
InstrItinClass iir, PatFrag opnode> {
// Note: We use the complex addrmode_imm12 rather than just an input
// GPR and a constrained immediate so that we can use this to match
// frame index references and avoid matching constant pool references.
Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes. llvm-svn: 119840
2010-11-19 22:07:51 +01:00
def i12 : AI2ldst<0b010, 0, isByte, (outs),
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 llvm-svn: 117505
2010-10-28 01:12:14 +02:00
(ins GPR:$Rt, addrmode_imm12:$addr),
AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
[(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
bits<4> Rt;
bits<17> addr;
let Inst{23} = addr{12}; // U (add = ('U' == 1))
let Inst{19-16} = addr{16-13}; // Rn
let Inst{15-12} = Rt;
let Inst{11-0} = addr{11-0}; // imm12
}
Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes. llvm-svn: 119840
2010-11-19 22:07:51 +01:00
def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 llvm-svn: 117505
2010-10-28 01:12:14 +02:00
AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
[(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
bits<4> Rt;
bits<17> shift;
Fix single word and unsigned byte data transfer instruction encodings so that Inst{4} = 0. rdar://problem/9213022 llvm-svn: 128662
2011-03-31 21:28:35 +02:00
let shift{4} = 0; // Inst{4} = 0
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 llvm-svn: 117505
2010-10-28 01:12:14 +02:00
let Inst{23} = shift{12}; // U (add = ('U' == 1))
let Inst{19-16} = shift{16-13}; // Rn
Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding. llvm-svn: 118600
2010-11-09 19:43:54 +01:00
let Inst{15-12} = Rt;
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 llvm-svn: 117505
2010-10-28 01:12:14 +02:00
let Inst{11-0} = shift{11-0};
}
}
Continue to tighten decoding by performing more operand validation. llvm-svn: 137340
2011-08-11 22:21:46 +02:00
multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
InstrItinClass iir, PatFrag opnode> {
// Note: We use the complex addrmode_imm12 rather than just an input
// GPR and a constrained immediate so that we can use this to match
// frame index references and avoid matching constant pool references.
def i12 : AI2ldst<0b010, 0, isByte, (outs),
(ins GPRnopc:$Rt, addrmode_imm12:$addr),
AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
[(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
bits<4> Rt;
bits<17> addr;
let Inst{23} = addr{12}; // U (add = ('U' == 1))
let Inst{19-16} = addr{16-13}; // Rn
let Inst{15-12} = Rt;
let Inst{11-0} = addr{11-0}; // imm12
}
Tidy up. 80 columns, whitespace, et. al. llvm-svn: 155399
2012-04-24 00:04:10 +02:00
def rs : AI2ldst<0b011, 0, isByte, (outs),
(ins GPRnopc:$Rt, ldst_so_reg:$shift),
AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
[(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
Continue to tighten decoding by performing more operand validation. llvm-svn: 137340
2011-08-11 22:21:46 +02:00
bits<4> Rt;
bits<17> shift;
let shift{4} = 0; // Inst{4} = 0
let Inst{23} = shift{12}; // U (add = ('U' == 1))
let Inst{19-16} = shift{16-13}; // Rn
let Inst{15-12} = Rt;
let Inst{11-0} = shift{11-0};
}
}
define the IntBinOp class and use it to implement the multiply instructions llvm-svn: 30978
2006-10-16 19:57:20 +02:00
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
//===----------------------------------------------------------------------===//
// Miscellaneous Instructions.
//
/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
/// the function. The first operand is the ID# for this instruction, the second
/// is the index into the MachineConstantPool that this is, the third is the
/// size in bytes of this constant pool entry.
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 01:46:26 +01:00
let hasSideEffects = 0, isNotDuplicable = 1 in
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
def CONSTPOOL_ENTRY :
Change instruction description to split OperandList into OutOperandList and InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
2007-07-19 03:14:50 +02:00
PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
ARM PseudoInst instructions don't need or use an assembler string. Get rid of the operand to the pattern. llvm-svn: 119607
2010-11-18 02:38:26 +01:00
i32imm:$size), NoItinerary, []>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
ARM: recommit r237590: allow jump tables to be placed as constant islands. The original version didn't properly account for the base register being modified before the final jump, so caused miscompilations in Chromium and LLVM. I've fixed this and tested with an LLVM self-host (I don't have the means to build & test Chromium). The general idea remains the same: in pathological cases jump tables can be too far away from the instructions referencing them (like other constants) so they need to be movable. Should fix PR23627. llvm-svn: 238680
2015-05-31 21:22:07 +02:00
/// A jumptable consisting of direct 32-bit addresses of the destination basic
/// blocks (either absolute, or relative to the start of the jump-table in PIC
/// mode). Used mostly in ARM and Thumb-1 modes.
def JUMPTABLE_ADDRS :
PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
i32imm:$size), NoItinerary, []>;
/// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables
/// that cannot be optimised to use TBB or TBH.
def JUMPTABLE_INSTS :
PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
i32imm:$size), NoItinerary, []>;
/// A jumptable consisting of 8-bit unsigned integers representing offsets from
/// a TBB instruction.
def JUMPTABLE_TBB :
PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
i32imm:$size), NoItinerary, []>;
/// A jumptable consisting of 16-bit unsigned integers representing offsets from
/// a TBH instruction.
def JUMPTABLE_TBH :
PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
i32imm:$size), NoItinerary, []>;
Updated version of r96634 (which was reverted due to failing 176.gcc and 126.gcc nightly tests. These failures uncovered latent bugs that machine DCE could remove one half of a stack adjust down/up pair, causing PEI to assert. This update fixes that, and the tests now pass. llvm-svn: 96822
2010-02-23 00:10:38 +01:00
// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
// from removing one half of the matched pairs. That breaks PEI, which assumes
// these will always be in pairs, and asserts if it finds otherwise. Better way?
let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
def ADJCALLSTACKUP :
ARM PseudoInst instructions don't need or use an assembler string. Get rid of the operand to the pattern. llvm-svn: 119607
2010-11-18 02:38:26 +01:00
PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as parameters instead of raw Constants. This prevents the constants from being selected by the isel pass, fixing PR2735. llvm-svn: 57385
2008-10-12 00:08:30 +02:00
[(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Remove trailing whitespace llvm-svn: 96388
2010-02-16 22:07:46 +01:00
def ADJCALLSTACKDOWN :
Add extra operand to CALLSEQ_START to keep frame part set up previously Using arguments with attribute inalloca creates problems for verification of machine representation. This attribute instructs the backend that the argument is prepared in stack prior to CALLSEQ_START..CALLSEQ_END sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size stored in CALLSEQ_START in this case does not count the size of this argument. However CALLSEQ_END still keeps total frame size, as caller can be responsible for cleanup of entire frame. So CALLSEQ_START and CALLSEQ_END keep different frame size and the difference is treated by MachineVerifier as stack error. Currently there is no way to distinguish this case from actual errors. This patch adds additional argument to CALLSEQ_START and its target-specific counterparts to keep size of stack that is set up prior to the call frame sequence. This argument allows MachineVerifier to calculate actual frame size associated with frame setup instruction and correctly process the case of inalloca arguments. The changes made by the patch are: - Frame setup instructions get the second mandatory argument. It affects all targets that use frame pseudo instructions and touched many files although the changes are uniform. - Access to frame properties are implemented using special instructions rather than calls getOperand(N).getImm(). For X86 and ARM such replacement was made previously. - Changes that reflect appearance of additional argument of frame setup instruction. These involve proper instruction initialization and methods that access instruction arguments. - MachineVerifier retrieves frame size using method, which reports sum of frame parts initialized inside frame instruction pair and outside it. The patch implements approach proposed by Quentin Colombet in https://bugs.llvm.org/show_bug.cgi?id=27481#c1. It fixes 9 tests failed with machine verifier enabled and listed in PR27481. Differential Revision: https://reviews.llvm.org/D32394 llvm-svn: 302527
2017-05-09 15:35:13 +02:00
PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2, pred:$p), NoItinerary,
[(ARMcallseq_start timm:$amt, timm:$amt2)]>;
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Make ARM hint ranges consistent, and add tests for these ranges llvm-svn: 193238
2013-10-23 12:14:40 +02:00
def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
ARM: provide a new generic hint intrinsic Introduce the llvm.arm.hint(i32) intrinsic that can be used to inject hints into the instruction stream. This is particularly useful for generating IR from a compiler where the user may inject an intrinsic (e.g. __yield). These are then pattern substituted into the correct instruction which already existed. llvm-svn: 207242
2014-04-25 19:24:24 +02:00
"hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>,
Requires<[IsARM, HasV6]> {
[ARM] Introduce the 'sevl' instruction in ARMv8. This also removes the restriction on the immediate field of the 'hint' instruction. llvm-svn: 191744
2013-10-01 14:39:11 +02:00
bits<8> imm;
let Inst{27-8} = 0b00110010000011110000;
let Inst{7-0} = imm;
RAS extensions are part of ARMv8.2-A. This change enables them by introducing a new instruction to ARM and AArch64 targets and several system registers. Patch by: Roger Ferrer Ibanez and Oliver Stannard Differential Revision: http://reviews.llvm.org/D20282 llvm-svn: 271670
2016-06-03 16:03:27 +02:00
let DecoderMethod = "DecodeHINTInstruction";
Added NOP, DBG, SVC to the instruction table for disassembly purpose. llvm-svn: 95784
2010-02-10 19:02:25 +01:00
}
[ARM] Add support for ARMV6K subtarget (LLVM) ARMv6K is another layer between ARMV6 and ARMV6T2. This is the LLVM side of the changes. ARMV6 family LLVM implementation. +-------------------------------------+ | ARMV6 | +----------------+--------------------+ | ARMV6M (thumb) | ARMV6K (arm,thumb) | <- From ARMV6K and ARMV6M processors +----------------+--------------------+ have support for hint instructions | ARMV6T2 (arm,thumb,thumb2) | (SEV/WFE/WFI/NOP/YIELD). They can +-------------------------------------+ be either real or default to NOP. | ARMV7 (arm,thumb,thumb2) | The two processors also use +-------------------------------------+ different encoding for them. Patch by Vinicius Tinti. llvm-svn: 232468
2015-03-17 12:55:28 +01:00
def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>;
def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>;
def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>;
def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>;
def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
[ARM] Introduce the 'sevl' instruction in ARMv8. This also removes the restriction on the immediate field of the 'hint' instruction. llvm-svn: 191744
2013-10-01 14:39:11 +02:00
def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
RAS extensions are part of ARMv8.2-A. This change enables them by introducing a new instruction to ARM and AArch64 targets and several system registers. Patch by: Roger Ferrer Ibanez and Oliver Stannard Differential Revision: http://reviews.llvm.org/D20282 llvm-svn: 271670
2016-06-03 16:03:27 +02:00
def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>;
[ARM][AArch64] Add CSDB speculation barrier instruction This adds the CSDB instruction, which is a new barrier instruction described by the whitepaper at [1]. This is in encoding space which was previously executed as a NOP, so it is available for all targets that have the relevant NOP encoding space. This matches the binutils behaviour for these instructions [2][3]. [1] https://developer.arm.com/support/security-update [2] https://sourceware.org/ml/binutils/2018-01/msg00116.html [3] https://sourceware.org/ml/binutils/2018-01/msg00120.html llvm-svn: 324324
2018-02-06 10:24:47 +01:00
def : InstAlias<"csdb$p", (HINT 20, pred:$p)>, Requires<[IsARM, HasV6K]>;
[ARM] Introduce the 'sevl' instruction in ARMv8. This also removes the restriction on the immediate field of the 'hint' instruction. llvm-svn: 191744
2013-10-01 14:39:11 +02:00
Making SEL decodings auto-generate-able. llvm-svn: 137363
2011-08-11 23:50:56 +02:00
def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
"\t$Rd, $Rn, $Rm",
[(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>,
Requires<[IsARM, HasV6]> {
Make a few more bits of some simple instructions explicit. nop, yield, wfe, wfi, sel, sev and bkpt. All would disassemble properly before, but more explicitness is good, especially with the integrated assembler coming in the future. llvm-svn: 116427
2010-10-13 22:30:55 +02:00
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
let Inst{3-0} = Rm;
let Inst{15-12} = Rd;
let Inst{19-16} = Rn;
Added SEL, SXTB16, SXTAB16, UXTAB16, SMMULR, SMMLAR, SMMLSR, SMUAD, and SMUSD, for disassembly only. llvm-svn: 96806
2010-02-22 22:50:40 +01:00
let Inst{27-20} = 0b01101000;
let Inst{7-4} = 0b1011;
Make a few more bits of some simple instructions explicit. nop, yield, wfe, wfi, sel, sev and bkpt. All would disassemble properly before, but more explicitness is good, especially with the integrated assembler coming in the future. llvm-svn: 116427
2010-10-13 22:30:55 +02:00
let Inst{11-8} = 0b1111;
Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. llvm-svn: 156609
2012-05-11 11:28:27 +02:00
let Unpredictable{11-8} = 0b1111;
Added SEL, SXTB16, SXTAB16, UXTAB16, SMMULR, SMMLAR, SMMLSR, SMUAD, and SMUSD, for disassembly only. llvm-svn: 96806
2010-02-22 22:50:40 +01:00
}
ARM: Define generic HINT instruction. The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/ a different immediate value in bits [7,0]. Define a generic HINT instruction and refactor NOP, WFI, WFI, SEV and YIELD to be assembly aliases of that. rdar://11600518 llvm-svn: 158674
2012-06-18 21:45:50 +02:00
// The 16-bit operand $val can be used by a debugger to store more information
Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose. llvm-svn: 95884
2010-02-11 19:12:29 +01:00
// about the breakpoint.
ARM: fix more cases where predication may or may not be allowed Unfortunately this addresses two issues (by the time I'd disentangled the logic it wasn't worth putting it back to half-broken): + Coprocessor instructions should all be predicable in Thumb mode. + BKPT should never be predicable. llvm-svn: 184965
2013-06-26 18:52:40 +02:00
def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
"bkpt", "\t$val", []>, Requires<[IsARM]> {
Make a few more bits of some simple instructions explicit. nop, yield, wfe, wfi, sel, sev and bkpt. All would disassemble properly before, but more explicitness is good, especially with the integrated assembler coming in the future. llvm-svn: 116427
2010-10-13 22:30:55 +02:00
bits<16> val;
let Inst{3-0} = val{3-0};
let Inst{19-8} = val{15-4};
Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose. llvm-svn: 95884
2010-02-11 19:12:29 +01:00
let Inst{27-20} = 0b00010010;
ARM: fix more cases where predication may or may not be allowed Unfortunately this addresses two issues (by the time I'd disentangled the logic it wasn't worth putting it back to half-broken): + Coprocessor instructions should all be predicable in Thumb mode. + BKPT should never be predicable. llvm-svn: 184965
2013-06-26 18:52:40 +02:00
let Inst{31-28} = 0xe; // AL
Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose. llvm-svn: 95884
2010-02-11 19:12:29 +01:00
let Inst{7-4} = 0b0111;
}
ARM: bkpt has an implicit immediate constant 0 The bkpt mnemonic has an implicit immediate constant of 0 unless otherwise specified. Add an instruction alias for the unvalued breakpoint mnemonic to treat it as a 0. This improves compatibility with GNU AS. Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org> llvm-svn: 197913
2013-12-23 18:23:58 +01:00
// default immediate for breakpoint mnemonic
ARM target does not use printAliasInstr machinery which forces having special checks in ArmInstPrinter::printInstruction. This patch addresses this issue. Not all special checks could be removed: either they involve elaborated conditions under which the alias is emitted (e.g. ldm/stm on sp may be pop/push but only if the number of registers is >= 2) or the number of registers is multivalued (like happens again with ldm/stm) and they do not match the InstAlias pattern which assumes single-valued operands in the pattern. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20237 llvm-svn: 271667
2016-06-03 15:19:43 +02:00
def : InstAlias<"bkpt", (BKPT 0), 0>, Requires<[IsARM]>;
Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose. llvm-svn: 95884
2010-02-11 19:12:29 +01:00
Add AArch32 DCPS{1,2,3} and HLT instructions. These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. llvm-svn: 190053
2013-09-05 16:14:19 +02:00
def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
"hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
bits<16> val;
let Inst{3-0} = val{3-0};
let Inst{19-8} = val{15-4};
let Inst{27-20} = 0b00010000;
let Inst{31-28} = 0xe; // AL
let Inst{7-4} = 0b0111;
}
Update FIXME. llvm-svn: 136470
2011-07-29 19:36:04 +02:00
// Change Processor State
// FIXME: We should use InstAlias to handle the optional operands.
Fix encoding and add parsing support for the arm/thumb CPS instruction: - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489
2011-02-14 14:09:44 +01:00
class CPS<dag iops, string asm_ops>
: AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
Tweak comment. llvm-svn: 136468
2011-07-29 19:33:29 +02:00
[]>, Requires<[IsARM]> {
Fix encoding and add parsing support for the arm/thumb CPS instruction: - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489
2011-02-14 14:09:44 +01:00
bits<2> imod;
bits<3> iflags;
bits<5> mode;
bit M;
Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only. llvm-svn: 95999
2010-02-12 19:55:33 +01:00
let Inst{31-28} = 0b1111;
let Inst{27-20} = 0b00010000;
Fix encoding and add parsing support for the arm/thumb CPS instruction: - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489
2011-02-14 14:09:44 +01:00
let Inst{19-18} = imod;
let Inst{17} = M; // Enabled if mode is set;
Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. llvm-svn: 143208
2011-10-28 20:02:13 +02:00
let Inst{16-9} = 0b00000000;
Fix encoding and add parsing support for the arm/thumb CPS instruction: - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489
2011-02-14 14:09:44 +01:00
let Inst{8-6} = iflags;
let Inst{5} = 0;
let Inst{4-0} = mode;
}
Tighten operand checking on CPS instructions. llvm-svn: 137172
2011-08-10 01:05:39 +02:00
let DecoderMethod = "DecodeCPSInstruction" in {
Fix encoding and add parsing support for the arm/thumb CPS instruction: - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489
2011-02-14 14:09:44 +01:00
let M = 1 in
ARM CPS mode immediate is 5 bits, not 4. llvm-svn: 136505
2011-07-29 22:02:39 +02:00
def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
Fix encoding and add parsing support for the arm/thumb CPS instruction: - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489
2011-02-14 14:09:44 +01:00
"$imod\t$iflags, $mode">;
let mode = 0, M = 0 in
def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
let imod = 0, iflags = 0, M = 1 in
ARM CPS mode immediate is 5 bits, not 4. llvm-svn: 136505
2011-07-29 22:02:39 +02:00
def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
Tighten operand checking on CPS instructions. llvm-svn: 137172
2011-08-10 01:05:39 +02:00
}
Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only. llvm-svn: 95999
2010-02-12 19:55:33 +01:00
Undo r96654. The printing of ARM shift instructions in canonical forms can be handled in ARMInstPrinter.cpp. And added PLD/PLDW/PLI (Preload Data/Instruction) for disassembly only. llvm-svn: 96719
2010-02-21 05:42:01 +01:00
// Preload signals the memory system of possible future data/instruction access.
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli. llvm-svn: 118237
2010-11-04 06:19:35 +01:00
multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
Undo r96654. The printing of ARM shift instructions in canonical forms can be handled in ARMInstPrinter.cpp. And added PLD/PLDW/PLI (Preload Data/Instruction) for disassembly only. llvm-svn: 96719
2010-02-21 05:42:01 +01:00
Fix unsupported addressing mode assertion for pld Summary: This commit gives an address mode to the PLD instruction. We were getting an assertion failure in the frame lowering code because we had code that was doing a pld of a stack allocated address. The frame lowering was checking the address mode and then asserting because pld had none defined. This commit fixes pld for arm mode. There was a previous fix for thumb mode in a separate commit. The commit for thumb mode added a test in a separate file because it would otherwise fail for arm. This commit moves the thumb test back into the prefetch.ll file and adds the corresponding arm test. Differential Revision: http://llvm-reviews.chandlerc.com/D2622 llvm-svn: 200248
2014-01-27 22:39:04 +01:00
def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm,
IIC_Preload, !strconcat(opc, "\t$addr"),
ARM sched model: Add preload instructions Reapply 183261. llvm-svn: 183425
2013-06-06 19:26:12 +02:00
[(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
Sched<[WritePreLd]> {
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. llvm-svn: 117571
2010-10-28 20:34:10 +02:00
bits<4> Rt;
bits<17> addr;
Undo r96654. The printing of ARM shift instructions in canonical forms can be handled in ARMInstPrinter.cpp. And added PLD/PLDW/PLI (Preload Data/Instruction) for disassembly only. llvm-svn: 96719
2010-02-21 05:42:01 +01:00
let Inst{31-26} = 0b111101;
let Inst{25} = 0; // 0 for immediate form
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli. llvm-svn: 118237
2010-11-04 06:19:35 +01:00
let Inst{24} = data;
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. llvm-svn: 117571
2010-10-28 20:34:10 +02:00
let Inst{23} = addr{12}; // U (add = ('U' == 1))
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli. llvm-svn: 118237
2010-11-04 06:19:35 +01:00
let Inst{22} = read;
Undo r96654. The printing of ARM shift instructions in canonical forms can be handled in ARMInstPrinter.cpp. And added PLD/PLDW/PLI (Preload Data/Instruction) for disassembly only. llvm-svn: 96719
2010-02-21 05:42:01 +01:00
let Inst{21-20} = 0b01;
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. llvm-svn: 117571
2010-10-28 20:34:10 +02:00
let Inst{19-16} = addr{16-13}; // Rn
Fix PLD encoding. llvm-svn: 124458
2011-01-28 00:48:34 +01:00
let Inst{15-12} = 0b1111;
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. llvm-svn: 117571
2010-10-28 20:34:10 +02:00
let Inst{11-0} = addr{11-0}; // imm12
Undo r96654. The printing of ARM shift instructions in canonical forms can be handled in ARMInstPrinter.cpp. And added PLD/PLDW/PLI (Preload Data/Instruction) for disassembly only. llvm-svn: 96719
2010-02-21 05:42:01 +01:00
}
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. llvm-svn: 118160
2010-11-03 07:34:55 +01:00
def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536. llvm-svn: 118152
2010-11-03 06:14:24 +01:00
!strconcat(opc, "\t$shift"),
ARM sched model: Add preload instructions Reapply 183261. llvm-svn: 183425
2013-06-06 19:26:12 +02:00
[(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
Sched<[WritePreLd]> {
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. llvm-svn: 117571
2010-10-28 20:34:10 +02:00
bits<17> shift;
Undo r96654. The printing of ARM shift instructions in canonical forms can be handled in ARMInstPrinter.cpp. And added PLD/PLDW/PLI (Preload Data/Instruction) for disassembly only. llvm-svn: 96719
2010-02-21 05:42:01 +01:00
let Inst{31-26} = 0b111101;
let Inst{25} = 1; // 1 for register form
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli. llvm-svn: 118237
2010-11-04 06:19:35 +01:00
let Inst{24} = data;
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. llvm-svn: 117571
2010-10-28 20:34:10 +02:00
let Inst{23} = shift{12}; // U (add = ('U' == 1))
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli. llvm-svn: 118237
2010-11-04 06:19:35 +01:00
let Inst{22} = read;
Undo r96654. The printing of ARM shift instructions in canonical forms can be handled in ARMInstPrinter.cpp. And added PLD/PLDW/PLI (Preload Data/Instruction) for disassembly only. llvm-svn: 96719
2010-02-21 05:42:01 +01:00
let Inst{21-20} = 0b01;
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. llvm-svn: 117571
2010-10-28 20:34:10 +02:00
let Inst{19-16} = shift{16-13}; // Rn
Fix PLD encoding. llvm-svn: 124458
2011-01-28 00:48:34 +01:00
let Inst{15-12} = 0b1111;
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. llvm-svn: 117571
2010-10-28 20:34:10 +02:00
let Inst{11-0} = shift{11-0};
Specify an additional fixed bit in the PLD/PLDW/PLI register-register encoding. llvm-svn: 138760
2011-08-29 22:42:00 +02:00
let Inst{4} = 0;
Undo r96654. The printing of ARM shift instructions in canonical forms can be handled in ARMInstPrinter.cpp. And added PLD/PLDW/PLI (Preload Data/Instruction) for disassembly only. llvm-svn: 96719
2010-02-21 05:42:01 +01:00
}
}
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli. llvm-svn: 118237
2010-11-04 06:19:35 +01:00
defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
Undo r96654. The printing of ARM shift instructions in canonical forms can be handled in ARMInstPrinter.cpp. And added PLD/PLDW/PLI (Preload Data/Instruction) for disassembly only. llvm-svn: 96719
2010-02-21 05:42:01 +01:00
Tidy up. llvm-svn: 135777
2011-07-22 19:46:13 +02:00
def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
Add an instruction deprecation feature to TableGen. The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. llvm-svn: 190598
2013-09-12 12:28:05 +02:00
"setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern and handle the operand explicitly. Flesh out encoding information. Add an explicit disassembler testcase for the instruction. llvm-svn: 116432
2010-10-13 23:00:04 +02:00
bits<1> end;
let Inst{31-10} = 0b1111000100000001000000;
let Inst{9} = end;
let Inst{8-0} = 0;
Add SETEND and BXJ instructions for disassembly only. llvm-svn: 96075
2010-02-13 03:51:09 +01:00
}
ARM Assembler support for DBG instruction. Add range checking and testing for parsing and encoding of DBG instruction. llvm-svn: 135102
2011-07-14 00:59:38 +02:00
def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
ARM: Add patterns for dbg llvm-svn: 216451
2014-08-26 14:47:26 +02:00
[(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> {
Add a FIXME. The ADR instruction is a bit odd. llvm-svn: 116437
2010-10-13 23:32:30 +02:00
bits<4> opt;
let Inst{27-4} = 0b001100100000111100001111;
let Inst{3-0} = opt;
Added NOP, DBG, SVC to the instruction table for disassembly purpose. llvm-svn: 95784
2010-02-10 19:02:25 +01:00
}
ARM: implement support for the UDF mnemonic The UDF instruction is a reserved undefined instruction space. The assembler mnemonic was introduced with ARM ARM rev C.a. The instruction is not predicated and the immediate constant is ignored by the CPU. Add support for the three encodings for this instruction. The changes to the invalid instruction test is due to the fact that the invalid instructions actually overlap with the undefined instruction. Introduction of the new instruction results in a partial decode as an undefined sequence. Drop the tests as they are invalid instruction patterns anyways. llvm-svn: 208751
2014-05-14 05:47:39 +02:00
// A8.8.247 UDF - Undefined (Encoding A1)
def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary,
ARM: introduce llvm.arm.undefined intrinsic This intrinsic permits the emission of platform specific undefined sequences. ARM has reserved the 0xde opcode which takes a single integer parameter (ignored by the CPU). This permits the operating system to implement custom behaviour on this trap. The llvm.arm.undefined intrinsic is meant to provide a means for generating the target specific behaviour from the frontend. This is particularly useful for Windows on ARM which has made use of a series of these special opcodes. llvm-svn: 209390
2014-05-22 06:46:46 +02:00
"udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> {
ARM: implement support for the UDF mnemonic The UDF instruction is a reserved undefined instruction space. The assembler mnemonic was introduced with ARM ARM rev C.a. The instruction is not predicated and the immediate constant is ignored by the CPU. Add support for the three encodings for this instruction. The changes to the invalid instruction test is due to the fact that the invalid instructions actually overlap with the undefined instruction. Introduction of the new instruction results in a partial decode as an undefined sequence. Drop the tests as they are invalid instruction patterns anyways. llvm-svn: 208751
2014-05-14 05:47:39 +02:00
bits<16> imm16;
let Inst{31-28} = 0b1110; // AL
let Inst{27-25} = 0b011;
let Inst{24-20} = 0b11111;
let Inst{19-8} = imm16{15-4};
let Inst{7-4} = 0b1111;
let Inst{3-0} = imm16{3-0};
}
Add a special ARM trap encoding for NaCl. More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html Patch by JF Bastien llvm-svn: 173943
2013-01-30 17:30:19 +01:00
/*
* A5.4 Permanently UNDEFINED instructions.
*
* For most targets use UDF #65006, for which the OS will generate SIGTRAP.
* Other UDF encodings generate SIGILL.
*
* NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
* Encoding A1:
* 1110 0111 1111 iiii iiii iiii 1111 iiii
* Encoding T1:
* 1101 1110 iiii iiii
* It uses the following encoding:
* 1110 0111 1111 1110 1101 1110 1111 0000
* - In ARM: UDF #60896;
* - In Thumb: UDF #254 followed by a branch-to-self.
*/
let isBarrier = 1, isTerminator = 1 in
def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
"trap", [(trap)]>,
Requires<[IsARM,UseNaClTrap]> {
let Inst = 0xe7fedef0;
}
Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction. llvm-svn: 103459
2010-05-11 09:26:32 +02:00
let isBarrier = 1, isTerminator = 1 in
Trailing whitespace. llvm-svn: 117188
2010-10-23 01:48:29 +02:00
def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't (yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the opcode directly. On Darwin, however, we do want the mnemonic for more readable assembly code and better disassembly. Adjust the .td file to use the 'trap' mnemonic and handle using the binutils workaround in the assembly printer. Also tweak the formatting of the opcode values to make them consistent between the MC printer and the old printer. llvm-svn: 114679
2010-09-23 20:05:37 +02:00
"trap", [(trap)]>,
Add a special ARM trap encoding for NaCl. More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html Patch by JF Bastien llvm-svn: 173943
2013-01-30 17:30:19 +01:00
Requires<[IsARM,DontUseNaClTrap]> {
Add encoding for ARM "trap" instruction. llvm-svn: 119938
2010-11-21 12:05:29 +01:00
let Inst = 0xe7ffdefe;
Add pseudo instruction TRAP for disassembly, which is encoded according to A5-21 as the "Permanently UNDEFINED" instruction. llvm-svn: 95873
2010-02-11 18:14:31 +01:00
}
ARM: Use BKPT instead of TRAP to implement llvm.debugtrap. The BKPT instruction is specified to cause a software breakpoint, and at least on Linux results in a SIGTRAP. This makes it more suitable for implementing debugtrap than TRAP (aka UDF #254), which is specified to cause an undefined instruction exception and results in a SIGILL on Linux. Moreover, BKPT is not marked as a terminator, which is not only consistent with the IR instruction but allows the analyzeBlock function to correctly analyze a basic block containing the instruction, which fixes an assertion failure in the machine block placement pass previously triggered by the included test case. Because BKPT is only supported starting with ARMv5T, we continue to use UDF #254 when targeting v4T. Differential Revision: https://reviews.llvm.org/D53614 llvm-svn: 345171
2018-10-24 20:10:38 +02:00
def : Pat<(debugtrap), (BKPT 0)>, Requires<[IsARM, HasV5T]>;
def : Pat<(debugtrap), (UDF 254)>, Requires<[IsARM, NoV5T]>;
- Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm. - Consolidate instruction formats. - Other clean up. llvm-svn: 58808
2008-11-06 18:48:05 +01:00
// Address computation and loads and stores in PIC mode.
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. llvm-svn: 37643
2007-06-19 03:26:51 +02:00
let isNotDuplicable = 1 in {
Parameterize ARMPseudoInst size property. llvm-svn: 120353
2010-11-30 00:48:41 +01:00
def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
4, IIC_iALUr,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
[(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
Sched<[WriteALU, ReadALU]>;
Add some patterns for PIC PC-relative loads and stores. llvm-svn: 37269
2007-05-22 00:14:33 +02:00
Only mark instructions that load a single value without extension as isSimpleLoad = 1. llvm-svn: 45727
2008-01-08 00:56:57 +01:00
let AddedComplexity = 10 in {
Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not just pretend to be. llvm-svn: 119602
2010-11-18 02:15:56 +01:00
def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
4, IIC_iLoad_r,
Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not just pretend to be. llvm-svn: 119602
2010-11-18 02:15:56 +01:00
[(set GPR:$dst, (load addrmodepc:$addr))]>;
initial support for branches llvm-svn: 29854
2006-08-24 15:45:55 +02:00
Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not just pretend to be. llvm-svn: 119602
2010-11-18 02:15:56 +01:00
def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
4, IIC_iLoad_bh_r,
Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not just pretend to be. llvm-svn: 119602
2010-11-18 02:15:56 +01:00
[(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
Add some patterns for PIC PC-relative loads and stores. llvm-svn: 37269
2007-05-22 00:14:33 +02:00
Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not just pretend to be. llvm-svn: 119602
2010-11-18 02:15:56 +01:00
def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
4, IIC_iLoad_bh_r,
Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not just pretend to be. llvm-svn: 119602
2010-11-18 02:15:56 +01:00
[(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
Add some patterns for PIC PC-relative loads and stores. llvm-svn: 37269
2007-05-22 00:14:33 +02:00
Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not just pretend to be. llvm-svn: 119602
2010-11-18 02:15:56 +01:00
def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
4, IIC_iLoad_bh_r,
Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not just pretend to be. llvm-svn: 119602
2010-11-18 02:15:56 +01:00
[(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
Add some patterns for PIC PC-relative loads and stores. llvm-svn: 37269
2007-05-22 00:14:33 +02:00
Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not just pretend to be. llvm-svn: 119602
2010-11-18 02:15:56 +01:00
def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
4, IIC_iLoad_bh_r,
Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not just pretend to be. llvm-svn: 119602
2010-11-18 02:15:56 +01:00
[(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
Add some patterns for PIC PC-relative loads and stores. llvm-svn: 37269
2007-05-22 00:14:33 +02:00
}
remove explicit isStore flags that are now inferrable. llvm-svn: 45653
2008-01-06 06:55:01 +01:00
let AddedComplexity = 10 in {
Refactor PICSTR* instructions to really be pseudos. Nuke dead classes. llvm-svn: 119841
2010-11-19 22:14:02 +01:00
def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
Add some patterns for PIC PC-relative loads and stores. llvm-svn: 37269
2007-05-22 00:14:33 +02:00
Refactor PICSTR* instructions to really be pseudos. Nuke dead classes. llvm-svn: 119841
2010-11-19 22:14:02 +01:00
def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
80-col. llvm-svn: 123505
2011-01-15 01:25:09 +01:00
addrmodepc:$addr)]>;
Add some patterns for PIC PC-relative loads and stores. llvm-svn: 37269
2007-05-22 00:14:33 +02:00
Refactor PICSTR* instructions to really be pseudos. Nuke dead classes. llvm-svn: 119841
2010-11-19 22:14:02 +01:00
def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
Add some patterns for PIC PC-relative loads and stores. llvm-svn: 37269
2007-05-22 00:14:33 +02:00
}
- Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm. - Consolidate instruction formats. - Other clean up. llvm-svn: 58808
2008-11-06 18:48:05 +01:00
} // isNotDuplicable = 1
Add some patterns for PIC PC-relative loads and stores. llvm-svn: 37269
2007-05-22 00:14:33 +02:00
Minor reorg. llvm-svn: 73948
2009-06-23 07:25:29 +02:00
// LEApcrel - Load a pc-relative address into a register without offending the
// assembler.
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 01:46:26 +01:00
let hasSideEffects = 0, isReMaterializable = 1 in
Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR instruction at MC lowering. Add binary encoding information for the ADR, including fixup data for the label operand. llvm-svn: 120594
2010-12-01 20:47:31 +01:00
// The 'adr' mnemonic encodes differently if the label is before or after
Add support for binary encoding of ARM 'adr' instructions referencing constant pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291. llvm-svn: 120635
2010-12-02 01:28:45 +01:00
// the instruction. The {24-21} opcode bits are set by the fixup, as we don't
// know until then which form of the instruction will be used.
ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled. Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to the more generic ADDri/SUBri instructions, and add a test case for that. llvm-svn: 128234
2011-03-24 21:42:48 +01:00
def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 07:01:06 +02:00
MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
Sched<[WriteALU, ReadALU]> {
Clean up LEApcrel instuction(s) a bit. It's not really a Pseudo, so don't mark it as such. Add some encoding information. llvm-svn: 119588
2010-11-18 00:33:14 +01:00
bits<4> Rd;
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. llvm-svn: 138635
2011-08-26 20:09:22 +02:00
bits<14> label;
Clean up LEApcrel instuction(s) a bit. It's not really a Pseudo, so don't mark it as such. Add some encoding information. llvm-svn: 119588
2010-11-18 00:33:14 +01:00
let Inst{27-25} = 0b001;
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. llvm-svn: 138635
2011-08-26 20:09:22 +02:00
let Inst{24} = 0;
let Inst{23-22} = label{13-12};
let Inst{21} = 0;
Clean up LEApcrel instuction(s) a bit. It's not really a Pseudo, so don't mark it as such. Add some encoding information. llvm-svn: 119588
2010-11-18 00:33:14 +01:00
let Inst{20} = 0;
let Inst{19-16} = 0b1111;
let Inst{15-12} = Rd;
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. llvm-svn: 138635
2011-08-26 20:09:22 +02:00
let Inst{11-0} = label{11-0};
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan. llvm-svn: 74972
2009-07-08 01:40:25 +02:00
}
Explicitly mark LEApcrel pseudos with hasSideEffects. It's not clear that they should be marked as such, but tbb formation fails if t2LEApcrelJT is hoisted of of a loop. This doesn't change the flags on these instructions, UnmodeledSideEffects was already inferred from the missing pattern. llvm-svn: 162603
2012-08-24 23:44:11 +02:00
Revert "[ARM] Mark LEApcrel instructions as isAsCheapAsAMove" Revert "[ARM] Mark LEApcrel as not having side effects" This reverts commit r303054 and r303053, as they broke the ARM self-hosting buildbots: http://lab.llvm.org:8011/builders/clang-cmake-thumbv7-a15-full-sh/builds/1550 http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15-selfhost-neon/builds/1349 http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15-selfhost/builds/1845 Offline investigation on course. llvm-svn: 303193
2017-05-16 19:59:07 +02:00
let hasSideEffects = 1 in {
Add support for binary encoding of ARM 'adr' instructions referencing constant pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291. llvm-svn: 120635
2010-12-02 01:28:45 +01:00
def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR instruction at MC lowering. Add binary encoding information for the ADR, including fixup data for the label operand. llvm-svn: 120594
2010-12-01 20:47:31 +01:00
def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
ARM: remove custom jump table UID We were creating and propagating two separate indices for each jump table (from back in the mists of time). However, the generic index used by other backends is sufficient to emit a unique symbol so this was unneeded. llvm-svn: 237294
2015-05-13 22:28:38 +02:00
(ins i32imm:$label, pred:$p),
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
Revert "[ARM] Mark LEApcrel instructions as isAsCheapAsAMove" Revert "[ARM] Mark LEApcrel as not having side effects" This reverts commit r303054 and r303053, as they broke the ARM self-hosting buildbots: http://lab.llvm.org:8011/builders/clang-cmake-thumbv7-a15-full-sh/builds/1550 http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15-selfhost-neon/builds/1349 http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15-selfhost/builds/1845 Offline investigation on course. llvm-svn: 303193
2017-05-16 19:59:07 +02:00
}
Minor reorg. llvm-svn: 73948
2009-06-23 07:25:29 +02:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
//===----------------------------------------------------------------------===//
// Control Flow Instructions.
//
create a generic bcond instruction that has a conditional code argument llvm-svn: 29856
2006-08-24 18:13:15 +02:00
Initial bits of ARMv4-only support. Patch by John Tytgat! llvm-svn: 97886
2010-03-06 20:39:36 +01:00
let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
// ARMV4T and above
Remove trailing whitespace llvm-svn: 96388
2010-02-16 22:07:46 +01:00
def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
Initial bits of ARMv4-only support. Patch by John Tytgat! llvm-svn: 97886
2010-03-06 20:39:36 +01:00
"bx", "\tlr", [(ARMretflag)]>,
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
Simplify some ARM encoding information. llvm-svn: 116440
2010-10-13 23:48:54 +02:00
let Inst{27-0} = 0b0001001011111111111100011110;
Initial bits of ARMv4-only support. Patch by John Tytgat! llvm-svn: 97886
2010-03-06 20:39:36 +01:00
}
// ARMV4 only
Trailing whitespace. llvm-svn: 117188
2010-10-23 01:48:29 +02:00
def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
Initial bits of ARMv4-only support. Patch by John Tytgat! llvm-svn: 97886
2010-03-06 20:39:36 +01:00
"mov", "\tpc, lr", [(ARMretflag)]>,
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
Simplify some ARM encoding information. llvm-svn: 116440
2010-10-13 23:48:54 +02:00
let Inst{27-0} = 0b0001101000001111000000001110;
Initial bits of ARMv4-only support. Patch by John Tytgat! llvm-svn: 97886
2010-03-06 20:39:36 +01:00
}
ARM: support interrupt attribute This function-attribute modifies the callee-saved register list and function epilogue (specifically the return instruction) so that a routine is suitable for use as an interrupt-handler of the specified type without disrupting user-mode applications. rdar://problem/14207019 llvm-svn: 191766
2013-10-01 16:33:28 +02:00
// Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
// the user-space one).
def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
4, IIC_Br,
[(ARMintretflag imm:$offset)]>;
Fix addrmode1 instruction encodings; fix bx_ret encoding. llvm-svn: 56277
2008-09-17 09:53:38 +02:00
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Add an indirect branch pattern for ARM. Testcase will be coming soon. llvm-svn: 85355
2009-10-28 01:37:03 +01:00
// Indirect branches
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
Initial bits of ARMv4-only support. Patch by John Tytgat! llvm-svn: 97886
2010-03-06 20:39:36 +01:00
// ARMV4T and above
Rename BX/BRIND/etc patterns to clarify which is actually the BX instruction and which are pseudos. llvm-svn: 120366
2010-11-30 01:24:05 +01:00
def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
Initial bits of ARMv4-only support. Patch by John Tytgat! llvm-svn: 97886
2010-03-06 20:39:36 +01:00
[(brind GPR:$dst)]>,
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
More binary encoding stuff, taking advantage of the new "by name" operand matching in tblgen to do the predicate operand. llvm-svn: 116213
2010-10-11 20:51:51 +02:00
bits<4> dst;
Simplify some ARM encoding information. llvm-svn: 116440
2010-10-13 23:48:54 +02:00
let Inst{31-4} = 0b1110000100101111111111110001;
Encoding information for ARM conditional move instructions. llvm-svn: 117687
2010-10-29 21:28:17 +02:00
let Inst{3-0} = dst;
Add an indirect branch pattern for ARM. Testcase will be coming soon. llvm-svn: 85355
2009-10-28 01:37:03 +01:00
}
Initial bits of ARMv4-only support. Patch by John Tytgat! llvm-svn: 97886
2010-03-06 20:39:36 +01:00
Fix encoding of predicate bits on ARM BX_pred. llvm-svn: 135076
2011-07-13 22:21:31 +02:00
def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
"bx", "\t$dst", [/* pattern left blank */]>,
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and modified ARMDisassemblerCore.cpp a little bit. llvm-svn: 131859
2011-05-22 19:51:04 +02:00
bits<4> dst;
let Inst{27-4} = 0b000100101111111111110001;
let Inst{3-0} = dst;
}
Add an indirect branch pattern for ARM. Testcase will be coming soon. llvm-svn: 85355
2009-10-28 01:37:03 +01:00
}
Switch ARM target to register masks. I'll let the buildbots determine the compile time improvements from this change, but 464.h264ref has 5% faster codegen at -O2. This patch does cause some assembly changes. Branch folding can make different decisions about calls with dead return values. CriticalAntiDepBreaker may choose different registers because its liveness tracking is affected. MachineCopyPropagation may sometimes leave a dead copy behind. llvm-svn: 151331
2012-02-24 02:19:29 +01:00
// SP is marked as a use to prevent stack-pointer assignments that appear
// immediately before calls from potentially appearing dead.
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one. llvm-svn: 78827
2009-08-12 20:31:53 +02:00
let isCall = 1,
Add FIXME. llvm-svn: 127516
2011-03-12 01:51:00 +01:00
// FIXME: Do we really need a non-predicated version? If so, it should
// at least be a pseudo instruction expanding to the predicated version
// at MC lowering time.
Switch ARM target to register masks. I'll let the buildbots determine the compile time improvements from this change, but 464.h264ref has 5% faster codegen at -O2. This patch does cause some assembly changes. Branch folding can make different decisions about calls with dead return values. CriticalAntiDepBreaker may choose different registers because its liveness tracking is affected. MachineCopyPropagation may sometimes leave a dead copy behind. llvm-svn: 151331
2012-02-24 02:19:29 +01:00
Defs = [LR], Uses = [SP] in {
ARM: validate immediate branch targets in AsmParser. Immediate branch targets aren't commonly used, but if they are we should make sure they can actually be encoded. This means they must be divisible by 2 when targeting Thumb mode, and by 4 when targeting ARM mode. Also do a little naming cleanup while I was changing everything around anyway. llvm-svn: 275116
2016-07-12 00:29:37 +02:00
def BL : ABXI<0b1011, (outs), (ins arm_bl_target:$func),
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT). llvm-svn: 115845
2010-10-06 23:36:43 +02:00
IIC_Br, "bl\t$func",
Make sure Thumb2 uses the right call instructions. llvm-svn: 77507
2009-07-29 23:26:42 +02:00
[(ARMcall tglobaladdr:$func)]>,
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
Requires<[IsARM]>, Sched<[WriteBrL]> {
Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between BL_pred and BLr9_pred. llvm-svn: 85297
2009-10-27 21:45:15 +01:00
let Inst{31-28} = 0b1110;
ARM fixup encoding for direct call instructions (BL). llvm-svn: 118829
2010-11-11 21:05:40 +01:00
bits<24> func;
let Inst{23-0} = func;
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. llvm-svn: 138675
2011-08-27 01:32:08 +02:00
let DecoderMethod = "DecodeBranchImmInstruction";
Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between BL_pred and BLr9_pred. llvm-svn: 85297
2009-10-27 21:45:15 +01:00
}
Allow predicated immediate ARM to ARM calls. llvm-svn: 37659
2007-06-19 23:05:09 +02:00
ARM: validate immediate branch targets in AsmParser. Immediate branch targets aren't commonly used, but if they are we should make sure they can actually be encoded. This means they must be divisible by 2 when targeting Thumb mode, and by 4 when targeting ARM mode. Also do a little naming cleanup while I was changing everything around anyway. llvm-svn: 275116
2016-07-12 00:29:37 +02:00
def BL_pred : ABI<0b1011, (outs), (ins arm_bl_target:$func),
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT). llvm-svn: 115845
2010-10-06 23:36:43 +02:00
IIC_Br, "bl", "\t$func",
Make sure Thumb2 uses the right call instructions. llvm-svn: 77507
2009-07-29 23:26:42 +02:00
[(ARMcall_pred tglobaladdr:$func)]>,
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
Requires<[IsARM]>, Sched<[WriteBrL]> {
ARM fixup encoding for direct call instructions (BL). llvm-svn: 118829
2010-11-11 21:05:40 +01:00
bits<24> func;
let Inst{23-0} = func;
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. llvm-svn: 138675
2011-08-27 01:32:08 +02:00
let DecoderMethod = "DecodeBranchImmInstruction";
ARM fixup encoding for direct call instructions (BL). llvm-svn: 118829
2010-11-11 21:05:40 +01:00
}
Allow predicated immediate ARM to ARM calls. llvm-svn: 37659
2007-06-19 23:05:09 +02:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// ARMv5T and above
Remove variable_ops from ARM call instructions. Function argument registers are added to the call SDNode, but InstrEmitter now knows how to make those operands implicit, and the call instruction doesn't have to be variadic. Explicit register operands should only be those that are encoded in the instruction, implicit register operands are for extra dependencies like call argument and return values. llvm-svn: 160188
2012-07-13 22:27:00 +02:00
def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
Change ARM asm strings to separate opcode from operands with a tab instead of a space. llvm-svn: 85178
2009-10-27 00:45:59 +01:00
IIC_Br, "blx\t$func",
Make sure Thumb2 uses the right call instructions. llvm-svn: 77507
2009-07-29 23:26:42 +02:00
[(ARMcall GPR:$func)]>,
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
More binary encoding stuff, taking advantage of the new "by name" operand matching in tblgen to do the predicate operand. llvm-svn: 116213
2010-10-11 20:51:51 +02:00
bits<4> func;
Minor cleanups to a few llvm_unreachable() calls. llvm-svn: 119767
2010-11-19 01:27:09 +01:00
let Inst{31-4} = 0b1110000100101111111111110011;
pr9367: Add missing predicated BLX instructions. Patch by Jyun-Yan You, with some minor adjustments and a testcase from me. llvm-svn: 126915
2011-03-03 02:41:01 +01:00
let Inst{3-0} = func;
}
Remove variable_ops from ARM call instructions. Function argument registers are added to the call SDNode, but InstrEmitter now knows how to make those operands implicit, and the call instruction doesn't have to be variadic. Explicit register operands should only be those that are encoded in the instruction, implicit register operands are for extra dependencies like call argument and return values. llvm-svn: 160188
2012-07-13 22:27:00 +02:00
def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
pr9367: Add missing predicated BLX instructions. Patch by Jyun-Yan You, with some minor adjustments and a testcase from me. llvm-svn: 126915
2011-03-03 02:41:01 +01:00
IIC_Br, "blx", "\t$func",
[(ARMcall_pred GPR:$func)]>,
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
pr9367: Add missing predicated BLX instructions. Patch by Jyun-Yan You, with some minor adjustments and a testcase from me. llvm-svn: 126915
2011-03-03 02:41:01 +01:00
bits<4> func;
let Inst{27-4} = 0b000100101111111111110011;
let Inst{3-0} = func;
Fix addrmode1 instruction encodings; fix bx_ret encoding. llvm-svn: 56277
2008-09-17 09:53:38 +02:00
}
1. In Thumb mode, select tBx instead of ARM variants. 2. BX does not "use" the link register, it defines it. 3. Fix a couple more places in thumb td file that still uses pre-UAL syntax. llvm-svn: 75585
2009-07-14 03:49:27 +02:00
// ARMv4T
Fix pr6111: Avoid using the LR register for the target address of an indirect branch in ARM v4 code, since it gets clobbered by the return address before it is used. Instead of adding a new register class containing all the GPRs except LR, just use the existing tGPR class. llvm-svn: 96360
2010-02-16 18:24:15 +01:00
// Note: Restrict $func to the tGPR regclass to prevent it being in LR.
Remove variable_ops from ARM call instructions. Function argument registers are added to the call SDNode, but InstrEmitter now knows how to make those operands implicit, and the call instruction doesn't have to be variadic. Explicit register operands should only be those that are encoded in the instruction, implicit register operands are for extra dependencies like call argument and return values. llvm-svn: 160188
2012-07-13 22:27:00 +02:00
def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
Initial bits of ARMv4-only support. Patch by John Tytgat! llvm-svn: 97886
2010-03-06 20:39:36 +01:00
// ARMv4
Remove variable_ops from ARM call instructions. Function argument registers are added to the call SDNode, but InstrEmitter now knows how to make those operands implicit, and the call instruction doesn't have to be variadic. Explicit register operands should only be those that are encoded in the instruction, implicit register operands are for extra dependencies like call argument and return values. llvm-svn: 160188
2012-07-13 22:27:00 +02:00
def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call. llvm-svn: 151645
2012-02-28 19:51:51 +01:00
// mov lr, pc; b if callee is marked noreturn to avoid confusing the
// return stack predictor.
ARM: validate immediate branch targets in AsmParser. Immediate branch targets aren't commonly used, but if they are we should make sure they can actually be encoded. This means they must be divisible by 2 when targeting Thumb mode, and by 4 when targeting ARM mode. Also do a little naming cleanup while I was changing everything around anyway. llvm-svn: 275116
2016-07-12 00:29:37 +02:00
def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins arm_bl_target:$func),
Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call. llvm-svn: 151645
2012-02-28 19:51:51 +01:00
8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
Requires<[IsARM]>, Sched<[WriteBr]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
}
added a skeleton of the ARM backend llvm-svn: 28301
2006-05-15 00:18:28 +02:00
Shuffle productions around a bit. No functional change. llvm-svn: 134714
2011-07-08 20:26:27 +02:00
let isBranch = 1, isTerminator = 1 in {
// FIXME: should be able to write a pattern for ARMBrcond, but can't use
// a two-value operand where a dag node expects two operands. :(
ARM: validate immediate branch targets in AsmParser. Immediate branch targets aren't commonly used, but if they are we should make sure they can actually be encoded. This means they must be divisible by 2 when targeting Thumb mode, and by 4 when targeting ARM mode. Also do a little naming cleanup while I was changing everything around anyway. llvm-svn: 275116
2016-07-12 00:29:37 +02:00
def Bcc : ABI<0b1010, (outs), (ins arm_br_target:$target),
Shuffle productions around a bit. No functional change. llvm-svn: 134714
2011-07-08 20:26:27 +02:00
IIC_Br, "b", "\t$target",
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
[/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
Sched<[WriteBr]> {
Shuffle productions around a bit. No functional change. llvm-svn: 134714
2011-07-08 20:26:27 +02:00
bits<24> target;
let Inst{23-0} = target;
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeBranchImmInstruction";
Shuffle productions around a bit. No functional change. llvm-svn: 134714
2011-07-08 20:26:27 +02:00
}
let isBarrier = 1 in {
// B is "predicable" since it's just a Bcc with an 'always' condition.
let isPredicable = 1 in
// FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
// should be sufficient.
// FIXME: Is B really a Barrier? That doesn't seem right.
ARM: validate immediate branch targets in AsmParser. Immediate branch targets aren't commonly used, but if they are we should make sure they can actually be encoded. This means they must be divisible by 2 when targeting Thumb mode, and by 4 when targeting ARM mode. Also do a little naming cleanup while I was changing everything around anyway. llvm-svn: 275116
2016-07-12 00:29:37 +02:00
def B : ARMPseudoExpand<(outs), (ins arm_br_target:$target), 4, IIC_Br,
[(br bb:$target)], (Bcc arm_br_target:$target,
(ops 14, zero_reg))>,
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
Sched<[WriteBr]>;
Shuffle productions around a bit. No functional change. llvm-svn: 134714
2011-07-08 20:26:27 +02:00
ARM: recommit r237590: allow jump tables to be placed as constant islands. The original version didn't properly account for the base register being modified before the final jump, so caused miscompilations in Chromium and LLVM. I've fixed this and tested with an LLVM self-host (I don't have the means to build & test Chromium). The general idea remains the same: in pathological cases jump tables can be too far away from the instructions referencing them (like other constants) so they need to be movable. Should fix PR23627. llvm-svn: 238680
2015-05-31 21:22:07 +02:00
let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in {
Shuffle productions around a bit. No functional change. llvm-svn: 134714
2011-07-08 20:26:27 +02:00
def BR_JTr : ARMPseudoInst<(outs),
ARM: remove custom jump table UID We were creating and propagating two separate indices for each jump table (from back in the mists of time). However, the generic index used by other backends is sufficient to emit a unique symbol so this was unneeded. llvm-svn: 237294
2015-05-13 22:28:38 +02:00
(ins GPR:$target, i32imm:$jt),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
0, IIC_Br,
ARM: remove custom jump table UID We were creating and propagating two separate indices for each jump table (from back in the mists of time). However, the generic index used by other backends is sufficient to emit a unique symbol so this was unneeded. llvm-svn: 237294
2015-05-13 22:28:38 +02:00
[(ARMbrjt GPR:$target, tjumptable:$jt)]>,
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
Sched<[WriteBr]>;
[ARM] Split Arm jump table branch into i12 and rs suffixed versions This is a refactoring/cleanup of Arm `addrmode2` operand class. The patch removes it completely. Differential Revision: https://reviews.llvm.org/D39832 llvm-svn: 318291
2017-11-15 13:02:55 +01:00
def BR_JTm_i12 : ARMPseudoInst<(outs),
(ins addrmode_imm12:$target, i32imm:$jt),
0, IIC_Br,
[(ARMbrjt (i32 (load addrmode_imm12:$target)),
tjumptable:$jt)]>, Sched<[WriteBrTbl]>;
def BR_JTm_rs : ARMPseudoInst<(outs),
(ins ldst_so_reg:$target, i32imm:$jt),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
0, IIC_Br,
[ARM] Split Arm jump table branch into i12 and rs suffixed versions This is a refactoring/cleanup of Arm `addrmode2` operand class. The patch removes it completely. Differential Revision: https://reviews.llvm.org/D39832 llvm-svn: 318291
2017-11-15 13:02:55 +01:00
[(ARMbrjt (i32 (load ldst_so_reg:$target)),
ARM: remove custom jump table UID We were creating and propagating two separate indices for each jump table (from back in the mists of time). However, the generic index used by other backends is sufficient to emit a unique symbol so this was unneeded. llvm-svn: 237294
2015-05-13 22:28:38 +02:00
tjumptable:$jt)]>, Sched<[WriteBrTbl]>;
Shuffle productions around a bit. No functional change. llvm-svn: 134714
2011-07-08 20:26:27 +02:00
def BR_JTadd : ARMPseudoInst<(outs),
ARM: remove custom jump table UID We were creating and propagating two separate indices for each jump table (from back in the mists of time). However, the generic index used by other backends is sufficient to emit a unique symbol so this was unneeded. llvm-svn: 237294
2015-05-13 22:28:38 +02:00
(ins GPR:$target, GPR:$idx, i32imm:$jt),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
0, IIC_Br,
ARM: remove custom jump table UID We were creating and propagating two separate indices for each jump table (from back in the mists of time). However, the generic index used by other backends is sufficient to emit a unique symbol so this was unneeded. llvm-svn: 237294
2015-05-13 22:28:38 +02:00
[(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>,
Sched<[WriteBrTbl]>;
Shuffle productions around a bit. No functional change. llvm-svn: 134714
2011-07-08 20:26:27 +02:00
} // isNotDuplicable = 1, isIndirectBranch = 1
} // isBarrier = 1
}
ARM assembly parsing and encoding for BLX (immediate). Add parsing support for BLX (immediate). Since the register operand version is predicated and the label operand version is not, we have to use some special handling to get the operand list right for matching. llvm-svn: 136406
2011-07-28 23:57:55 +02:00
// BLX (immediate)
ARM: validate immediate branch targets in AsmParser. Immediate branch targets aren't commonly used, but if they are we should make sure they can actually be encoded. This means they must be divisible by 2 when targeting Thumb mode, and by 4 when targeting ARM mode. Also do a little naming cleanup while I was changing everything around anyway. llvm-svn: 275116
2016-07-12 00:29:37 +02:00
def BLXi : AXI<(outs), (ins arm_blx_target:$target), BrMiscFrm, NoItinerary,
ARM assembly parsing and encoding for BLX (immediate). Add parsing support for BLX (immediate). Since the register operand version is predicated and the label operand version is not, we have to use some special handling to get the operand list right for matching. llvm-svn: 136406
2011-07-28 23:57:55 +02:00
"blx\t$target", []>,
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
Shuffle productions around a bit. No functional change. llvm-svn: 134714
2011-07-08 20:26:27 +02:00
let Inst{31-25} = 0b1111101;
bits<25> target;
let Inst{23-0} = target{24-1};
let Inst{24} = target{0};
ARM: mark branch-like instructions with correct flags. There's probably no way to test BXJ, but if the compiler ever did emit it during CodeGen it would have to be a block terminator so "isBranch" is appropriate. BLX is more tricky. Clearly a call, but it affects surprisingly little. rdar://18719544 llvm-svn: 236140
2015-04-29 21:16:38 +02:00
let isCall = 1;
Shuffle productions around a bit. No functional change. llvm-svn: 134714
2011-07-08 20:26:27 +02:00
}
Fix encoding for ARM BXJ instruction. llvm-svn: 135077
2011-07-13 22:25:01 +02:00
// Branch and Exchange Jazelle
Shuffle productions around a bit. No functional change. llvm-svn: 134714
2011-07-08 20:26:27 +02:00
def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
[/* pattern left blank */]>, Sched<[WriteBr]> {
Fix encoding for ARM BXJ instruction. llvm-svn: 135077
2011-07-13 22:25:01 +02:00
bits<4> func;
Shuffle productions around a bit. No functional change. llvm-svn: 134714
2011-07-08 20:26:27 +02:00
let Inst{23-20} = 0b0010;
Fix encoding for ARM BXJ instruction. llvm-svn: 135077
2011-07-13 22:25:01 +02:00
let Inst{19-8} = 0xfff;
Shuffle productions around a bit. No functional change. llvm-svn: 134714
2011-07-08 20:26:27 +02:00
let Inst{7-4} = 0b0010;
Fix encoding for ARM BXJ instruction. llvm-svn: 135077
2011-07-13 22:25:01 +02:00
let Inst{3-0} = func;
ARM: mark branch-like instructions with correct flags. There's probably no way to test BXJ, but if the compiler ever did emit it during CodeGen it would have to be a block terminator so "isBranch" is appropriate. BLX is more tricky. Clearly a call, but it affects surprisingly little. rdar://18719544 llvm-svn: 236140
2015-04-29 21:16:38 +02:00
let isBranch = 1;
Shuffle productions around a bit. No functional change. llvm-svn: 134714
2011-07-08 20:26:27 +02:00
}
Early implementation of tail call for ARM. A temporary flag -arm-tail-calls defaults to off, so there is no functional change by default. Intrepid users may try this; simple cases work but there are bugs. llvm-svn: 105413
2010-06-03 23:09:53 +02:00
// Tail calls.
Eliminate iOS-specific tail call instructions. After register masks were introdruced to represent the call clobbers, it is no longer necessary to have duplicate instruction for iOS. llvm-svn: 154209
2012-04-06 23:17:42 +02:00
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
Sched<[WriteBr]>;
Indentation and remove dead code. llvm-svn: 106362
2010-06-19 02:11:54 +02:00
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
Sched<[WriteBr]>;
Indentation and remove dead code. llvm-svn: 106362
2010-06-19 02:11:54 +02:00
ARM: validate immediate branch targets in AsmParser. Immediate branch targets aren't commonly used, but if they are we should make sure they can actually be encoded. This means they must be divisible by 2 when targeting Thumb mode, and by 4 when targeting ARM mode. Also do a little naming cleanup while I was changing everything around anyway. llvm-svn: 275116
2016-07-12 00:29:37 +02:00
def TAILJMPd : ARMPseudoExpand<(outs), (ins arm_br_target:$dst),
Eliminate iOS-specific tail call instructions. After register masks were introdruced to represent the call clobbers, it is no longer necessary to have duplicate instruction for iOS. llvm-svn: 154209
2012-04-06 23:17:42 +02:00
4, IIC_Br, [],
ARM: validate immediate branch targets in AsmParser. Immediate branch targets aren't commonly used, but if they are we should make sure they can actually be encoded. This means they must be divisible by 2 when targeting Thumb mode, and by 4 when targeting ARM mode. Also do a little naming cleanup while I was changing everything around anyway. llvm-svn: 275116
2016-07-12 00:29:37 +02:00
(Bcc arm_br_target:$dst, (ops 14, zero_reg))>,
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
Requires<[IsARM]>, Sched<[WriteBr]>;
Changes to ARM tail calls, mostly cosmetic. Add explicit testcases for tail calls within the same module. Duplicate some code to humor those who think .w doesn't apply on ARM. Leave this disabled on Thumb1, and add some comments explaining why it's hard and won't gain much. llvm-svn: 107851
2010-07-08 03:18:23 +02:00
Remove variable_ops from ARM call instructions. Function argument registers are added to the call SDNode, but InstrEmitter now knows how to make those operands implicit, and the call instruction doesn't have to be variadic. Explicit register operands should only be those that are encoded in the instruction, implicit register operands are for extra dependencies like call argument and return values. llvm-svn: 160188
2012-07-13 22:27:00 +02:00
def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
Eliminate iOS-specific tail call instructions. After register masks were introdruced to represent the call clobbers, it is no longer necessary to have duplicate instruction for iOS. llvm-svn: 154209
2012-04-06 23:17:42 +02:00
4, IIC_Br, [],
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
(BX GPR:$dst)>, Sched<[WriteBr]>,
Fix ARMv4 support ARMv4 doesn't support the "BX" instruction, which has been introduced with ARMv4t. Adjust the call lowering and tail call implementation accordingly. Further changes are necessary to ensure that presence of the v4t feature is correctly set. Most importantly, the "generic" CPU for thumb-* triples should include ARMv4t, since thumb mode without thumb support would naturally be pointless. Add a couple of asserts to ensure thumb instructions are not emitted without CPU support. Differential Revision: https://reviews.llvm.org/D37030 llvm-svn: 311921
2017-08-28 22:20:47 +02:00
Requires<[IsARM, HasV4T]>;
Early implementation of tail call for ARM. A temporary flag -arm-tail-calls defaults to off, so there is no functional change by default. Intrepid users may try this; simple cases work but there are bugs. llvm-svn: 105413
2010-06-03 23:09:53 +02:00
}
Remove no-longer-true comments. These are for the assembler, also. llvm-svn: 137375
2011-08-12 00:30:30 +02:00
// Secure Monitor Call is a system instruction.
ARM assembly parsing and encoding for SMC instruction. llvm-svn: 135782
2011-07-22 20:13:31 +02:00
def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
ARM: Make "SMC" instructions conditional on new TrustZone architecture feature. These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. llvm-svn: 179171
2013-04-10 14:08:35 +02:00
[]>, Requires<[IsARM, HasTrustZone]> {
Add operand encoding bits for SMC and SVC in ARM mode. llvm-svn: 116447
2010-10-14 00:38:23 +02:00
bits<4> opt;
let Inst{23-4} = 0b01100000000000000111;
let Inst{3-0} = opt;
Add SMC (Secure Monitor Call) system instruction for disassembly only. llvm-svn: 96401
2010-02-16 22:59:54 +01:00
}
Recognize that ARM1176JZ[F]-S support TrustZone Summary: ARMv6KZ cores were set up incorrectly in ARM.td; also, the SMI mnemonic (the old name for SMC, as defined in ARMv6KZ) wasn't supported. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14154 llvm-svn: 251627
2015-10-29 14:56:19 +01:00
def : MnemonicAlias<"smi", "smc">;
Add SMC (Secure Monitor Call) system instruction for disassembly only. llvm-svn: 96401
2010-02-16 22:59:54 +01:00
ARM parsing and encoding for SVC instruction. llvm-svn: 136090
2011-07-26 18:24:27 +02:00
// Supervisor Call (Software Interrupt)
Mark Darwin call instructions as using "r7" to prevent the frame-register assignment instructions from being moved below / above calls. rdar://8690640 llvm-svn: 120339
2010-11-29 23:43:27 +01:00
let isCall = 1, Uses = [SP] in {
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
Sched<[WriteBr]> {
Add operand encoding bits for SMC and SVC in ARM mode. llvm-svn: 116447
2010-10-14 00:38:23 +02:00
bits<24> svc;
let Inst{23-0} = svc;
}
Added NOP, DBG, SVC to the instruction table for disassembly purpose. llvm-svn: 95784
2010-02-10 19:02:25 +01:00
}
ARM SRS and RFE instructions are not code-gen only. llvm-svn: 136475
2011-07-29 19:51:39 +02:00
// Store Return State
ARM SRS instruction parsing, diassembly and encoding support. Fix the instruction encoding for operands. Refactor mode to use explicit instruction definitions per FIXME to be more consistent with loads/stores. Fix disassembler accordingly. Add tests. llvm-svn: 136509
2011-07-29 22:26:09 +02:00
class SRSI<bit wb, string asm>
: XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
NoItinerary, asm, "", []> {
bits<5> mode;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
let Inst{31-28} = 0b1111;
ARM SRS instruction parsing, diassembly and encoding support. Fix the instruction encoding for operands. Refactor mode to use explicit instruction definitions per FIXME to be more consistent with loads/stores. Fix disassembler accordingly. Add tests. llvm-svn: 136509
2011-07-29 22:26:09 +02:00
let Inst{27-25} = 0b100;
let Inst{22} = 1;
let Inst{21} = wb;
let Inst{20} = 0;
let Inst{19-16} = 0b1101; // SP
let Inst{15-5} = 0b00000101000;
let Inst{4-0} = mode;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
}
ARM SRS instruction parsing, diassembly and encoding support. Fix the instruction encoding for operands. Refactor mode to use explicit instruction definitions per FIXME to be more consistent with loads/stores. Fix disassembler accordingly. Add tests. llvm-svn: 136509
2011-07-29 22:26:09 +02:00
def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
let Inst{24-23} = 0;
}
def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
let Inst{24-23} = 0;
}
def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
let Inst{24-23} = 0b10;
}
def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
let Inst{24-23} = 0b10;
}
def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
let Inst{24-23} = 0b01;
}
def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
let Inst{24-23} = 0b01;
}
def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
let Inst{24-23} = 0b11;
}
def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
let Inst{24-23} = 0b11;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
}
ARM assembly parsing and encoding for RFE instruction. Fill in the missing fixed bits and the register operand bits of the instruction encoding. Refactor the definition to make the mode explicit, which is consistent with how loads and stores are normally represented and makes parsing much easier. Add parsing aliases for pseudo-instruction variants. Update the disassembler for the new representations. Add tests for parsing and encoding. llvm-svn: 136479
2011-07-29 20:47:24 +02:00
ARM: Convenience aliases for 'srs*' instructions. Handle an implied 'sp' operand. rdar://11466783 llvm-svn: 175940
2013-02-23 01:52:09 +01:00
def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
ARM SRS and RFE instructions are not code-gen only. llvm-svn: 136475
2011-07-29 19:51:39 +02:00
// Return From Exception
ARM assembly parsing and encoding for RFE instruction. Fill in the missing fixed bits and the register operand bits of the instruction encoding. Refactor the definition to make the mode explicit, which is consistent with how loads and stores are normally represented and makes parsing much easier. Add parsing aliases for pseudo-instruction variants. Update the disassembler for the new representations. Add tests for parsing and encoding. llvm-svn: 136479
2011-07-29 20:47:24 +02:00
class RFEI<bit wb, string asm>
: XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
NoItinerary, asm, "", []> {
bits<4> Rn;
Added RFE for disassembly only. B6.1.8 RFE Return From Exception loads the PC and the CPSR from the word at the specified address and the following word respectively. llvm-svn: 96519
2010-02-17 22:39:10 +01:00
let Inst{31-28} = 0b1111;
ARM assembly parsing and encoding for RFE instruction. Fill in the missing fixed bits and the register operand bits of the instruction encoding. Refactor the definition to make the mode explicit, which is consistent with how loads and stores are normally represented and makes parsing much easier. Add parsing aliases for pseudo-instruction variants. Update the disassembler for the new representations. Add tests for parsing and encoding. llvm-svn: 136479
2011-07-29 20:47:24 +02:00
let Inst{27-25} = 0b100;
let Inst{22} = 0;
let Inst{21} = wb;
let Inst{20} = 1;
let Inst{19-16} = Rn;
let Inst{15-0} = 0xa00;
Added RFE for disassembly only. B6.1.8 RFE Return From Exception loads the PC and the CPSR from the word at the specified address and the following word respectively. llvm-svn: 96519
2010-02-17 22:39:10 +01:00
}
ARM assembly parsing and encoding for RFE instruction. Fill in the missing fixed bits and the register operand bits of the instruction encoding. Refactor the definition to make the mode explicit, which is consistent with how loads and stores are normally represented and makes parsing much easier. Add parsing aliases for pseudo-instruction variants. Update the disassembler for the new representations. Add tests for parsing and encoding. llvm-svn: 136479
2011-07-29 20:47:24 +02:00
def RFEDA : RFEI<0, "rfeda\t$Rn"> {
let Inst{24-23} = 0;
}
def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
let Inst{24-23} = 0;
}
def RFEDB : RFEI<0, "rfedb\t$Rn"> {
let Inst{24-23} = 0b10;
}
def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
let Inst{24-23} = 0b10;
}
def RFEIA : RFEI<0, "rfeia\t$Rn"> {
let Inst{24-23} = 0b01;
}
def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
let Inst{24-23} = 0b01;
}
def RFEIB : RFEI<0, "rfeib\t$Rn"> {
let Inst{24-23} = 0b11;
}
def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
let Inst{24-23} = 0b11;
Added RFE for disassembly only. B6.1.8 RFE Return From Exception loads the PC and the CPSR from the word at the specified address and the following word respectively. llvm-svn: 96519
2010-02-17 22:39:10 +01:00
}
Add ARM ERET and HVC virtualisation extension instructions. Patch by Matthew Wahab. Change-Id: Iad75f078fbaa4ecc7d7a4820ad9b3930679cbbbb llvm-svn: 222989
2014-12-01 09:33:28 +01:00
// Hypervisor Call is a system instruction
let isCall = 1 in {
def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary,
"hvc", "\t$imm", []>,
Requires<[IsARM, HasVirtualization]> {
bits<16> imm;
// Even though HVC isn't predicable, it's encoding includes a condition field.
// The instruction is undefined if the condition field is 0xf otherwise it is
// unpredictable if it isn't condition AL (0xe).
let Inst{31-28} = 0b1110;
let Unpredictable{31-28} = 0b1111;
let Inst{27-24} = 0b0001;
let Inst{23-20} = 0b0100;
let Inst{19-8} = imm{15-4};
let Inst{7-4} = 0b0111;
let Inst{3-0} = imm{3-0};
}
}
// Return from exception in Hypervisor mode.
let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>,
Requires<[IsARM, HasVirtualization]> {
let Inst{23-0} = 0b011000000000000001101110;
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
//===----------------------------------------------------------------------===//
Commit test, capitalizing store... keep it simple. llvm-svn: 142336
2011-10-18 06:44:36 +02:00
// Load / Store Instructions.
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
//
implement movri add a stub LowerFORMAL_ARGUMENTS llvm-svn: 28388
2006-05-18 23:45:49 +02:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// Load
First part of refactoring ARM addrmode2 (load/store) instructions to be more explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
2010-10-27 00:37:02 +02:00
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, load>;
Continue to tighten decoding by performing more operand validation. llvm-svn: 137340
2011-08-11 22:21:46 +02:00
defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
zextloadi8>;
defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, store>;
Continue to tighten decoding by performing more operand validation. llvm-svn: 137340
2011-08-11 22:21:46 +02:00
defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
truncstorei8>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Special LDR instructions to load from non-pc-relative constantpools. These are rematerializable. Only used for constant generation for now. llvm-svn: 35162
2007-03-19 08:20:03 +01:00
// Special LDR for loads from non-pc-relative constpools.
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 01:46:26 +01:00
let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0,
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
isReMaterializable = 1, isCodeGenOnly = 1 in
Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes. llvm-svn: 119840
2010-11-19 22:07:51 +01:00
def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
More ARM load/store indexed refactoring. Also fix an incorrect IndexMode flag for the LDRT/STRT family instructions as a side effect. llvm-svn: 118955
2010-11-13 01:35:48 +01:00
AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
[]> {
First part of refactoring ARM addrmode2 (load/store) instructions to be more explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
2010-10-27 00:37:02 +02:00
bits<4> Rt;
bits<17> addr;
let Inst{23} = addr{12}; // U (add = ('U' == 1))
let Inst{19-16} = 0b1111;
let Inst{15-12} = Rt;
let Inst{11-0} = addr{11-0}; // imm12
}
Special LDR instructions to load from non-pc-relative constantpools. These are rematerializable. Only used for constant generation for now. llvm-svn: 35162
2007-03-19 08:20:03 +01:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// Loads with zero extension
ARM LDRD binary encoding. llvm-svn: 119812
2010-11-19 19:16:46 +01:00
def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
More ARM encoding bits. LDRH now encodes properly. llvm-svn: 119529
2010-11-17 19:11:11 +01:00
IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
[(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// Loads with sign extension
ARM LDRD binary encoding. llvm-svn: 119812
2010-11-19 19:16:46 +01:00
def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
More ARM encoding bits. LDRH now encodes properly. llvm-svn: 119529
2010-11-17 19:11:11 +01:00
IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
[(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
ARM LDRD binary encoding. llvm-svn: 119812
2010-11-19 19:16:46 +01:00
def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
More ARM encoding bits. LDRH now encodes properly. llvm-svn: 119529
2010-11-17 19:11:11 +01:00
IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
[(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 01:46:26 +01:00
let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
ARM: style changes to LDRD, STRD definition Fix indentation, name registers similar to ARM ARM. No functionality change! llvm-svn: 198563
2014-01-05 17:36:37 +01:00
// Load doubleword
def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
Requires<[IsARM, HasV5TE]>;
Add ARM binary encoding information for the rest of the indexed loads. llvm-svn: 119821
2010-11-19 20:41:26 +01:00
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
[ARMv8] Add MC support for the new load/store acquire/release instructions. llvm-svn: 189388
2013-08-27 19:38:16 +02:00
def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
NoItinerary, "lda", "\t$Rt, $addr", []>;
def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
NoItinerary, "ldab", "\t$Rt, $addr", []>;
def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
NoItinerary, "ldah", "\t$Rt, $addr", []>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// Indexed loads
Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen. llvm-svn: 143675
2011-11-04 02:48:58 +01:00
multiclass AI2_ldridx<bit isByte, string opc,
InstrItinClass iii, InstrItinClass iir> {
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. llvm-svn: 138653
2011-08-26 22:43:14 +02:00
def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
ARM: Correct printing of pre-indexed operands. According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
2013-04-12 20:47:25 +02:00
(ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding. llvm-svn: 119180
2010-11-15 21:47:07 +01:00
opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. llvm-svn: 138653
2011-08-26 22:43:14 +02:00
bits<17> addr;
let Inst{25} = 0;
ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding. llvm-svn: 119180
2010-11-15 21:47:07 +01:00
let Inst{23} = addr{12};
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. llvm-svn: 138653
2011-08-26 22:43:14 +02:00
let Inst{19-16} = addr{16-13};
ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding. llvm-svn: 119180
2010-11-15 21:47:07 +01:00
let Inst{11-0} = addr{11-0};
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. llvm-svn: 138653
2011-08-26 22:43:14 +02:00
let DecoderMethod = "DecodeLDRPreImm";
}
def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen. llvm-svn: 143675
2011-11-04 02:48:58 +01:00
(ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. llvm-svn: 138653
2011-08-26 22:43:14 +02:00
opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
bits<17> addr;
let Inst{25} = 1;
let Inst{23} = addr{12};
let Inst{19-16} = addr{16-13};
let Inst{11-0} = addr{11-0};
let Inst{4} = 0;
let DecoderMethod = "DecodeLDRPreReg";
ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding. llvm-svn: 119180
2010-11-15 21:47:07 +01:00
}
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
2011-07-26 22:54:26 +02:00
def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
ARM assembly parsing and encoding for LDR instructions. Enhance support for LDR instruction assembly parsing for post-indexed addressing with immediate values. Add tests. llvm-svn: 136940
2011-08-05 01:01:30 +02:00
(ins addr_offset_none:$addr, am2offset_reg:$offset),
Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen. llvm-svn: 143675
2011-11-04 02:48:58 +01:00
IndexModePost, LdFrm, iir,
ARM assembly parsing and encoding for LDR instructions. Enhance support for LDR instruction assembly parsing for post-indexed addressing with immediate values. Add tests. llvm-svn: 136940
2011-08-05 01:01:30 +02:00
opc, "\t$Rt, $addr, $offset",
"$addr.base = $Rn_wb", []> {
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
2011-07-26 22:54:26 +02:00
// {12} isAdd
// {11-0} imm12/Rm
bits<14> offset;
ARM assembly parsing and encoding for LDR instructions. Enhance support for LDR instruction assembly parsing for post-indexed addressing with immediate values. Add tests. llvm-svn: 136940
2011-08-05 01:01:30 +02:00
bits<4> addr;
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
2011-07-26 22:54:26 +02:00
let Inst{25} = 1;
let Inst{23} = offset{12};
ARM assembly parsing and encoding for LDR instructions. Enhance support for LDR instruction assembly parsing for post-indexed addressing with immediate values. Add tests. llvm-svn: 136940
2011-08-05 01:01:30 +02:00
let Inst{19-16} = addr;
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
2011-07-26 22:54:26 +02:00
let Inst{11-0} = offset{11-0};
s tightens up the encoding description for ARM post-indexed ldr instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL. llvm-svn: 180778
2013-04-30 11:00:12 +02:00
let Inst{4} = 0;
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
2011-07-26 22:54:26 +02:00
}
def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
ARM assembly parsing and encoding for LDR instructions. Enhance support for LDR instruction assembly parsing for post-indexed addressing with immediate values. Add tests. llvm-svn: 136940
2011-08-05 01:01:30 +02:00
(ins addr_offset_none:$addr, am2offset_imm:$offset),
Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen. llvm-svn: 143675
2011-11-04 02:48:58 +01:00
IndexModePost, LdFrm, iii,
ARM assembly parsing and encoding for LDR instructions. Enhance support for LDR instruction assembly parsing for post-indexed addressing with immediate values. Add tests. llvm-svn: 136940
2011-08-05 01:01:30 +02:00
opc, "\t$Rt, $addr, $offset",
"$addr.base = $Rn_wb", []> {
ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding. llvm-svn: 119180
2010-11-15 21:47:07 +01:00
// {12} isAdd
// {11-0} imm12/Rm
Revert r128632 again, until I figure out what break the tests llvm-svn: 128635
2011-03-31 17:54:36 +02:00
bits<14> offset;
ARM assembly parsing and encoding for LDR instructions. Enhance support for LDR instruction assembly parsing for post-indexed addressing with immediate values. Add tests. llvm-svn: 136940
2011-08-05 01:01:30 +02:00
bits<4> addr;
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
2011-07-26 22:54:26 +02:00
let Inst{25} = 0;
Revert r128632 again, until I figure out what break the tests llvm-svn: 128635
2011-03-31 17:54:36 +02:00
let Inst{23} = offset{12};
ARM assembly parsing and encoding for LDR instructions. Enhance support for LDR instruction assembly parsing for post-indexed addressing with immediate values. Add tests. llvm-svn: 136940
2011-08-05 01:01:30 +02:00
let Inst{19-16} = addr;
Revert r128632 again, until I figure out what break the tests llvm-svn: 128635
2011-03-31 17:54:36 +02:00
let Inst{11-0} = offset{11-0};
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding. llvm-svn: 119180
2010-11-15 21:47:07 +01:00
}
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
More ARM load/store indexed refactoring. Also fix an incorrect IndexMode flag for the LDRT/STRT family instructions as a side effect. llvm-svn: 118955
2010-11-13 01:35:48 +01:00
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 01:46:26 +01:00
let mayLoad = 1, hasSideEffects = 0 in {
Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen. llvm-svn: 143675
2011-11-04 02:48:58 +01:00
// FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
// IIC_iLoad_siu depending on whether it the offset register is shifted.
defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
Add ARM binary encoding information for the rest of the indexed loads. llvm-svn: 119821
2010-11-19 20:41:26 +01:00
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Tidy up. Remove unused template parameter. llvm-svn: 137345
2011-08-11 22:41:13 +02:00
multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
ARM: Correct printing of pre-indexed operands. According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
2013-04-12 20:47:25 +02:00
(ins addrmode3_pre:$addr), IndexModePre,
Add ARM binary encoding information for the rest of the indexed loads. llvm-svn: 119821
2010-11-19 20:41:26 +01:00
LdMiscFrm, itin,
opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
bits<14> addr;
let Inst{23} = addr{8}; // U bit
let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
let Inst{19-16} = addr{12-9}; // Rn
let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests. llvm-svn: 137502
2011-08-12 22:36:11 +02:00
let DecoderMethod = "DecodeAddrMode3Instruction";
Add ARM binary encoding information for the rest of the indexed loads. llvm-svn: 119821
2010-11-19 20:41:26 +01:00
}
Tidy up. Remove unused template parameter. llvm-svn: 137345
2011-08-11 22:41:13 +02:00
def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
ARM LDRH(immediate) assembly parsing and encoding support. llvm-svn: 137260
2011-08-11 00:42:16 +02:00
(ins addr_offset_none:$addr, am3offset:$offset),
IndexModePost, LdMiscFrm, itin,
opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
[]> {
Fix ARM LDR* post-indexed operand encoding. llvm-svn: 119869
2010-11-20 00:14:43 +01:00
bits<10> offset;
ARM LDRH(immediate) assembly parsing and encoding support. llvm-svn: 137260
2011-08-11 00:42:16 +02:00
bits<4> addr;
Fix ARM LDR* post-indexed operand encoding. llvm-svn: 119869
2010-11-20 00:14:43 +01:00
let Inst{23} = offset{8}; // U bit
let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
ARM LDRH(immediate) assembly parsing and encoding support. llvm-svn: 137260
2011-08-11 00:42:16 +02:00
let Inst{19-16} = addr;
Fix ARM LDR* post-indexed operand encoding. llvm-svn: 119869
2010-11-20 00:14:43 +01:00
let Inst{11-8} = offset{7-4}; // imm7_4/zero
let Inst{3-0} = offset{3-0}; // imm3_0/Rm
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests. llvm-svn: 137502
2011-08-12 22:36:11 +02:00
let DecoderMethod = "DecodeAddrMode3Instruction";
Add ARM binary encoding information for the rest of the indexed loads. llvm-svn: 119821
2010-11-19 20:41:26 +01:00
}
}
Added LDRD_PRE/POST & STRD_PRE/POST for disassembly only. llvm-svn: 96619
2010-02-18 23:31:18 +01:00
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 01:46:26 +01:00
let mayLoad = 1, hasSideEffects = 0 in {
Tidy up. Remove unused template parameter. llvm-svn: 137345
2011-08-11 22:41:13 +02:00
defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
Mark hasExtraDefRegAllocReq=1 on LDRD. The previous cleanup of LDRD got overzealous and removed it, causing post-RA scheduling to get overzealous in breaking antidependencies and invalidate these instructions. Hilarity and invalid assembly ensued. rdar://9244161 llvm-svn: 129144
2011-04-08 20:47:05 +02:00
let hasExtraDefRegAllocReq = 1 in {
Tidy up. Remove unused template parameter. llvm-svn: 137345
2011-08-11 22:41:13 +02:00
def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
ARM: Correct printing of pre-indexed operands. According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
2013-04-12 20:47:25 +02:00
(ins addrmode3_pre:$addr), IndexModePre,
Make second source operand of LDRD pre/post explicit. Finish what r128736 started. llvm-svn: 128903
2011-04-05 20:40:13 +02:00
LdMiscFrm, IIC_iLoad_d_ru,
"ldrd", "\t$Rt, $Rt2, $addr!",
"$addr.base = $Rn_wb", []> {
bits<14> addr;
let Inst{23} = addr{8}; // U bit
let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
let Inst{19-16} = addr{12-9}; // Rn
let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
Fill in some encoding information for STRD instructions. llvm-svn: 136366
2011-07-28 19:53:25 +02:00
let DecoderMethod = "DecodeAddrMode3Instruction";
Make second source operand of LDRD pre/post explicit. Finish what r128736 started. llvm-svn: 128903
2011-04-05 20:40:13 +02:00
}
Tidy up. Remove unused template parameter. llvm-svn: 137345
2011-08-11 22:41:13 +02:00
def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
ARM LDRD(immediate) assembly parsing and encoding support. llvm-svn: 137244
2011-08-10 22:29:19 +02:00
(ins addr_offset_none:$addr, am3offset:$offset),
IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
"ldrd", "\t$Rt, $Rt2, $addr, $offset",
"$addr.base = $Rn_wb", []> {
Make second source operand of LDRD pre/post explicit. Finish what r128736 started. llvm-svn: 128903
2011-04-05 20:40:13 +02:00
bits<10> offset;
ARM LDRD(immediate) assembly parsing and encoding support. llvm-svn: 137244
2011-08-10 22:29:19 +02:00
bits<4> addr;
Make second source operand of LDRD pre/post explicit. Finish what r128736 started. llvm-svn: 128903
2011-04-05 20:40:13 +02:00
let Inst{23} = offset{8}; // U bit
let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
ARM LDRD(immediate) assembly parsing and encoding support. llvm-svn: 137244
2011-08-10 22:29:19 +02:00
let Inst{19-16} = addr;
Make second source operand of LDRD pre/post explicit. Finish what r128736 started. llvm-svn: 128903
2011-04-05 20:40:13 +02:00
let Inst{11-8} = offset{7-4}; // imm7_4/zero
let Inst{3-0} = offset{3-0}; // imm3_0/Rm
Fill in some encoding information for STRD instructions. llvm-svn: 136366
2011-07-28 19:53:25 +02:00
let DecoderMethod = "DecodeAddrMode3Instruction";
Make second source operand of LDRD pre/post explicit. Finish what r128736 started. llvm-svn: 128903
2011-04-05 20:40:13 +02:00
}
Mark hasExtraDefRegAllocReq=1 on LDRD. The previous cleanup of LDRD got overzealous and removed it, causing post-RA scheduling to get overzealous in breaking antidependencies and invalidate these instructions. Hilarity and invalid assembly ensued. rdar://9244161 llvm-svn: 129144
2011-04-08 20:47:05 +02:00
} // hasExtraDefRegAllocReq = 1
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 01:46:26 +01:00
} // mayLoad = 1, hasSideEffects = 0
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Tidy up comment. llvm-svn: 137359
2011-08-11 23:41:59 +02:00
// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 01:46:26 +01:00
let mayLoad = 1, hasSideEffects = 0 in {
ARM LDRT assembly parsing and encoding. llvm-svn: 137282
2011-08-11 01:43:54 +02:00
def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addr_offset_none:$addr, am2offset_reg:$offset),
IndexModePost, LdFrm, IIC_iLoad_ru,
"ldrt", "\t$Rt, $addr, $offset",
"$addr.base = $Rn_wb", []> {
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
// {12} isAdd
// {11-0} imm12/Rm
ARM LDRT assembly parsing and encoding. llvm-svn: 137282
2011-08-11 01:43:54 +02:00
bits<14> offset;
bits<4> addr;
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let Inst{25} = 1;
ARM LDRT assembly parsing and encoding. llvm-svn: 137282
2011-08-11 01:43:54 +02:00
let Inst{23} = offset{12};
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let Inst{21} = 1; // overwrite
ARM LDRT assembly parsing and encoding. llvm-svn: 137282
2011-08-11 01:43:54 +02:00
let Inst{19-16} = addr;
let Inst{11-5} = offset{11-5};
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let Inst{4} = 0;
ARM LDRT assembly parsing and encoding. llvm-svn: 137282
2011-08-11 01:43:54 +02:00
let Inst{3-0} = offset{3-0};
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
ARM LDRT assembly parsing and encoding. llvm-svn: 137282
2011-08-11 01:43:54 +02:00
ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. llvm-svn: 199032
2014-01-12 05:36:01 +01:00
def LDRT_POST_IMM
: AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addr_offset_none:$addr, am2offset_imm:$offset),
ARM IAS: support implicit immediate 0s for {LD,ST}R{B,}T The ARM ARM indicates the mnemonics as follows: ldrbt{<c>}{<q>} <Rt>, [<Rn>], {, #+/-<imm>} ldrt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>} strbt{<c>}{<q>} <Rt>, [<Rn>] {, #<imm>} strt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>} This improves the parser to deal with the implicit immediate 0 for the mnemonics as per the specification. Thanks to Joerg Sonnenberger for the tests! llvm-svn: 198914
2014-01-10 05:38:31 +01:00
IndexModePost, LdFrm, IIC_iLoad_ru,
ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. llvm-svn: 199032
2014-01-12 05:36:01 +01:00
"ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
Apply again changes to support ARM memory asm parsing. I removed all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128689
2011-04-01 01:26:08 +02:00
// {12} isAdd
// {11-0} imm12/Rm
ARM LDRT assembly parsing and encoding. llvm-svn: 137282
2011-08-11 01:43:54 +02:00
bits<14> offset;
bits<4> addr;
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let Inst{25} = 0;
ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. llvm-svn: 199032
2014-01-12 05:36:01 +01:00
let Inst{23} = offset{12};
Added LDRT/LDRBT/STRT/STRBT for disassembly only. llvm-svn: 95916
2010-02-11 21:31:08 +01:00
let Inst{21} = 1; // overwrite
ARM LDRT assembly parsing and encoding. llvm-svn: 137282
2011-08-11 01:43:54 +02:00
let Inst{19-16} = addr;
ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. llvm-svn: 199032
2014-01-12 05:36:01 +01:00
let Inst{11-0} = offset{11-0};
ARM: fix regression caused by r198914 The disassembler would no longer be able to disambiguage between the two variants (explicit immediate #0 vs implicit, omitted #0) for the ldrt, strt, ldrbt, strbt mnemonics as both versions indicated the disassembler routine. llvm-svn: 198944
2014-01-10 17:22:47 +01:00
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
ARM parsing and encoding for LDRBT instruction. Fix the instruction representation to correctly only allow post-indexed form. Add tests. llvm-svn: 137074
2011-08-09 01:28:47 +02:00
def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addr_offset_none:$addr, am2offset_reg:$offset),
IndexModePost, LdFrm, IIC_iLoad_bh_ru,
"ldrbt", "\t$Rt, $addr, $offset",
"$addr.base = $Rn_wb", []> {
Apply again changes to support ARM memory asm parsing. I removed all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128689
2011-04-01 01:26:08 +02:00
// {12} isAdd
// {11-0} imm12/Rm
ARM parsing and encoding for LDRBT instruction. Fix the instruction representation to correctly only allow post-indexed form. Add tests. llvm-svn: 137074
2011-08-09 01:28:47 +02:00
bits<14> offset;
bits<4> addr;
let Inst{25} = 1;
let Inst{23} = offset{12};
Added LDRSBT, LDRHT, LDRSHT for disassembly only. And fixed encoding errors of AI3ldsbpo, AI3ldhpo, and AI3ldshpo in ARMInstrFormats.td in the process. llvm-svn: 96565
2010-02-18 04:27:42 +01:00
let Inst{21} = 1; // overwrite
ARM parsing and encoding for LDRBT instruction. Fix the instruction representation to correctly only allow post-indexed form. Add tests. llvm-svn: 137074
2011-08-09 01:28:47 +02:00
let Inst{19-16} = addr;
Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings. llvm-svn: 137494
2011-08-12 21:41:29 +02:00
let Inst{11-5} = offset{11-5};
let Inst{4} = 0;
let Inst{3-0} = offset{3-0};
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
ARM parsing and encoding for LDRBT instruction. Fix the instruction representation to correctly only allow post-indexed form. Add tests. llvm-svn: 137074
2011-08-09 01:28:47 +02:00
}
ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. llvm-svn: 199032
2014-01-12 05:36:01 +01:00
def LDRBT_POST_IMM
: AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addr_offset_none:$addr, am2offset_imm:$offset),
IndexModePost, LdFrm, IIC_iLoad_bh_ru,
"ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
ARM parsing and encoding for LDRBT instruction. Fix the instruction representation to correctly only allow post-indexed form. Add tests. llvm-svn: 137074
2011-08-09 01:28:47 +02:00
// {12} isAdd
// {11-0} imm12/Rm
bits<14> offset;
bits<4> addr;
let Inst{25} = 0;
ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. llvm-svn: 199032
2014-01-12 05:36:01 +01:00
let Inst{23} = offset{12};
ARM parsing and encoding for LDRBT instruction. Fix the instruction representation to correctly only allow post-indexed form. Add tests. llvm-svn: 137074
2011-08-09 01:28:47 +02:00
let Inst{21} = 1; // overwrite
let Inst{19-16} = addr;
ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. llvm-svn: 199032
2014-01-12 05:36:01 +01:00
let Inst{11-0} = offset{11-0};
ARM: fix regression caused by r198914 The disassembler would no longer be able to disambiguage between the two variants (explicit immediate #0 vs implicit, omitted #0) for the ldrt, strt, ldrbt, strbt mnemonics as both versions indicated the disassembler routine. llvm-svn: 198944
2014-01-10 17:22:47 +01:00
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
multiclass AI3ldrT<bits<4> op, string opc> {
def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
(ins addr_offset_none:$addr, postidx_imm8:$offset),
IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
"\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
bits<9> offset;
let Inst{23} = offset{8};
let Inst{22} = 1;
let Inst{11-8} = offset{7-4};
let Inst{3-0} = offset{3-0};
}
Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM llvm-svn: 153251
2012-03-22 14:24:43 +01:00
def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
(ins addr_offset_none:$addr, postidx_reg:$Rm),
IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
"\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
bits<5> Rm;
let Inst{23} = Rm{4};
let Inst{22} = 0;
let Inst{11-8} = 0;
Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM llvm-svn: 153251
2012-03-22 14:24:43 +01:00
let Unpredictable{11-8} = 0b1111;
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
let Inst{3-0} = Rm{3-0};
Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM llvm-svn: 153251
2012-03-22 14:24:43 +01:00
let DecoderMethod = "DecodeLDR";
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
}
Added LDRT/LDRBT/STRT/STRBT for disassembly only. llvm-svn: 95916
2010-02-11 21:31:08 +01:00
}
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
defm LDRHT : AI3ldrT<0b1011, "ldrht">;
defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
Add ARM binary encoding information for the rest of the indexed loads. llvm-svn: 119821
2010-11-19 20:41:26 +01:00
}
Added LDRT/LDRBT/STRT/STRBT for disassembly only. llvm-svn: 95916
2010-02-11 21:31:08 +01:00
ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. llvm-svn: 199032
2014-01-12 05:36:01 +01:00
def LDRT_POST
: ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
(outs GPR:$Rt)>;
def LDRBT_POST
: ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
(outs GPR:$Rt)>;
[ARM] Delay ARM constant pool creation. NFC. This change adds a new constant pool kind to ARMOperand. When parsing the operand for =immediate we create an instance of this operand rather than creating a constant pool entry and rewriting the operand. As the new operand kind is only created for ldr rt,= we can make ldr rt,= an explicit pseudo instruction in ARM, Thumb and Thumb2 The pseudo instruction is expanded in processInstruction(). This creates the constant pool and transforms the pseudo instruction into a pc-relative ldr to the constant pool. There are no functional changes and no modifications needed to existing tests. Required by the patch that fixes PR25722. Patch by Peter Smith. llvm-svn: 269352
2016-05-12 23:22:31 +02:00
// Pseudo instruction ldr Rt, =immediate
def LDRConstPool
: ARMAsmPseudo<"ldr${q} $Rt, $immediate",
(ins const_pool_asm_imm:$immediate, pred:$q),
(outs GPR:$Rt)>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// Store
// Stores with truncate
Add ARM encoding information for STRD. llvm-svn: 119852
2010-11-19 23:14:31 +01:00
def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
ARM STRH encoding information. llvm-svn: 118757
2010-11-11 02:09:40 +01:00
IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
[(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// Store doubleword
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 01:46:26 +01:00
let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
ARM: style changes to LDRD, STRD definition Fix indentation, name registers similar to ARM ARM. No functionality change! llvm-svn: 198563
2014-01-05 17:36:37 +01:00
def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
Requires<[IsARM, HasV5TE]> {
let Inst{21} = 0;
}
ARM IAS: support GNU extension for ldrd, strd The GNU assembler has an extension that allows for the elision of the paired register (dt2) for the LDRD and STRD mnemonics. Add support for this in the assembly parser. Canonicalise the usage during the instruction parsing from the specified version. llvm-svn: 198915
2014-01-10 05:38:35 +01:00
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// Indexed stores
Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen. llvm-svn: 143675
2011-11-04 02:48:58 +01:00
multiclass AI2_stridx<bit isByte, string opc,
InstrItinClass iii, InstrItinClass iir> {
ARM refactor indexed store instructions. Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
2011-08-05 22:35:44 +02:00
def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
ARM: Correct printing of pre-indexed operands. According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
2013-04-12 20:47:25 +02:00
(ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen. llvm-svn: 143675
2011-11-04 02:48:58 +01:00
StFrm, iii,
[ARM] Add earlyclobber constraint to pre/post-indexed ARM STR instructions. The post-indexed instructions were missing the constraint, causing unpredictable STR instructions to be emitted. The earlyclobber constraint on the pre-indexed STR instructions is not strictly necessary, as the instruction selection for pre-indexed STR instructions goes through an additional layer of pseudo instructions which have the constraint defined, however it doesn't hurt to specify the constraint directly on the pre-indexed instructions as well, since at some point someone might create instances of them programmatically and then the constraint is definitely needed. This fixes PR20323. llvm-svn: 213369
2014-07-18 14:05:49 +02:00
opc, "\t$Rt, $addr!",
"$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
ARM refactor indexed store instructions. Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
2011-08-05 22:35:44 +02:00
bits<17> addr;
let Inst{25} = 0;
let Inst{23} = addr{12}; // U (add = ('U' == 1))
let Inst{19-16} = addr{16-13}; // Rn
let Inst{11-0} = addr{11-0}; // imm12
Fix decoding of pre-indexed stores. llvm-svn: 137487
2011-08-12 20:12:39 +02:00
let DecoderMethod = "DecodeSTRPreImm";
ARM refactor indexed store instructions. Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
2011-08-05 22:35:44 +02:00
}
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
2011-07-26 22:54:26 +02:00
ARM refactor indexed store instructions. Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
2011-08-05 22:35:44 +02:00
def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
ARM STR(immediate) assembly parsing and encoding. llvm-svn: 137331
2011-08-11 21:22:40 +02:00
(ins GPR:$Rt, ldst_so_reg:$addr),
Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen. llvm-svn: 143675
2011-11-04 02:48:58 +01:00
IndexModePre, StFrm, iir,
[ARM] Add earlyclobber constraint to pre/post-indexed ARM STR instructions. The post-indexed instructions were missing the constraint, causing unpredictable STR instructions to be emitted. The earlyclobber constraint on the pre-indexed STR instructions is not strictly necessary, as the instruction selection for pre-indexed STR instructions goes through an additional layer of pseudo instructions which have the constraint defined, however it doesn't hurt to specify the constraint directly on the pre-indexed instructions as well, since at some point someone might create instances of them programmatically and then the constraint is definitely needed. This fixes PR20323. llvm-svn: 213369
2014-07-18 14:05:49 +02:00
opc, "\t$Rt, $addr!",
"$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
ARM refactor indexed store instructions. Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
2011-08-05 22:35:44 +02:00
bits<17> addr;
let Inst{25} = 1;
let Inst{23} = addr{12}; // U (add = ('U' == 1))
let Inst{19-16} = addr{16-13}; // Rn
let Inst{11-0} = addr{11-0};
let Inst{4} = 0; // Inst{4} = 0
Fix decoding of pre-indexed stores. llvm-svn: 137487
2011-08-12 20:12:39 +02:00
let DecoderMethod = "DecodeSTRPreReg";
ARM refactor indexed store instructions. Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
2011-08-05 22:35:44 +02:00
}
def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
(ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen. llvm-svn: 143675
2011-11-04 02:48:58 +01:00
IndexModePost, StFrm, iir,
ARM refactor indexed store instructions. Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
2011-08-05 22:35:44 +02:00
opc, "\t$Rt, $addr, $offset",
[ARM] Add earlyclobber constraint to pre/post-indexed ARM STR instructions. The post-indexed instructions were missing the constraint, causing unpredictable STR instructions to be emitted. The earlyclobber constraint on the pre-indexed STR instructions is not strictly necessary, as the instruction selection for pre-indexed STR instructions goes through an additional layer of pseudo instructions which have the constraint defined, however it doesn't hurt to specify the constraint directly on the pre-indexed instructions as well, since at some point someone might create instances of them programmatically and then the constraint is definitely needed. This fixes PR20323. llvm-svn: 213369
2014-07-18 14:05:49 +02:00
"$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
ARM refactor indexed store instructions. Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
2011-08-05 22:35:44 +02:00
// {12} isAdd
// {11-0} imm12/Rm
bits<14> offset;
bits<4> addr;
let Inst{25} = 1;
let Inst{23} = offset{12};
let Inst{19-16} = addr;
let Inst{11-0} = offset{11-0};
Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. llvm-svn: 156609
2012-05-11 11:28:27 +02:00
let Inst{4} = 0;
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
ARM refactor indexed store instructions. Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
2011-08-05 22:35:44 +02:00
}
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
2011-07-26 22:54:26 +02:00
ARM refactor indexed store instructions. Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
2011-08-05 22:35:44 +02:00
def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
(ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen. llvm-svn: 143675
2011-11-04 02:48:58 +01:00
IndexModePost, StFrm, iii,
ARM refactor indexed store instructions. Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
2011-08-05 22:35:44 +02:00
opc, "\t$Rt, $addr, $offset",
[ARM] Add earlyclobber constraint to pre/post-indexed ARM STR instructions. The post-indexed instructions were missing the constraint, causing unpredictable STR instructions to be emitted. The earlyclobber constraint on the pre-indexed STR instructions is not strictly necessary, as the instruction selection for pre-indexed STR instructions goes through an additional layer of pseudo instructions which have the constraint defined, however it doesn't hurt to specify the constraint directly on the pre-indexed instructions as well, since at some point someone might create instances of them programmatically and then the constraint is definitely needed. This fixes PR20323. llvm-svn: 213369
2014-07-18 14:05:49 +02:00
"$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
ARM refactor indexed store instructions. Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
2011-08-05 22:35:44 +02:00
// {12} isAdd
// {11-0} imm12/Rm
bits<14> offset;
bits<4> addr;
let Inst{25} = 0;
let Inst{23} = offset{12};
let Inst{19-16} = addr;
let Inst{11-0} = offset{11-0};
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
ARM refactor indexed store instructions. Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
2011-08-05 22:35:44 +02:00
}
}
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
2011-07-26 22:54:26 +02:00
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 01:46:26 +01:00
let mayStore = 1, hasSideEffects = 0 in {
Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen. llvm-svn: 143675
2011-11-04 02:48:58 +01:00
// FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
// IIC_iStore_siu depending on whether it the offset register is shifted.
defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
ARM refactor indexed store instructions. Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
2011-08-05 22:35:44 +02:00
}
def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
am2offset_reg:$offset),
(STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
am2offset_reg:$offset)>;
def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
am2offset_imm:$offset),
(STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
am2offset_imm:$offset)>;
def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
am2offset_reg:$offset),
(STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
am2offset_reg:$offset)>;
def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
am2offset_imm:$offset),
(STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
am2offset_imm:$offset)>;
// Pseudo-instructions for pattern matching the pre-indexed stores. We can't
// put the patterns on the instruction definitions directly as ISel wants
// the address base and offset to be separate operands, not a single
// complex operand like we represent the instructions themselves. The
// pseudos map between the two.
let usesCustomInserter = 1,
Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
(ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
4, IIC_iStore_ru,
[(set GPR:$Rn_wb,
(pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
(ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
4, IIC_iStore_ru,
[(set GPR:$Rn_wb,
(pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
(ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
4, IIC_iStore_ru,
[(set GPR:$Rn_wb,
(pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
(ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
4, IIC_iStore_ru,
[(set GPR:$Rn_wb,
(pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
ARM STRH assembly parsing and encoding. llvm-svn: 137353
2011-08-11 23:17:22 +02:00
def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
(ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
4, IIC_iStore_ru,
[(set GPR:$Rn_wb,
(pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
}
def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
ARM: Correct printing of pre-indexed operands. According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
2013-04-12 20:47:25 +02:00
(ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
ARM STRH assembly parsing and encoding. llvm-svn: 137353
2011-08-11 23:17:22 +02:00
StMiscFrm, IIC_iStore_bh_ru,
[ARM] Add earlyclobber constraint to pre/post-indexed ARM STRH instructions. The post-indexed instructions were missing the constraint, causing unpredictable STRH instructions to be emitted. The earlyclobber constraint on the pre-indexed STR instructions is not strictly necessary, as the instruction selection for pre-indexed STR instructions goes through an additional layer of pseudo instructions which have the constraint defined, however it doesn't hurt to specify the constraint directly on the pre-indexed instructions as well, since at some point someone might create instances of them programmatically and then the constraint is definitely needed. llvm-svn: 213729
2014-07-23 10:12:51 +02:00
"strh", "\t$Rt, $addr!",
"$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
ARM STRH assembly parsing and encoding. llvm-svn: 137353
2011-08-11 23:17:22 +02:00
bits<14> addr;
let Inst{23} = addr{8}; // U bit
let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
let Inst{19-16} = addr{12-9}; // Rn
let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
Fix decoding of ARM-mode STRH. llvm-svn: 137499
2011-08-12 22:02:50 +02:00
let DecoderMethod = "DecodeAddrMode3Instruction";
ARM refactor indexed store instructions. Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
2011-08-05 22:35:44 +02:00
}
Shuffle things around a bit to keep like things together. Tidy up formatting. llvm-svn: 119851
2010-11-19 23:06:57 +01:00
ARM STRH assembly parsing and encoding. llvm-svn: 137353
2011-08-11 23:17:22 +02:00
def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
(ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
[ARM] Add earlyclobber constraint to pre/post-indexed ARM STRH instructions. The post-indexed instructions were missing the constraint, causing unpredictable STRH instructions to be emitted. The earlyclobber constraint on the pre-indexed STR instructions is not strictly necessary, as the instruction selection for pre-indexed STR instructions goes through an additional layer of pseudo instructions which have the constraint defined, however it doesn't hurt to specify the constraint directly on the pre-indexed instructions as well, since at some point someone might create instances of them programmatically and then the constraint is definitely needed. llvm-svn: 213729
2014-07-23 10:12:51 +02:00
"strh", "\t$Rt, $addr, $offset",
"$addr.base = $Rn_wb,@earlyclobber $Rn_wb",
ARM STRH assembly parsing and encoding. llvm-svn: 137353
2011-08-11 23:17:22 +02:00
[(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
addr_offset_none:$addr,
am3offset:$offset))]> {
bits<10> offset;
bits<4> addr;
let Inst{23} = offset{8}; // U bit
let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
let Inst{19-16} = addr;
let Inst{11-8} = offset{7-4}; // imm7_4/zero
let Inst{3-0} = offset{3-0}; // imm3_0/Rm
Fix decoding of ARM-mode STRH. llvm-svn: 137499
2011-08-12 22:02:50 +02:00
let DecoderMethod = "DecodeAddrMode3Instruction";
ARM STRH assembly parsing and encoding. llvm-svn: 137353
2011-08-11 23:17:22 +02:00
}
skeleton of a lowerCall implementation for ARM llvm-svn: 29159
2006-07-16 03:02:57 +02:00
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 01:46:26 +01:00
let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
Tidy up. Remove unused template parameter. llvm-svn: 137345
2011-08-11 22:41:13 +02:00
def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
ARM: Correct printing of pre-indexed operands. According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
2013-04-12 20:47:25 +02:00
(ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
ARM STRD assembly parsing and encoding. llvm-svn: 137342
2011-08-11 22:28:23 +02:00
IndexModePre, StMiscFrm, IIC_iStore_d_ru,
"strd", "\t$Rt, $Rt2, $addr!",
"$addr.base = $Rn_wb", []> {
bits<14> addr;
let Inst{23} = addr{8}; // U bit
let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
let Inst{19-16} = addr{12-9}; // Rn
let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
Fill in some encoding information for STRD instructions. llvm-svn: 136366
2011-07-28 19:53:25 +02:00
let DecoderMethod = "DecodeAddrMode3Instruction";
}
Added LDRD_PRE/POST & STRD_PRE/POST for disassembly only. llvm-svn: 96619
2010-02-18 23:31:18 +01:00
Tidy up. Remove unused template parameter. llvm-svn: 137345
2011-08-11 22:41:13 +02:00
def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
ARM STRD assembly parsing and encoding. llvm-svn: 137342
2011-08-11 22:28:23 +02:00
(ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
am3offset:$offset),
IndexModePost, StMiscFrm, IIC_iStore_d_ru,
"strd", "\t$Rt, $Rt2, $addr, $offset",
"$addr.base = $Rn_wb", []> {
Fill in some encoding information for STRD instructions. llvm-svn: 136366
2011-07-28 19:53:25 +02:00
bits<10> offset;
ARM STRD assembly parsing and encoding. llvm-svn: 137342
2011-08-11 22:28:23 +02:00
bits<4> addr;
let Inst{23} = offset{8}; // U bit
let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
let Inst{19-16} = addr;
let Inst{11-8} = offset{7-4}; // imm7_4/zero
let Inst{3-0} = offset{3-0}; // imm3_0/Rm
Fill in some encoding information for STRD instructions. llvm-svn: 136366
2011-07-28 19:53:25 +02:00
let DecoderMethod = "DecodeAddrMode3Instruction";
}
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 01:46:26 +01:00
} // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
Added LDRD_PRE/POST & STRD_PRE/POST for disassembly only. llvm-svn: 96619
2010-02-18 23:31:18 +01:00
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
// STRT, STRBT, and STRHT
Added LDRT/LDRBT/STRT/STRBT for disassembly only. llvm-svn: 95916
2010-02-11 21:31:08 +01:00
ARM STRBT assembly parsing and encoding. llvm-svn: 137337
2011-08-11 22:04:56 +02:00
def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
(ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
IndexModePost, StFrm, IIC_iStore_bh_ru,
"strbt", "\t$Rt, $addr, $offset",
"$addr.base = $Rn_wb", []> {
// {12} isAdd
// {11-0} imm12/Rm
bits<14> offset;
bits<4> addr;
Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions. llvm-svn: 136255
2011-07-27 22:29:48 +02:00
let Inst{25} = 1;
ARM STRBT assembly parsing and encoding. llvm-svn: 137337
2011-08-11 22:04:56 +02:00
let Inst{23} = offset{12};
Added LDRT/LDRBT/STRT/STRBT for disassembly only. llvm-svn: 95916
2010-02-11 21:31:08 +01:00
let Inst{21} = 1; // overwrite
ARM STRBT assembly parsing and encoding. llvm-svn: 137337
2011-08-11 22:04:56 +02:00
let Inst{19-16} = addr;
let Inst{11-5} = offset{11-5};
Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions. llvm-svn: 136255
2011-07-27 22:29:48 +02:00
let Inst{4} = 0;
ARM STRBT assembly parsing and encoding. llvm-svn: 137337
2011-08-11 22:04:56 +02:00
let Inst{3-0} = offset{3-0};
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
Added LDRT/LDRBT/STRT/STRBT for disassembly only. llvm-svn: 95916
2010-02-11 21:31:08 +01:00
}
ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. llvm-svn: 199032
2014-01-12 05:36:01 +01:00
def STRBT_POST_IMM
: AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
(ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
IndexModePost, StFrm, IIC_iStore_bh_ru,
"strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
ARM STRBT assembly parsing and encoding. llvm-svn: 137337
2011-08-11 22:04:56 +02:00
// {12} isAdd
// {11-0} imm12/Rm
bits<14> offset;
bits<4> addr;
Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions. llvm-svn: 136255
2011-07-27 22:29:48 +02:00
let Inst{25} = 0;
ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. llvm-svn: 199032
2014-01-12 05:36:01 +01:00
let Inst{23} = offset{12};
Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions. llvm-svn: 136255
2011-07-27 22:29:48 +02:00
let Inst{21} = 1; // overwrite
ARM STRBT assembly parsing and encoding. llvm-svn: 137337
2011-08-11 22:04:56 +02:00
let Inst{19-16} = addr;
ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. llvm-svn: 199032
2014-01-12 05:36:01 +01:00
let Inst{11-0} = offset{11-0};
ARM: fix regression caused by r198914 The disassembler would no longer be able to disambiguage between the two variants (explicit immediate #0 vs implicit, omitted #0) for the ldrt, strt, ldrbt, strbt mnemonics as both versions indicated the disassembler routine. llvm-svn: 198944
2014-01-10 17:22:47 +01:00
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. llvm-svn: 199032
2014-01-12 05:36:01 +01:00
def STRBT_POST
: ARMAsmPseudo<"strbt${q} $Rt, $addr",
(ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
ARM IAS: support implicit immediate 0s for {LD,ST}R{B,}T The ARM ARM indicates the mnemonics as follows: ldrbt{<c>}{<q>} <Rt>, [<Rn>], {, #+/-<imm>} ldrt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>} strbt{<c>}{<q>} <Rt>, [<Rn>] {, #<imm>} strt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>} This improves the parser to deal with the implicit immediate 0 for the mnemonics as per the specification. Thanks to Joerg Sonnenberger for the tests! llvm-svn: 198914
2014-01-10 05:38:31 +01:00
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 01:46:26 +01:00
let mayStore = 1, hasSideEffects = 0 in {
ARM STRT assembly parsing and encoding. llvm-svn: 137372
2011-08-12 00:18:00 +02:00
def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
(ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
IndexModePost, StFrm, IIC_iStore_ru,
"strt", "\t$Rt, $addr, $offset",
"$addr.base = $Rn_wb", []> {
// {12} isAdd
// {11-0} imm12/Rm
bits<14> offset;
bits<4> addr;
Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions. llvm-svn: 136255
2011-07-27 22:29:48 +02:00
let Inst{25} = 1;
ARM STRT assembly parsing and encoding. llvm-svn: 137372
2011-08-12 00:18:00 +02:00
let Inst{23} = offset{12};
Added LDRT/LDRBT/STRT/STRBT for disassembly only. llvm-svn: 95916
2010-02-11 21:31:08 +01:00
let Inst{21} = 1; // overwrite
ARM STRT assembly parsing and encoding. llvm-svn: 137372
2011-08-12 00:18:00 +02:00
let Inst{19-16} = addr;
let Inst{11-5} = offset{11-5};
Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions. llvm-svn: 136255
2011-07-27 22:29:48 +02:00
let Inst{4} = 0;
ARM STRT assembly parsing and encoding. llvm-svn: 137372
2011-08-12 00:18:00 +02:00
let Inst{3-0} = offset{3-0};
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
Added LDRT/LDRBT/STRT/STRBT for disassembly only. llvm-svn: 95916
2010-02-11 21:31:08 +01:00
}
ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. llvm-svn: 199032
2014-01-12 05:36:01 +01:00
def STRT_POST_IMM
: AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
(ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
IndexModePost, StFrm, IIC_iStore_ru,
"strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
ARM STRT assembly parsing and encoding. llvm-svn: 137372
2011-08-12 00:18:00 +02:00
// {12} isAdd
// {11-0} imm12/Rm
bits<14> offset;
bits<4> addr;
Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions. llvm-svn: 136255
2011-07-27 22:29:48 +02:00
let Inst{25} = 0;
ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. llvm-svn: 199032
2014-01-12 05:36:01 +01:00
let Inst{23} = offset{12};
Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions. llvm-svn: 136255
2011-07-27 22:29:48 +02:00
let Inst{21} = 1; // overwrite
ARM STRT assembly parsing and encoding. llvm-svn: 137372
2011-08-12 00:18:00 +02:00
let Inst{19-16} = addr;
ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. llvm-svn: 199032
2014-01-12 05:36:01 +01:00
let Inst{11-0} = offset{11-0};
ARM: fix regression caused by r198914 The disassembler would no longer be able to disambiguage between the two variants (explicit immediate #0 vs implicit, omitted #0) for the ldrt, strt, ldrbt, strbt mnemonics as both versions indicated the disassembler routine. llvm-svn: 198944
2014-01-10 17:22:47 +01:00
let DecoderMethod = "DecodeAddrMode2IdxInstruction";
}
ARM STRT assembly parsing and encoding. llvm-svn: 137372
2011-08-12 00:18:00 +02:00
}
ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. llvm-svn: 199032
2014-01-12 05:36:01 +01:00
def STRT_POST
: ARMAsmPseudo<"strt${q} $Rt, $addr",
(ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions. llvm-svn: 136255
2011-07-27 22:29:48 +02:00
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
multiclass AI3strT<bits<4> op, string opc> {
def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
(ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
"\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
bits<9> offset;
let Inst{23} = offset{8};
let Inst{22} = 1;
let Inst{11-8} = offset{7-4};
let Inst{3-0} = offset{3-0};
}
def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
(ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
"\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
bits<5> Rm;
let Inst{23} = Rm{4};
let Inst{22} = 0;
let Inst{11-8} = 0;
let Inst{3-0} = Rm{3-0};
}
Added STRHT for disassembly only and fixed a bug in AI3sthpo class where the W bit should be set to 0 instead of 1. llvm-svn: 97481
2010-03-01 20:22:00 +01:00
}
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
defm STRHT : AI3strT<0b1011, "strht">;
[ARMv8] Fix a few things in one swoop. # Add some negative tests. # Fix some formatting issues. # Add some missing IsThumb / ARMv8 # Fix some outs / ins mistakes. llvm-svn: 189490
2013-08-28 18:39:20 +02:00
def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
[ARMv8] Add MC support for the new load/store acquire/release instructions. llvm-svn: 189388
2013-08-27 19:38:16 +02:00
NoItinerary, "stl", "\t$Rt, $addr", []>;
[ARMv8] Fix a few things in one swoop. # Add some negative tests. # Fix some formatting issues. # Add some missing IsThumb / ARMv8 # Fix some outs / ins mistakes. llvm-svn: 189490
2013-08-28 18:39:20 +02:00
def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
[ARMv8] Add MC support for the new load/store acquire/release instructions. llvm-svn: 189388
2013-08-27 19:38:16 +02:00
NoItinerary, "stlb", "\t$Rt, $addr", []>;
[ARMv8] Fix a few things in one swoop. # Add some negative tests. # Fix some formatting issues. # Add some missing IsThumb / ARMv8 # Fix some outs / ins mistakes. llvm-svn: 189490
2013-08-28 18:39:20 +02:00
def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
[ARMv8] Add MC support for the new load/store acquire/release instructions. llvm-svn: 189388
2013-08-27 19:38:16 +02:00
NoItinerary, "stlh", "\t$Rt, $addr", []>;
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
//===----------------------------------------------------------------------===//
// Load / store multiple Instructions.
//
added a skeleton of the ARM backend llvm-svn: 28301
2006-05-15 00:18:28 +02:00
ARM LDM/STM system instruction variants. rdar://10550269 llvm-svn: 146519
2011-12-13 22:48:29 +01:00
multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
InstrItinClass itin, InstrItinClass itin_upd> {
Update ARM Assembly of LDM/STM. ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such. Update the parsing/encoding tests accordingly. llvm-svn: 135168
2011-07-14 20:35:38 +02:00
// IA is the default, so no need for an explicit suffix on the
Fix typos found by http://github.com/lyda/misspell-check llvm-svn: 157885
2012-06-02 12:20:22 +02:00
// mnemonic here. Without it is the canonical spelling.
Encode the multi-load/store instructions with their respective modes ('ia', 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
2010-11-16 02:16:36 +01:00
def IA :
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, f, itin,
ARM LDM/STM system instruction variants. rdar://10550269 llvm-svn: 146519
2011-12-13 22:48:29 +01:00
!strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
let Inst{24-23} = 0b01; // Increment After
ARM LDM/STM system instruction variants. rdar://10550269 llvm-svn: 146519
2011-12-13 22:48:29 +01:00
let Inst{22} = P_bit;
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
}
Encode the multi-load/store instructions with their respective modes ('ia', 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
2010-11-16 02:16:36 +01:00
def IA_UPD :
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeUpd, f, itin_upd,
ARM LDM/STM system instruction variants. rdar://10550269 llvm-svn: 146519
2011-12-13 22:48:29 +01:00
!strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
let Inst{24-23} = 0b01; // Increment After
ARM LDM/STM system instruction variants. rdar://10550269 llvm-svn: 146519
2011-12-13 22:48:29 +01:00
let Inst{22} = P_bit;
Encode the multi-load/store instructions with their respective modes ('ia', 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
2010-11-16 02:16:36 +01:00
let Inst{21} = 1; // Writeback
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
let Inst{20} = L_bit;
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
}
Encode the multi-load/store instructions with their respective modes ('ia', 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
2010-11-16 02:16:36 +01:00
def DA :
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, f, itin,
ARM LDM/STM system instruction variants. rdar://10550269 llvm-svn: 146519
2011-12-13 22:48:29 +01:00
!strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
let Inst{24-23} = 0b00; // Decrement After
ARM LDM/STM system instruction variants. rdar://10550269 llvm-svn: 146519
2011-12-13 22:48:29 +01:00
let Inst{22} = P_bit;
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
}
Encode the multi-load/store instructions with their respective modes ('ia', 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
2010-11-16 02:16:36 +01:00
def DA_UPD :
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeUpd, f, itin_upd,
ARM LDM/STM system instruction variants. rdar://10550269 llvm-svn: 146519
2011-12-13 22:48:29 +01:00
!strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
let Inst{24-23} = 0b00; // Decrement After
ARM LDM/STM system instruction variants. rdar://10550269 llvm-svn: 146519
2011-12-13 22:48:29 +01:00
let Inst{22} = P_bit;
Encode the multi-load/store instructions with their respective modes ('ia', 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
2010-11-16 02:16:36 +01:00
let Inst{21} = 1; // Writeback
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
let Inst{20} = L_bit;
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
}
Encode the multi-load/store instructions with their respective modes ('ia', 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
2010-11-16 02:16:36 +01:00
def DB :
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, f, itin,
ARM LDM/STM system instruction variants. rdar://10550269 llvm-svn: 146519
2011-12-13 22:48:29 +01:00
!strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
let Inst{24-23} = 0b10; // Decrement Before
ARM LDM/STM system instruction variants. rdar://10550269 llvm-svn: 146519
2011-12-13 22:48:29 +01:00
let Inst{22} = P_bit;
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
}
Encode the multi-load/store instructions with their respective modes ('ia', 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
2010-11-16 02:16:36 +01:00
def DB_UPD :
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeUpd, f, itin_upd,
ARM LDM/STM system instruction variants. rdar://10550269 llvm-svn: 146519
2011-12-13 22:48:29 +01:00
!strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
let Inst{24-23} = 0b10; // Decrement Before
ARM LDM/STM system instruction variants. rdar://10550269 llvm-svn: 146519
2011-12-13 22:48:29 +01:00
let Inst{22} = P_bit;
Encode the multi-load/store instructions with their respective modes ('ia', 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
2010-11-16 02:16:36 +01:00
let Inst{21} = 1; // Writeback
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
let Inst{20} = L_bit;
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
}
Encode the multi-load/store instructions with their respective modes ('ia', 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
2010-11-16 02:16:36 +01:00
def IB :
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, f, itin,
ARM LDM/STM system instruction variants. rdar://10550269 llvm-svn: 146519
2011-12-13 22:48:29 +01:00
!strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
let Inst{24-23} = 0b11; // Increment Before
ARM LDM/STM system instruction variants. rdar://10550269 llvm-svn: 146519
2011-12-13 22:48:29 +01:00
let Inst{22} = P_bit;
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
}
Encode the multi-load/store instructions with their respective modes ('ia', 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
2010-11-16 02:16:36 +01:00
def IB_UPD :
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeUpd, f, itin_upd,
ARM LDM/STM system instruction variants. rdar://10550269 llvm-svn: 146519
2011-12-13 22:48:29 +01:00
!strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
let Inst{24-23} = 0b11; // Increment Before
ARM LDM/STM system instruction variants. rdar://10550269 llvm-svn: 146519
2011-12-13 22:48:29 +01:00
let Inst{22} = P_bit;
Encode the multi-load/store instructions with their respective modes ('ia', 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
2010-11-16 02:16:36 +01:00
let Inst{21} = 1; // Writeback
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
let Inst{20} = L_bit;
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
}
Clean whitespace. llvm-svn: 127900
2011-03-18 20:47:14 +01:00
}
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the future to separate out the ia, ib, da, db variants of the load/store multiple instructions. llvm-svn: 118995
2010-11-13 10:09:38 +01:00
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 01:46:26 +01:00
let hasSideEffects = 0 in {
Add uses of the *_ldst_multi multiclasses. These aren't used yet. llvm-svn: 118999
2010-11-13 11:57:02 +01:00
[ARM][MC] Move information about variadic register defs into tablegen Currently, variadic operands on an MCInst are assumed to be uses, because they come after the defs. However, this is not always the case, for example the Arm/Thumb LDM instructions write to a variable number of registers. This adds a property of instruction definitions which can be used to mark variadic operands as defs. This only affects MCInst, because MachineInstruction already tracks use/def per operand in each instance of the instruction, so can already represent this. This property can then be checked in MCInstrDesc, allowing us to remove some special cases in ARMAsmParser::isITBlockTerminator. Differential revision: https://reviews.llvm.org/D54853 llvm-svn: 348114
2018-12-03 11:32:42 +01:00
let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in
ARM LDM/STM system instruction variants. rdar://10550269 llvm-svn: 146519
2011-12-13 22:48:29 +01:00
defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
ARM: further improve deprecated diagnosis (LDM) The ARM ARM states: LDM/LDMIA/LDMFD: The SP can be in the list. However, ARM deprecates using these instructions with SP in the list. ARM deprecates using these instructions with both the LR and the PC in the list. LDMDA/LDMFA/LDMDB/LDMEA/LDMIB/LDMED: The SP can be in the list. However, instructions that include the SP in the list are deprecated. Instructions that include both the LR and the PC in the list are deprecated. POP: The SP can only be in the list before ARMv7. ARM deprecates any use of ARM instructions that include the SP, and the value of the SP after such an instruction is UNKNOWN. ARM deprecates the use of this instruction with both the LR and the PC in the list. Attempt to diagnose use of deprecated forms of these instructions. This mirrors the previous changes to diagnose use of the deprecated forms of STM in ARM mode. llvm-svn: 224682
2014-12-20 21:25:36 +01:00
IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">;
Add uses of the *_ldst_multi multiclasses. These aren't used yet. llvm-svn: 118999
2010-11-13 11:57:02 +01:00
let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
ARM LDM/STM system instruction variants. rdar://10550269 llvm-svn: 146519
2011-12-13 22:48:29 +01:00
defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
ARM: diagnose deprecated syntax The use of SP and PC in the register list for stores is deprecated on ARM (ARM ARM A.8.8.199): ARM deprecates the use of ARM instructions that include the SP or the PC in the list. Provide a deprecation warning from the assembler in the case that the syntax is ever seen. llvm-svn: 224319
2014-12-16 06:53:25 +01:00
IIC_iStore_mu>,
ComplexDeprecationPredicate<"ARMStore">;
Add uses of the *_ldst_multi multiclasses. These aren't used yet. llvm-svn: 118999
2010-11-13 11:57:02 +01:00
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 01:46:26 +01:00
} // hasSideEffects
Add uses of the *_ldst_multi multiclasses. These aren't used yet. llvm-svn: 118999
2010-11-13 11:57:02 +01:00
Encode the multi-load/store instructions with their respective modes ('ia', 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
2010-11-16 02:16:36 +01:00
// FIXME: remove when we have a way to marking a MI with these properties.
// FIXME: Should pc be an implicit operand like PICADD, etc?
let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
2011-07-08 19:40:42 +02:00
def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
reglist:$regs, variable_ops),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
4, IIC_iLoad_mBr, [],
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
2011-07-08 19:40:42 +02:00
(LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side- effect that we get proper instruction printing using the "pop" mnemonic for it. llvm-svn: 127502
2011-03-11 23:51:41 +01:00
RegConstraint<"$Rn = $wb">;
Change ARM ld/st multiple instructions to have variant instructions for writebacks to the address register. This gets rid of the hack that the first register on the list was the magic writeback register operand. There was an implicit constraint that if that operand was not reg0 it had to match the base register operand. The post-RA scheduler's antidependency breaker did not understand that constraint and sometimes changed one without the other. This also fixes Radar 7495976 and should help the verifier work better for ARM code. There are now new ld/st instructions explicit writeback operands and explicit constraints that tie those registers together. llvm-svn: 98409
2010-03-13 02:08:20 +01:00
ARM LDM/STM system instruction variants. rdar://10550269 llvm-svn: 146519
2011-12-13 22:48:29 +01:00
let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
IIC_iLoad_mu>;
let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
IIC_iStore_mu>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
//===----------------------------------------------------------------------===//
// Move Instructions.
//
implement LDRB, LDRSB, LDRH and LDRSH llvm-svn: 30976
2006-10-16 19:17:22 +02:00
[X86][MIPS][ARM] New machine instruction property 'isMoveReg' This property is needed in order to follow values movement between registers. This property is used in TII to implement method that returns true if simple copy like instruction is recognized, along with source and destination machine operands. Patch by Nikola Prica. Differential Revision: https://reviews.llvm.org/D45204 llvm-svn: 333093
2018-05-23 17:28:28 +02:00
let hasSideEffects = 0, isMoveReg = 1 in
Add MOVi ARM encoding. llvm-svn: 116321
2010-10-12 20:09:12 +02:00
def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
"mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
Add MOVi ARM encoding. llvm-svn: 116321
2010-10-12 20:09:12 +02:00
bits<4> Rd;
bits<4> Rm;
Implement a few more binary encoding bits. Still very early stage proof-of- concept level stuff at this point, but it is generally working for those instructions that know how to map the operands. This patch fills in the register operands for add/sub/or/etc instructions and adds the conditional execution predicate encoding. llvm-svn: 116112
2010-10-08 23:45:55 +02:00
Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000. rdar://problem/9224276 llvm-svn: 128749
2011-04-02 01:30:25 +02:00
let Inst{19-16} = 0b0000;
My previous patch (r84124) for setting the encoding bits 4 and 7 of DPSoRegFrm was wrong and too aggressive in the sense that DPSoRegFrm includes both constant shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and Inst{7} = 0). The 'rr' fragment of the multiclass definitions actually means register/register with no shift, see A8-11. llvm-svn: 86319
2009-11-07 01:54:36 +01:00
let Inst{11-4} = 0b00000000;
Set instruction encoding bits 4 and 7 for ARM register-register and register-shifted-register instructions. Patch by Johnny Chen. llvm-svn: 84124
2009-10-14 21:00:24 +02:00
let Inst{25} = 0;
Add MOVi ARM encoding. llvm-svn: 116321
2010-10-12 20:09:12 +02:00
let Inst{3-0} = Rm;
let Inst{15-12} = Rd;
Set instruction encoding bits 4 and 7 for ARM register-register and register-shifted-register instructions. Patch by Johnny Chen. llvm-svn: 84124
2009-10-14 21:00:24 +02:00
}
Add file missing from previous commit. llvm-svn: 106058
2010-06-16 00:24:08 +02:00
// A version for the smaller set of tail call registers.
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 01:46:26 +01:00
let hasSideEffects = 0 in
Trailing whitespace. llvm-svn: 117188
2010-10-23 01:48:29 +02:00
def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
Add MOVi ARM encoding. llvm-svn: 116321
2010-10-12 20:09:12 +02:00
bits<4> Rd;
bits<4> Rm;
Implement a few more binary encoding bits. Still very early stage proof-of- concept level stuff at this point, but it is generally working for those instructions that know how to map the operands. This patch fills in the register operands for add/sub/or/etc instructions and adds the conditional execution predicate encoding. llvm-svn: 116112
2010-10-08 23:45:55 +02:00
Add file missing from previous commit. llvm-svn: 106058
2010-06-16 00:24:08 +02:00
let Inst{11-4} = 0b00000000;
let Inst{25} = 0;
Add MOVi ARM encoding. llvm-svn: 116321
2010-10-12 20:09:12 +02:00
let Inst{3-0} = Rm;
let Inst{15-12} = Rd;
Add file missing from previous commit. llvm-svn: 106058
2010-06-16 00:24:08 +02:00
}
Tighten operand checking of register-shifted-register operands. llvm-svn: 137180
2011-08-10 01:33:27 +02:00
def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. llvm-svn: 135722
2011-07-22 01:38:37 +02:00
DPSoRegRegFrm, IIC_iMOVsr,
Tidy up. 80 columns. llvm-svn: 137277
2011-08-11 01:23:47 +02:00
"mov", "\t$Rd, $src",
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
[(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
Sched<[WriteALU]> {
Add missing Rd encoding for MOVs instruction. llvm-svn: 116537
2010-10-15 01:28:31 +02:00
bits<4> Rd;
MOVi16 and MOVT ARM mode encodings. llvm-svn: 116498
2010-10-14 20:54:27 +02:00
bits<12> src;
Add missing Rd encoding for MOVs instruction. llvm-svn: 116537
2010-10-15 01:28:31 +02:00
let Inst{15-12} = Rd;
MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE. rdar://problem/9224120 llvm-svn: 128748
2011-04-02 01:15:50 +02:00
let Inst{19-16} = 0b0000;
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. llvm-svn: 135722
2011-07-22 01:38:37 +02:00
let Inst{11-8} = src{11-8};
let Inst{7} = 0;
let Inst{6-5} = src{6-5};
let Inst{4} = 1;
let Inst{3-0} = src{3-0};
Set instruction encoding bits 4 and 7 for ARM register-register and register-shifted-register instructions. Patch by Johnny Chen. llvm-svn: 84124
2009-10-14 21:00:24 +02:00
let Inst{25} = 0;
}
Constant generation instructions are re-materializable. llvm-svn: 35161
2007-03-19 08:09:02 +01:00
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. llvm-svn: 135722
2011-07-22 01:38:37 +02:00
def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
DPSoRegImmFrm, IIC_iMOVsr,
"mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
UnaryDP, Sched<[WriteALU]> {
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. llvm-svn: 135722
2011-07-22 01:38:37 +02:00
bits<4> Rd;
bits<12> src;
let Inst{15-12} = Rd;
let Inst{19-16} = 0b0000;
let Inst{11-5} = src{11-5};
let Inst{4} = 0;
let Inst{3-0} = src{3-0};
let Inst{25} = 0;
}
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 llvm-svn: 119548
2010-11-17 21:13:28 +01:00
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
"mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
Sched<[WriteALU]> {
Add MOVi ARM encoding. llvm-svn: 116321
2010-10-12 20:09:12 +02:00
bits<4> Rd;
Move the ARM so_imm encoding into a custom operand encoder and remove the explicit handling of the instructions referencing it from the MC code emitter. llvm-svn: 116367
2010-10-13 01:18:08 +02:00
bits<12> imm;
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. This should be better than single load from constpool. llvm-svn: 82948
2009-09-28 01:52:58 +02:00
let Inst{25} = 1;
Add MOVi ARM encoding. llvm-svn: 116321
2010-10-12 20:09:12 +02:00
let Inst{15-12} = Rd;
let Inst{19-16} = 0b0000;
Move the ARM so_imm encoding into a custom operand encoder and remove the explicit handling of the instructions referencing it from the MC code emitter. llvm-svn: 116367
2010-10-13 01:18:08 +02:00
let Inst{11-0} = imm;
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. This should be better than single load from constpool. llvm-svn: 82948
2009-09-28 01:52:58 +02:00
}
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 llvm-svn: 119548
2010-11-17 21:13:28 +01:00
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
ARM assembly parsing for MOV (immediate). Add range checking for the immediate operand and handle the "mov" mnemonic choosing between encodings based on the value of the immediate. Add tests for fixups, encoding choice and values, and diagnostic for out of range values. llvm-svn: 135500
2011-07-19 21:13:28 +02:00
def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. This should be better than single load from constpool. llvm-svn: 82948
2009-09-28 01:52:58 +02:00
DPFrm, IIC_iMOVi,
MOVi16 and MOVT ARM mode encodings. llvm-svn: 116498
2010-10-14 20:54:27 +02:00
"movw", "\t$Rd, $imm",
[(set GPR:$Rd, imm0_65535:$imm)]>,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
MOVi16 and MOVT ARM mode encodings. llvm-svn: 116498
2010-10-14 20:54:27 +02:00
bits<4> Rd;
bits<16> imm;
let Inst{15-12} = Rd;
let Inst{11-0} = imm{11-0};
let Inst{19-16} = imm{15-12};
Add some ARM instruction encoding bits. Patch by Johnny Chen. llvm-svn: 83983
2009-10-13 19:35:30 +02:00
let Inst{20} = 0;
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. This should be better than single load from constpool. llvm-svn: 82948
2009-09-28 01:52:58 +02:00
let Inst{25} = 1;
Adding back support for printing operands symbolically to ARM's new disassembler using llvm's public 'C' disassembler API now including annotations. Hooked this up to Darwin's otool(1) so it can again print things like branch targets for example this: blx _puts instead of this: blx #-36 and includes support for annotations for branches to symbol stubs like: bl 0x40 @ symbol stub for: _puts and annotations for pc relative loads like this: ldr r3, #8 @ literal pool for: Hello, world! Also again can print the expression encoded in the Mach-O relocation entries for things like this: movt r0, :upper16:((_foo-_bar)+1234) llvm-svn: 141129
2011-10-05 00:44:48 +02:00
let DecoderMethod = "DecodeArmMOVTWInstruction";
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. This should be better than single load from constpool. llvm-svn: 82948
2009-09-28 01:52:58 +02:00
}
ARM assembly parsing for MOV (immediate). Add range checking for the immediate operand and handle the "mov" mnemonic choosing between encodings based on the value of the immediate. Add tests for fixups, encoding choice and values, and diagnostic for out of range values. llvm-svn: 135500
2011-07-19 21:13:28 +02:00
def : InstAlias<"mov${p} $Rd, $imm",
ARM target does not use printAliasInstr machinery which forces having special checks in ArmInstPrinter::printInstruction. This patch addresses this issue. Not all special checks could be removed: either they involve elaborated conditions under which the alias is emitted (e.g. ldm/stm on sp may be pop/push but only if the number of registers is >= 2) or the number of registers is multivalued (like happens again with ldm/stm) and they do not match the InstAlias pattern which assumes single-valued operands in the pattern. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20237 llvm-svn: 271667
2016-06-03 15:19:43 +02:00
(MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>,
[ARM] ARM mov InstAlias for MOVW lacks HasV6T2 The movw instruction is only available in ARM state for V6T2 and above. The MOVi16 instruction has requirement HasV6T2 but the InstAlias for mov rd, imm where the operand is imm0_65535_expr:$imm does not. This means that movw can incorrectly be used in ARMv4 and ARMv5 by writing mov rd, 0x1234. The simple fix is to the requirement HasV6T2 to the InstAlias. Tests added to not-armv4.s. Patch by Peter Smith. llvm-svn: 269761
2016-05-17 15:05:28 +02:00
Requires<[IsARM, HasV6T2]>;
ARM assembly parsing for MOV (immediate). Add range checking for the immediate operand and handle the "mov" mnemonic choosing between encodings based on the value of the immediate. Add tests for fixups, encoding choice and values, and diagnostic for out of range values. llvm-svn: 135500
2011-07-19 21:13:28 +02:00
Last round of fixes for movw + movt global address codegen. 1. Fixed ARM pc adjustment. 2. Fixed dynamic-no-pic codegen 3. CSE of pc-relative load of global addresses. It's now enabled by default for Darwin. llvm-svn: 123991
2011-01-21 19:55:51 +01:00
def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
(ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
Sched<[WriteALU]>;
Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g. movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4)) movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4)) LPC0_0: add r0, pc, r0 It's not yet enabled by default as some tests are failing. I suspect bugs in down stream tools. llvm-svn: 123619
2011-01-17 09:03:18 +01:00
let Constraints = "$src = $Rd" in {
Tidy up. 80 columns. llvm-svn: 137277
2011-08-11 01:23:47 +02:00
def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
(ins GPR:$src, imm0_65535_expr:$imm),
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. This should be better than single load from constpool. llvm-svn: 82948
2009-09-28 01:52:58 +02:00
DPFrm, IIC_iMOVi,
MOVi16 and MOVT ARM mode encodings. llvm-svn: 116498
2010-10-14 20:54:27 +02:00
"movt", "\t$Rd, $imm",
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
[(set GPRnopc:$Rd,
Remove trailing whitespace llvm-svn: 96388
2010-02-16 22:07:46 +01:00
(or (and GPR:$src, 0xffff),
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. This should be better than single load from constpool. llvm-svn: 82948
2009-09-28 01:52:58 +02:00
lo16AllZero:$imm))]>, UnaryDP,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
MOVi16 and MOVT ARM mode encodings. llvm-svn: 116498
2010-10-14 20:54:27 +02:00
bits<4> Rd;
bits<16> imm;
let Inst{15-12} = Rd;
let Inst{11-0} = imm{11-0};
let Inst{19-16} = imm{15-12};
Add some ARM instruction encoding bits. Patch by Johnny Chen. llvm-svn: 83983
2009-10-13 19:35:30 +02:00
let Inst{20} = 0;
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. This should be better than single load from constpool. llvm-svn: 82948
2009-09-28 01:52:58 +02:00
let Inst{25} = 1;
Adding back support for printing operands symbolically to ARM's new disassembler using llvm's public 'C' disassembler API now including annotations. Hooked this up to Darwin's otool(1) so it can again print things like branch targets for example this: blx _puts instead of this: blx #-36 and includes support for annotations for branches to symbol stubs like: bl 0x40 @ symbol stub for: _puts and annotations for pc relative loads like this: ldr r3, #8 @ literal pool for: Hello, world! Also again can print the expression encoded in the Mach-O relocation entries for things like this: movt r0, :upper16:((_foo-_bar)+1234) llvm-svn: 141129
2011-10-05 00:44:48 +02:00
let DecoderMethod = "DecodeArmMOVTWInstruction";
Fix arm jit encoding bug introduced by 75048. Some instructions', e.g. MOVi, bit 25 should be set. llvm-svn: 81310
2009-09-09 03:47:07 +02:00
}
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. llvm-svn: 38501
2007-07-10 20:08:01 +02:00
Last round of fixes for movw + movt global address codegen. 1. Fixed ARM pc adjustment. 2. Fixed dynamic-no-pic codegen 3. CSE of pc-relative load of global addresses. It's now enabled by default for Darwin. llvm-svn: 123991
2011-01-21 19:55:51 +01:00
def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
(ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
Sched<[WriteALU]>;
Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g. movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4)) movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4)) LPC0_0: add r0, pc, r0 It's not yet enabled by default as some tests are failing. I suspect bugs in down stream tools. llvm-svn: 123619
2011-01-17 09:03:18 +01:00
} // Constraints
Match more patterns to movt. llvm-svn: 84751
2009-10-21 10:15:52 +02:00
def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
Requires<[IsARM, HasV6T2]>;
RRX reads CPSR. llvm-svn: 80699
2009-09-01 20:32:09 +02:00
let Uses = [CPSR] in
ARM PseudoInst instructions don't need or use an assembler string. Get rid of the operand to the pattern. llvm-svn: 119607
2010-11-18 02:38:26 +01:00
def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs) instruction form. llvm-svn: 116534
2010-10-15 00:57:13 +02:00
[(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
Requires<[IsARM]>, Sched<[WriteALU]>;
implement LDRB, LDRSB, LDRH and LDRSH llvm-svn: 30976
2006-10-16 19:17:22 +02:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// These aren't really mov instructions, but we have to define them this way
// due to flag operands.
added a skeleton of the ARM backend llvm-svn: 28301
2006-05-15 00:18:28 +02:00
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
let Defs = [CPSR] in {
ARM PseudoInst instructions don't need or use an assembler string. Get rid of the operand to the pattern. llvm-svn: 119607
2010-11-18 02:38:26 +01:00
def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs) instruction form. llvm-svn: 116534
2010-10-15 00:57:13 +02:00
[(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
Sched<[WriteALU]>, Requires<[IsARM]>;
ARM PseudoInst instructions don't need or use an assembler string. Get rid of the operand to the pattern. llvm-svn: 119607
2010-11-18 02:38:26 +01:00
def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs) instruction form. llvm-svn: 116534
2010-10-15 00:57:13 +02:00
[(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
Sched<[WriteALU]>, Requires<[IsARM]>;
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. llvm-svn: 41863
2007-09-11 21:55:27 +02:00
}
implement STRB and STRH llvm-svn: 31138
2006-10-23 22:34:27 +02:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
//===----------------------------------------------------------------------===//
// Extend Instructions.
//
initial implementation of ARMRegisterInfo::eliminateFrameIndex fixes test/Regression/CodeGen/ARM/ret_arg5.ll llvm-svn: 28854
2006-06-18 02:08:07 +02:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// Sign extenders
add mvn llvm-svn: 32454
2006-12-12 01:37:38 +01:00
ARM extend instructions simplification. Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. llvm-svn: 136225
2011-07-27 18:47:19 +02:00
def SXTB : AI_ext_rrot<0b01101010,
Fix zero and sign extension instructions scheduling itineraries. llvm-svn: 114780
2010-09-25 02:49:35 +02:00
"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
ARM extend instructions simplification. Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. llvm-svn: 136225
2011-07-27 18:47:19 +02:00
def SXTH : AI_ext_rrot<0b01101011,
Fix zero and sign extension instructions scheduling itineraries. llvm-svn: 114780
2010-09-25 02:49:35 +02:00
"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
add the eor (xor) instruction llvm-svn: 30189
2006-09-08 18:59:47 +02:00
ARM cleanup of remaining extend instructions. Refactor the rest of the extend instructions to not artificially distinguish between a rotate of zero and a rotate of any other value. Replace the by-zero versions with Pat<>'s for ISel. llvm-svn: 136226
2011-07-27 19:48:13 +02:00
def SXTAB : AI_exta_rrot<0b01101010,
Encode extend instructions; more clean up. llvm-svn: 58818
2008-11-06 23:15:19 +01:00
"sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
ARM cleanup of remaining extend instructions. Refactor the rest of the extend instructions to not artificially distinguish between a rotate of zero and a rotate of any other value. Replace the by-zero versions with Pat<>'s for ISel. llvm-svn: 136226
2011-07-27 19:48:13 +02:00
def SXTAH : AI_exta_rrot<0b01101011,
Encode extend instructions; more clean up. llvm-svn: 58818
2008-11-06 23:15:19 +01:00
"sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
Implement SELECT_CC (f32/f64) for ARM. llvm-svn: 32762
2006-12-28 14:11:14 +01:00
[ARM] Improve sxta{b|h} and uxta{b|h} tests Created a Thumb2 predicated pattern matcher that uses Thumb2 and HasT2ExtractPack and used it to redefine the patterns for sxta{b|h} and uxta{b|h}. Also used the similar patterns to fill in isel pattern gaps for the corresponding instructions in the ARM backend. The patch is mainly changes to tests since most of this functionality appears not to have been tested. Differential Revision: https://reviews.llvm.org/D23273 llvm-svn: 278207
2016-08-10 11:34:34 +02:00
def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)),
(SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot),
i16)),
(SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
ARM extend instructions simplification. Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. llvm-svn: 136225
2011-07-27 18:47:19 +02:00
def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
def : ARMV6Pat<(int_arm_sxtb16 GPR:$Src),
(SXTB16 GPR:$Src, 0)>;
[ARM] Rotated operand patterns for *xtb16 Add intrinsic isel patterns for sxtb16, sxtab16, uxtb16 and uxtab16 so that they can perform a ror. Differential Revision: https://reviews.llvm.org/D51034 llvm-svn: 340405
2018-08-22 14:58:36 +02:00
def : ARMV6Pat<(int_arm_sxtb16 (rotr GPR:$Src, rot_imm:$rot)),
(SXTB16 GPR:$Src, rot_imm:$rot)>;
Added SEL, SXTB16, SXTAB16, UXTAB16, SMMULR, SMMLAR, SMMLSR, SMUAD, and SMUSD, for disassembly only. llvm-svn: 96806
2010-02-22 22:50:40 +01:00
ARM cleanup of remaining extend instructions. Refactor the rest of the extend instructions to not artificially distinguish between a rotate of zero and a rotate of any other value. Replace the by-zero versions with Pat<>'s for ISel. llvm-svn: 136226
2011-07-27 19:48:13 +02:00
def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, GPR:$RHS),
(SXTAB16 GPR:$LHS, GPR:$RHS, 0)>;
[ARM] Rotated operand patterns for *xtb16 Add intrinsic isel patterns for sxtb16, sxtab16, uxtb16 and uxtab16 so that they can perform a ror. Differential Revision: https://reviews.llvm.org/D51034 llvm-svn: 340405
2018-08-22 14:58:36 +02:00
def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)),
(SXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>;
Implement SELECT_CC (f32/f64) for ARM. llvm-svn: 32762
2006-12-28 14:11:14 +01:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// Zero extenders
initial support for select llvm-svn: 29802
2006-08-22 00:00:32 +02:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
let AddedComplexity = 16 in {
ARM extend instructions simplification. Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. llvm-svn: 136225
2011-07-27 18:47:19 +02:00
def UXTB : AI_ext_rrot<0b01101110,
Fix zero and sign extension instructions scheduling itineraries. llvm-svn: 114780
2010-09-25 02:49:35 +02:00
"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
ARM extend instructions simplification. Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. llvm-svn: 136225
2011-07-27 18:47:19 +02:00
def UXTH : AI_ext_rrot<0b01101111,
Fix zero and sign extension instructions scheduling itineraries. llvm-svn: 114780
2010-09-25 02:49:35 +02:00
"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
ARM extend instructions simplification. Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. llvm-svn: 136225
2011-07-27 18:47:19 +02:00
def UXTB16 : AI_ext_rrot<0b01101100,
Fix zero and sign extension instructions scheduling itineraries. llvm-svn: 114780
2010-09-25 02:49:35 +02:00
"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
implement SRL and MUL llvm-svn: 30262
2006-09-11 21:24:19 +02:00
ARM mode version of r109693. Remove incorrect substitution pattern for UXTB16. It wrongly assumed the input shift was actually a rotate. rdar://8240138 llvm-svn: 109696
2010-07-29 01:25:44 +02:00
// FIXME: This pattern incorrectly assumes the shl operator is a rotate.
// The transformation should probably be done as a combiner action
// instead so we can include a check for masking back in the upper
// eight bits of the source into the lower eight bits of the result.
//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
ARM cleanup of rot_imm encoding. Start of cleaning this up a bit. First step is to remove the encoder hook by storing the operand as the bits it'll actually encode to so it can just be directly used. Map it to the assembly source values 8/16/24 when we print it. llvm-svn: 136152
2011-07-26 23:28:43 +02:00
// (UXTB16r_rot GPR:$Src, 3)>;
Add explicit types for shift count constants. This is in preparation for another change that makes the types ambiguous (at least as far as tablegen is concerned). llvm-svn: 73909
2009-06-23 00:08:29 +02:00
def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
ARM extend instructions simplification. Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. llvm-svn: 136225
2011-07-27 18:47:19 +02:00
(UXTB16 GPR:$Src, 1)>;
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
def : ARMV6Pat<(int_arm_uxtb16 GPR:$Src),
(UXTB16 GPR:$Src, 0)>;
[ARM] Rotated operand patterns for *xtb16 Add intrinsic isel patterns for sxtb16, sxtab16, uxtb16 and uxtab16 so that they can perform a ror. Differential Revision: https://reviews.llvm.org/D51034 llvm-svn: 340405
2018-08-22 14:58:36 +02:00
def : ARMV6Pat<(int_arm_uxtb16 (rotr GPR:$Src, rot_imm:$rot)),
(UXTB16 GPR:$Src, rot_imm:$rot)>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
ARM cleanup of remaining extend instructions. Refactor the rest of the extend instructions to not artificially distinguish between a rotate of zero and a rotate of any other value. Replace the by-zero versions with Pat<>'s for ISel. llvm-svn: 136226
2011-07-27 19:48:13 +02:00
def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
ARM cleanup of remaining extend instructions. Refactor the rest of the extend instructions to not artificially distinguish between a rotate of zero and a rotate of any other value. Replace the by-zero versions with Pat<>'s for ISel. llvm-svn: 136226
2011-07-27 19:48:13 +02:00
def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
[ARM] Improve sxta{b|h} and uxta{b|h} tests Created a Thumb2 predicated pattern matcher that uses Thumb2 and HasT2ExtractPack and used it to redefine the patterns for sxta{b|h} and uxta{b|h}. Also used the similar patterns to fill in isel pattern gaps for the corresponding instructions in the ARM backend. The patch is mainly changes to tests since most of this functionality appears not to have been tested. Differential Revision: https://reviews.llvm.org/D23273 llvm-svn: 278207
2016-08-10 11:34:34 +02:00
def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)),
(UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)),
(UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
implement smull and umull llvm-svn: 30975
2006-10-16 18:33:29 +02:00
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
ARM cleanup of remaining extend instructions. Refactor the rest of the extend instructions to not artificially distinguish between a rotate of zero and a rotate of any other value. Replace the by-zero versions with Pat<>'s for ISel. llvm-svn: 136226
2011-07-27 19:48:13 +02:00
def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, GPR:$RHS),
(UXTAB16 GPR:$LHS, GPR:$RHS, 0)>;
[ARM] Rotated operand patterns for *xtb16 Add intrinsic isel patterns for sxtb16, sxtab16, uxtb16 and uxtab16 so that they can perform a ror. Differential Revision: https://reviews.llvm.org/D51034 llvm-svn: 340405
2018-08-22 14:58:36 +02:00
def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)),
(UXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>;
add isTerminatortto b and bcond llvm-svn: 31036
2006-10-18 18:20:57 +02:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
def SBFX : I<(outs GPRnopc:$Rd),
(ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
ARM mode encoding information for UBFX and SBFX instructions. llvm-svn: 116588
2010-10-15 19:15:16 +02:00
"sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. llvm-svn: 84009
2009-10-13 20:59:48 +02:00
Requires<[IsARM, HasV6T2]> {
ARM mode encoding information for UBFX and SBFX instructions. llvm-svn: 116588
2010-10-15 19:15:16 +02:00
bits<4> Rd;
bits<4> Rn;
bits<5> lsb;
bits<5> width;
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. llvm-svn: 84009
2009-10-13 20:59:48 +02:00
let Inst{27-21} = 0b0111101;
let Inst{6-4} = 0b101;
ARM mode encoding information for UBFX and SBFX instructions. llvm-svn: 116588
2010-10-15 19:15:16 +02:00
let Inst{20-16} = width;
let Inst{15-12} = Rd;
let Inst{11-7} = lsb;
let Inst{3-0} = Rn;
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. llvm-svn: 84009
2009-10-13 20:59:48 +02:00
}
ARM: mark UBFX as not allowing PC. Strictly, it's unpredictable. But we don't quite model that yet and an error is better than ignoring the issue. This one somehow got left out before though. rdar://problem/15997748 llvm-svn: 211490
2014-06-23 11:20:02 +02:00
def UBFX : I<(outs GPRnopc:$Rd),
(ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
ARM mode encoding information for UBFX and SBFX instructions. llvm-svn: 116588
2010-10-15 19:15:16 +02:00
"ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. llvm-svn: 84009
2009-10-13 20:59:48 +02:00
Requires<[IsARM, HasV6T2]> {
ARM mode encoding information for UBFX and SBFX instructions. llvm-svn: 116588
2010-10-15 19:15:16 +02:00
bits<4> Rd;
bits<4> Rn;
bits<5> lsb;
bits<5> width;
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. llvm-svn: 84009
2009-10-13 20:59:48 +02:00
let Inst{27-21} = 0b0111111;
let Inst{6-4} = 0b101;
ARM mode encoding information for UBFX and SBFX instructions. llvm-svn: 116588
2010-10-15 19:15:16 +02:00
let Inst{20-16} = width;
let Inst{15-12} = Rd;
let Inst{11-7} = lsb;
let Inst{3-0} = Rn;
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. llvm-svn: 84009
2009-10-13 20:59:48 +02:00
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
//===----------------------------------------------------------------------===//
// Arithmetic Instructions.
//
This reapplies r281304. The issue was that I had missed to copy the new isAdd field in the tablegen data structure. llvm-svn: 281447
2016-09-14 10:20:03 +02:00
let isAdd = 1 in
Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right) llvm-svn: 57524
2008-10-14 22:36:24 +02:00
defm ADD : AsI1_bin_irs<0b0100, "add",
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
IIC_iALUi, IIC_iALUr, IIC_iALUsr, add, 1>;
Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right) llvm-svn: 57524
2008-10-14 22:36:24 +02:00
defm SUB : AsI1_bin_irs<0b0010, "sub",
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
IIC_iALUi, IIC_iALUr, IIC_iALUsr, sub>;
implement unconditional branches fix select.ll llvm-svn: 30186
2006-09-08 14:47:03 +02:00
Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. llvm-svn: 37895
2007-07-05 09:13:32 +02:00
// ADD and SUB with 's' bit set.
Lower ARM adds/subs to add/sub after adding optional CPSR operand. This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. llvm-svn: 140228
2011-09-21 04:20:46 +02:00
//
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
2011-10-18 21:18:52 +02:00
// Currently, ADDS/SUBS are pseudo opcodes that exist only in the
// selection DAG. They are "lowered" to real ADD/SUB opcodes by
Lower ARM adds/subs to add/sub after adding optional CPSR operand. This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. llvm-svn: 140228
2011-09-21 04:20:46 +02:00
// AdjustInstrPostInstrSelection where we determine whether or not to
// set the "s" bit based on CPSR liveness.
//
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
2011-10-18 21:18:52 +02:00
// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
Lower ARM adds/subs to add/sub after adding optional CPSR operand. This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. llvm-svn: 140228
2011-09-21 04:20:46 +02:00
// support for an optional CPSR definition that corresponds to the DAG
// node's second value. We can then eliminate the implicit def of CPSR.
This reapplies r281304. The issue was that I had missed to copy the new isAdd field in the tablegen data structure. llvm-svn: 281447
2016-09-14 10:20:03 +02:00
let isAdd = 1 in
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMaddc, 1>;
defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>;
Mark these instructions clobbersPred. They modify the condition code register. llvm-svn: 37468
2007-06-06 12:17:05 +02:00
ARM: use target-specific SUBS node when combining cmp with cmov. This has two positive effects. First, using a custom node prevents recombination leading to an infinite loop since the output DAG is notionally a little more complex than the input one. Using a flag-setting instruction also allows the subtraction to be folded with the related comparison more easily. https://reviews.llvm.org/D53190 llvm-svn: 348122
2018-12-03 12:16:21 +01:00
def : ARMPat<(ARMsubs GPR:$Rn, mod_imm:$imm), (SUBSri $Rn, mod_imm:$imm)>;
def : ARMPat<(ARMsubs GPR:$Rn, GPR:$Rm), (SUBSrr $Rn, $Rm)>;
def : ARMPat<(ARMsubs GPR:$Rn, so_reg_imm:$shift),
(SUBSrsi $Rn, so_reg_imm:$shift)>;
def : ARMPat<(ARMsubs GPR:$Rn, so_reg_reg:$shift),
(SUBSrsr $Rn, so_reg_reg:$shift)>;
This reapplies r281304. The issue was that I had missed to copy the new isAdd field in the tablegen data structure. llvm-svn: 281447
2016-09-14 10:20:03 +02:00
let isAdd = 1 in
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
defm ADC : AI1_adde_sube_irs<0b0101, "adc", ARMadde, 1>;
defm SBC : AI1_adde_sube_irs<0b0110, "sbc", ARMsube>;
ARM/MC: Mark several '...S' instructions as codegen only, they aren't real instructions but are restricted pseudo forms. llvm-svn: 123176
2011-01-10 16:26:35 +01:00
ARM: Tidy up. Remove unused template parameters. llvm-svn: 161222
2012-08-03 00:08:27 +02:00
defm RSB : AsI1_rbin_irs<0b0011, "rsb",
IIC_iALUi, IIC_iALUr, IIC_iALUsr,
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
sub>;
Fix fall outs from my recent change on how carry bit is modeled during isel. Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well. Also fix isel hook to correctly set the optional operand. rdar://10073745 llvm-svn: 139157
2011-09-06 20:52:20 +02:00
// FIXME: Eliminate them if we can write def : Pat patterns which defines
// CPSR and the implicit def of CPSR is not needed.
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>;
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
defm RSC : AI1_rsc_irs<0b0111, "rsc", ARMsube>;
Mark these instructions clobbersPred. They modify the condition code register. llvm-svn: 37468
2007-06-06 12:17:05 +02:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
Improve 64-subtraction of immediates when parts of the immediate can fit in the literal field of an instruction. E.g., long long foo(long long a) { return a - 734439407618LL; } rdar://7038284 llvm-svn: 108339
2010-07-14 19:45:16 +02:00
// The assume-no-carry-in form uses the negation of the input since add/sub
// assume opposite meanings of the carry flag (i.e., carry == !borrow).
// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
// details.
[ARM] Cleanup so_imm* tblgen defintions No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
2015-01-06 16:55:09 +01:00
def : ARMPat<(add GPR:$src, mod_imm_neg:$imm),
(SUBri GPR:$src, mod_imm_neg:$imm)>;
def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm),
(SUBSri GPR:$src, mod_imm_neg:$imm)>;
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
2011-08-30 03:34:54 +02:00
(sub X, imm) gets canonicalized to (add X, -imm) There are patterns to handle immediates when they fit in the immediate field. e.g. %sub = add i32 %x, -123 => sub r0, r0, #123 Add patterns to catch immediates that do not fit but should be materialized with a single movw instruction rather than movw + movt pair. e.g. %sub = add i32 %x, -65535 => movw r1, #65535 sub r0, r0, r1 rdar://11726136 llvm-svn: 159057
2012-06-23 02:29:06 +02:00
def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
MOVi16 (movw) is only legal on cpus with V6T2 support. rdar://12300648 llvm-svn: 164169
2012-09-18 23:24:16 +02:00
(SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
Requires<[IsARM, HasV6T2]>;
(sub X, imm) gets canonicalized to (add X, -imm) There are patterns to handle immediates when they fit in the immediate field. e.g. %sub = add i32 %x, -123 => sub r0, r0, #123 Add patterns to catch immediates that do not fit but should be materialized with a single movw instruction rather than movw + movt pair. e.g. %sub = add i32 %x, -65535 => movw r1, #65535 sub r0, r0, r1 rdar://11726136 llvm-svn: 159057
2012-06-23 02:29:06 +02:00
def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
MOVi16 (movw) is only legal on cpus with V6T2 support. rdar://12300648 llvm-svn: 164169
2012-09-18 23:24:16 +02:00
(SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
Requires<[IsARM, HasV6T2]>;
(sub X, imm) gets canonicalized to (add X, -imm) There are patterns to handle immediates when they fit in the immediate field. e.g. %sub = add i32 %x, -123 => sub r0, r0, #123 Add patterns to catch immediates that do not fit but should be materialized with a single movw instruction rather than movw + movt pair. e.g. %sub = add i32 %x, -65535 => movw r1, #65535 sub r0, r0, r1 rdar://11726136 llvm-svn: 159057
2012-06-23 02:29:06 +02:00
Improve 64-subtraction of immediates when parts of the immediate can fit in the literal field of an instruction. E.g., long long foo(long long a) { return a - 734439407618LL; } rdar://7038284 llvm-svn: 108339
2010-07-14 19:45:16 +02:00
// The with-carry-in form matches bitwise not instead of the negation.
// Effectively, the inverse interpretation of the carry flag already accounts
// for part of the negation.
[ARM] Cleanup so_imm* tblgen defintions No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
2015-01-06 16:55:09 +01:00
def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR),
(SBCri GPR:$src, mod_imm_not:$imm)>;
Fix a miscompilation caused by a typo. When turning a adde with negative value into a sbc with a positive number, the immediate should be complemented, not negated. Also added a missing pattern for ARM codegen. rdar://12559385 llvm-svn: 166613
2012-10-24 21:53:01 +02:00
def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
Only emit movw on ARMv6T2+ Fix PR18364. Patch by Dimitry Andric. llvm-svn: 216989
2014-09-03 00:45:13 +02:00
(SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
Requires<[IsARM, HasV6T2]>;
compare doubles llvm-svn: 30856
2006-10-10 18:33:47 +02:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// Note: These are implemented in C++ code, because they have to generate
// ADD/SUBrs instructions, which use a complex pattern that a xform function
// cannot produce.
// (mul X, 2^n+1) -> (add (X << n), X)
// (mul X, 2^n-1) -> (rsb X, (X << n))
add FCPYS and FCPYD llvm-svn: 30995
2006-10-17 15:13:23 +02:00
Clean up a few more comments. These instruction definitions are for the assembler, too, not just the disassembler. llvm-svn: 135781
2011-07-22 20:06:01 +02:00
// ARM Arithmetic Instruction
Try to factorize the specification of saturating add/subtract operations a bit, as suggested by Bob Wilson. llvm-svn: 96153
2010-02-14 07:32:20 +01:00
// GPR:$dst = GPR:$a op GPR:$b
Encoding information for the various ARM saturating add/sub instructions. llvm-svn: 116612
2010-10-15 21:49:46 +02:00
class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
Clean up a few more comments. These instruction definitions are for the assembler, too, not just the disassembler. llvm-svn: 135781
2011-07-22 20:06:01 +02:00
list<dag> pattern = [],
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
string asm = "\t$Rd, $Rn, $Rm">
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
: AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
Sched<[WriteALU, ReadALU, ReadALU]> {
Encoding information for the various ARM saturating add/sub instructions. llvm-svn: 116612
2010-10-15 21:49:46 +02:00
bits<4> Rn;
Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm", qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This is described in ARM manuals and matches the encoding used by the gnu assembler. llvm-svn: 123975
2011-01-21 15:07:40 +01:00
bits<4> Rd;
Encoding information for the various ARM saturating add/sub instructions. llvm-svn: 116612
2010-10-15 21:49:46 +02:00
bits<4> Rm;
Added a bunch of saturating add/subtract instructions for disassembly only. llvm-svn: 96063
2010-02-13 02:21:01 +01:00
let Inst{27-20} = op27_20;
Encoding information for the various ARM saturating add/sub instructions. llvm-svn: 116612
2010-10-15 21:49:46 +02:00
let Inst{11-4} = op11_4;
let Inst{19-16} = Rn;
let Inst{15-12} = Rd;
let Inst{3-0} = Rm;
Tidy up. 80 columns, whitespace, et. al. llvm-svn: 155399
2012-04-24 00:04:10 +02:00
Added support for handling unpredictable arithmetic instructions on ARM. llvm-svn: 154100
2012-04-05 18:13:15 +02:00
let Unpredictable{11-8} = 0b1111;
Added a bunch of saturating add/subtract instructions for disassembly only. llvm-svn: 96063
2010-02-13 02:21:01 +01:00
}
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
// Wrappers around the AAI class
class AAIRevOpr<bits<8> op27_20, bits<8> op11_4, string opc,
list<dag> pattern = []>
: AAI<op27_20, op11_4, opc,
pattern,
(ins GPRnopc:$Rm, GPRnopc:$Rn),
"\t$Rd, $Rm, $Rn">;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
class AAIIntrinsic<bits<8> op27_20, bits<8> op11_4, string opc,
Intrinsic intrinsic>
: AAI<op27_20, op11_4, opc,
[(set GPRnopc:$Rd, (intrinsic GPRnopc:$Rn, GPRnopc:$Rm))]>;
// Saturating add/subtract
let hasSideEffects = 1 in {
def QADD8 : AAIIntrinsic<0b01100010, 0b11111001, "qadd8", int_arm_qadd8>;
def QADD16 : AAIIntrinsic<0b01100010, 0b11110001, "qadd16", int_arm_qadd16>;
def QSUB16 : AAIIntrinsic<0b01100010, 0b11110111, "qsub16", int_arm_qsub16>;
def QSUB8 : AAIIntrinsic<0b01100010, 0b11111111, "qsub8", int_arm_qsub8>;
def QDADD : AAIRevOpr<0b00010100, 0b00000101, "qdadd",
[(set GPRnopc:$Rd, (int_arm_qadd (int_arm_qadd GPRnopc:$Rm,
GPRnopc:$Rm),
GPRnopc:$Rn))]>;
def QDSUB : AAIRevOpr<0b00010110, 0b00000101, "qdsub",
[(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm,
(int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>;
def QSUB : AAIRevOpr<0b00010010, 0b00000101, "qsub",
[(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))]>;
ARM: fix CPS decoding when ambiguous with QADD Handle the case when the disassembler table can't tell the difference between some encodings of QADD and CPS. Add some necessary safe guards in CPS decoding as well. llvm-svn: 183610
2013-06-08 15:38:52 +02:00
let DecoderMethod = "DecodeQADDInstruction" in
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
def QADD : AAIRevOpr<0b00010000, 0b00000101, "qadd",
[(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))]>;
}
def UQADD16 : AAIIntrinsic<0b01100110, 0b11110001, "uqadd16", int_arm_uqadd16>;
def UQADD8 : AAIIntrinsic<0b01100110, 0b11111001, "uqadd8", int_arm_uqadd8>;
def UQSUB16 : AAIIntrinsic<0b01100110, 0b11110111, "uqsub16", int_arm_uqsub16>;
def UQSUB8 : AAIIntrinsic<0b01100110, 0b11111111, "uqsub8", int_arm_uqsub8>;
def QASX : AAIIntrinsic<0b01100010, 0b11110011, "qasx", int_arm_qasx>;
def QSAX : AAIIntrinsic<0b01100010, 0b11110101, "qsax", int_arm_qsax>;
def UQASX : AAIIntrinsic<0b01100110, 0b11110011, "uqasx", int_arm_uqasx>;
def UQSAX : AAIIntrinsic<0b01100110, 0b11110101, "uqsax", int_arm_uqsax>;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
Clean up a few more comments. These instruction definitions are for the assembler, too, not just the disassembler. llvm-svn: 135781
2011-07-22 20:06:01 +02:00
// Signed/Unsigned add/subtract
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
def SASX : AAIIntrinsic<0b01100001, 0b11110011, "sasx", int_arm_sasx>;
def SADD16 : AAIIntrinsic<0b01100001, 0b11110001, "sadd16", int_arm_sadd16>;
def SADD8 : AAIIntrinsic<0b01100001, 0b11111001, "sadd8", int_arm_sadd8>;
def SSAX : AAIIntrinsic<0b01100001, 0b11110101, "ssax", int_arm_ssax>;
def SSUB16 : AAIIntrinsic<0b01100001, 0b11110111, "ssub16", int_arm_ssub16>;
def SSUB8 : AAIIntrinsic<0b01100001, 0b11111111, "ssub8", int_arm_ssub8>;
def UASX : AAIIntrinsic<0b01100101, 0b11110011, "uasx", int_arm_uasx>;
def UADD16 : AAIIntrinsic<0b01100101, 0b11110001, "uadd16", int_arm_uadd16>;
def UADD8 : AAIIntrinsic<0b01100101, 0b11111001, "uadd8", int_arm_uadd8>;
def USAX : AAIIntrinsic<0b01100101, 0b11110101, "usax", int_arm_usax>;
def USUB16 : AAIIntrinsic<0b01100101, 0b11110111, "usub16", int_arm_usub16>;
def USUB8 : AAIIntrinsic<0b01100101, 0b11111111, "usub8", int_arm_usub8>;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
Clean up a few more comments. These instruction definitions are for the assembler, too, not just the disassembler. llvm-svn: 135781
2011-07-22 20:06:01 +02:00
// Signed/Unsigned halving add/subtract
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
def SHASX : AAIIntrinsic<0b01100011, 0b11110011, "shasx", int_arm_shasx>;
def SHADD16 : AAIIntrinsic<0b01100011, 0b11110001, "shadd16", int_arm_shadd16>;
def SHADD8 : AAIIntrinsic<0b01100011, 0b11111001, "shadd8", int_arm_shadd8>;
def SHSAX : AAIIntrinsic<0b01100011, 0b11110101, "shsax", int_arm_shsax>;
def SHSUB16 : AAIIntrinsic<0b01100011, 0b11110111, "shsub16", int_arm_shsub16>;
def SHSUB8 : AAIIntrinsic<0b01100011, 0b11111111, "shsub8", int_arm_shsub8>;
def UHASX : AAIIntrinsic<0b01100111, 0b11110011, "uhasx", int_arm_uhasx>;
def UHADD16 : AAIIntrinsic<0b01100111, 0b11110001, "uhadd16", int_arm_uhadd16>;
def UHADD8 : AAIIntrinsic<0b01100111, 0b11111001, "uhadd8", int_arm_uhadd8>;
def UHSAX : AAIIntrinsic<0b01100111, 0b11110101, "uhsax", int_arm_uhsax>;
def UHSUB16 : AAIIntrinsic<0b01100111, 0b11110111, "uhsub16", int_arm_uhsub16>;
def UHSUB8 : AAIIntrinsic<0b01100111, 0b11111111, "uhsub8", int_arm_uhsub8>;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
Remove no-longer-true comments. These are for the assembler, also. llvm-svn: 137375
2011-08-12 00:30:30 +02:00
// Unsigned Sum of Absolute Differences [and Accumulate].
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
ARM encoding information for [SU]SAT* instructions. llvm-svn: 116768
2010-10-19 01:35:38 +02:00
def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
MulFrm /* for convenience */, NoItinerary, "usad8",
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
"\t$Rd, $Rn, $Rm",
[(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
ARM encoding information for [SU]SAT* instructions. llvm-svn: 116768
2010-10-19 01:35:38 +02:00
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
let Inst{27-20} = 0b01111000;
let Inst{15-12} = 0b1111;
let Inst{7-4} = 0b0001;
ARM encoding information for [SU]SAT* instructions. llvm-svn: 116768
2010-10-19 01:35:38 +02:00
let Inst{19-16} = Rd;
let Inst{11-8} = Rm;
let Inst{3-0} = Rn;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
}
ARM encoding information for [SU]SAT* instructions. llvm-svn: 116768
2010-10-19 01:35:38 +02:00
def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
MulFrm /* for convenience */, NoItinerary, "usada8",
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
"\t$Rd, $Rn, $Rm, $Ra",
[(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
ARM encoding information for [SU]SAT* instructions. llvm-svn: 116768
2010-10-19 01:35:38 +02:00
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
bits<4> Ra;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
let Inst{27-20} = 0b01111000;
let Inst{7-4} = 0b0001;
ARM encoding information for [SU]SAT* instructions. llvm-svn: 116768
2010-10-19 01:35:38 +02:00
let Inst{19-16} = Rd;
let Inst{15-12} = Ra;
let Inst{11-8} = Rm;
let Inst{3-0} = Rn;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
}
Remove no-longer-true comments. These are for the assembler, also. llvm-svn: 137375
2011-08-12 00:30:30 +02:00
// Signed/Unsigned saturate
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
def SSAT : AI<(outs GPRnopc:$Rd),
(ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
[ARM] Saturation instructions are DSP-only The saturation instructions appeared in v6T2, with DSP extensions, but they were being accepted / generated on any, with the new introduction of the saturation detection in the back-end. This commit restricts the usage to DSP-enable only cores. Fixes PR28607. llvm-svn: 276701
2016-07-26 00:25:25 +02:00
SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>,
[ARM] Some saturation instructions not DSP-only Summary: Commit 276701 requires that targets have the DSP extensions to use certain saturating instructions. This requires some corrections. For ARM ISA the instructions in question are available in all v6* architectures. For Thumb2, the instructions in question are available from v6T2. SSAT and USAT are part of the base architecture while SSAT16 and USAT16 require the DSP extensions. Reviewers: rengolin Subscribers: aemerson, rengolin, samparker, llvm-commits Differential Revision: https://reviews.llvm.org/D23010 llvm-svn: 277439
2016-08-02 12:04:03 +02:00
Requires<[IsARM,HasV6]>{
ARM encoding information for [SU]SAT* instructions. llvm-svn: 116768
2010-10-19 01:35:38 +02:00
bits<4> Rd;
bits<5> sat_imm;
bits<4> Rn;
bits<8> sh;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
let Inst{27-21} = 0b0110101;
Move the ARM SSAT and USAT optional shift amount operand out of the instruction opcode. This also fixes part of PR7792. llvm-svn: 110875
2010-08-12 01:10:46 +02:00
let Inst{5-4} = 0b01;
ARM encoding information for [SU]SAT* instructions. llvm-svn: 116768
2010-10-19 01:35:38 +02:00
let Inst{20-16} = sat_imm;
let Inst{15-12} = Rd;
ARM assembly parsing and encoding for SSAT instruction. Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the shift operand to correctly handle the allowed shift types and immediate ranges and issue meaningful diagnostics when an illegal value or shift type is specified. Add aliases to parse an ommitted shift operand (default value of 'lsl #0'). Add tests for diagnostics and proper encoding. llvm-svn: 135990
2011-07-26 00:20:28 +02:00
let Inst{11-7} = sh{4-0};
let Inst{6} = sh{5};
ARM encoding information for [SU]SAT* instructions. llvm-svn: 116768
2010-10-19 01:35:38 +02:00
let Inst{3-0} = Rn;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
}
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
def SSAT16 : AI<(outs GPRnopc:$Rd),
(ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
[ARM] Saturation instructions are DSP-only The saturation instructions appeared in v6T2, with DSP extensions, but they were being accepted / generated on any, with the new introduction of the saturation detection in the back-end. This commit restricts the usage to DSP-enable only cores. Fixes PR28607. llvm-svn: 276701
2016-07-26 00:25:25 +02:00
NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
[ARM] Some saturation instructions not DSP-only Summary: Commit 276701 requires that targets have the DSP extensions to use certain saturating instructions. This requires some corrections. For ARM ISA the instructions in question are available in all v6* architectures. For Thumb2, the instructions in question are available from v6T2. SSAT and USAT are part of the base architecture while SSAT16 and USAT16 require the DSP extensions. Reviewers: rengolin Subscribers: aemerson, rengolin, samparker, llvm-commits Differential Revision: https://reviews.llvm.org/D23010 llvm-svn: 277439
2016-08-02 12:04:03 +02:00
Requires<[IsARM,HasV6]>{
ARM encoding information for [SU]SAT* instructions. llvm-svn: 116768
2010-10-19 01:35:38 +02:00
bits<4> Rd;
bits<4> sat_imm;
bits<4> Rn;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
let Inst{27-20} = 0b01101010;
ARM encoding information for [SU]SAT* instructions. llvm-svn: 116768
2010-10-19 01:35:38 +02:00
let Inst{11-4} = 0b11110011;
let Inst{15-12} = Rd;
let Inst{19-16} = sat_imm;
let Inst{3-0} = Rn;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
}
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
def USAT : AI<(outs GPRnopc:$Rd),
(ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
[ARM] Saturation instructions are DSP-only The saturation instructions appeared in v6T2, with DSP extensions, but they were being accepted / generated on any, with the new introduction of the saturation detection in the back-end. This commit restricts the usage to DSP-enable only cores. Fixes PR28607. llvm-svn: 276701
2016-07-26 00:25:25 +02:00
SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>,
[ARM] Some saturation instructions not DSP-only Summary: Commit 276701 requires that targets have the DSP extensions to use certain saturating instructions. This requires some corrections. For ARM ISA the instructions in question are available in all v6* architectures. For Thumb2, the instructions in question are available from v6T2. SSAT and USAT are part of the base architecture while SSAT16 and USAT16 require the DSP extensions. Reviewers: rengolin Subscribers: aemerson, rengolin, samparker, llvm-commits Differential Revision: https://reviews.llvm.org/D23010 llvm-svn: 277439
2016-08-02 12:04:03 +02:00
Requires<[IsARM,HasV6]> {
ARM encoding information for [SU]SAT* instructions. llvm-svn: 116768
2010-10-19 01:35:38 +02:00
bits<4> Rd;
bits<5> sat_imm;
bits<4> Rn;
bits<8> sh;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
let Inst{27-21} = 0b0110111;
Move the ARM SSAT and USAT optional shift amount operand out of the instruction opcode. This also fixes part of PR7792. llvm-svn: 110875
2010-08-12 01:10:46 +02:00
let Inst{5-4} = 0b01;
ARM encoding information for [SU]SAT* instructions. llvm-svn: 116768
2010-10-19 01:35:38 +02:00
let Inst{15-12} = Rd;
ARM assembly parsing and encoding for SSAT instruction. Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the shift operand to correctly handle the allowed shift types and immediate ranges and issue meaningful diagnostics when an illegal value or shift type is specified. Add aliases to parse an ommitted shift operand (default value of 'lsl #0'). Add tests for diagnostics and proper encoding. llvm-svn: 135990
2011-07-26 00:20:28 +02:00
let Inst{11-7} = sh{4-0};
let Inst{6} = sh{5};
ARM encoding information for [SU]SAT* instructions. llvm-svn: 116768
2010-10-19 01:35:38 +02:00
let Inst{20-16} = sat_imm;
let Inst{3-0} = Rn;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
}
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
def USAT16 : AI<(outs GPRnopc:$Rd),
Make the USAT16 operand decoder auto-generate-able. llvm-svn: 137371
2011-08-12 00:10:11 +02:00
(ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
[ARM] Saturation instructions are DSP-only The saturation instructions appeared in v6T2, with DSP extensions, but they were being accepted / generated on any, with the new introduction of the saturation detection in the back-end. This commit restricts the usage to DSP-enable only cores. Fixes PR28607. llvm-svn: 276701
2016-07-26 00:25:25 +02:00
NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>,
[ARM] Some saturation instructions not DSP-only Summary: Commit 276701 requires that targets have the DSP extensions to use certain saturating instructions. This requires some corrections. For ARM ISA the instructions in question are available in all v6* architectures. For Thumb2, the instructions in question are available from v6T2. SSAT and USAT are part of the base architecture while SSAT16 and USAT16 require the DSP extensions. Reviewers: rengolin Subscribers: aemerson, rengolin, samparker, llvm-commits Differential Revision: https://reviews.llvm.org/D23010 llvm-svn: 277439
2016-08-02 12:04:03 +02:00
Requires<[IsARM,HasV6]>{
ARM encoding information for [SU]SAT* instructions. llvm-svn: 116768
2010-10-19 01:35:38 +02:00
bits<4> Rd;
bits<4> sat_imm;
bits<4> Rn;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
let Inst{27-20} = 0b01101110;
ARM encoding information for [SU]SAT* instructions. llvm-svn: 116768
2010-10-19 01:35:38 +02:00
let Inst{11-4} = 0b11110011;
let Inst{15-12} = Rd;
let Inst{19-16} = sat_imm;
let Inst{3-0} = Rn;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
}
add FCPYS and FCPYD llvm-svn: 30995
2006-10-17 15:13:23 +02:00
Fix mapping of @llvm.arm.ssat/usat intrinsics to ssat/usat instructions The mapping of these two intrinsics in ARMInstrInfo.td had a small omission which lead to their operands not being validated/transformed before being lowered into usat and ssat instructions. This can cause incorrect instructions to be emitted. I've also added tests for the remaining two saturating arithmatic intrinsics @llvm.arm.qadd and @llvm.arm.qsub as they are missing codegen tests. llvm-svn: 250697
2015-10-19 13:44:24 +02:00
def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos),
(SSAT imm1_32:$pos, GPRnopc:$a, 0)>;
def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos),
(USAT imm0_31:$pos, GPRnopc:$a, 0)>;
[ARM] Lower (select_cc k k (select_cc ~k ~k x)) into (SSAT l_k x) Summary: SSAT saturates an integer, making sure that its value lies within an interval [-k, k]. Since the constant is given to SSAT as the number of bytes set to one, k + 1 must be a power of 2, otherwise the optimization is not possible. Also, the select_cc must use < and > respectively so that they define an interval. Reviewers: mcrosier, jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D21372 llvm-svn: 273581
2016-06-23 18:53:49 +02:00
def : ARMPat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm),
(SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
[ARM] Lower unsigned saturation to USAT Summary: Implement lower of unsigned saturation on an interval [0, k] where k + 1 is a power of two using USAT instruction in a similar way to how [~k, k] is lowered using SSAT on ARM models that supports it. Patch by Marten Svanfeldt Reviewers: t.p.northover, pbarrio, eastig, SjoerdMeijer, javed.absar, fhahn Reviewed By: fhahn Subscribers: fhahn, aemerson, javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D41348 llvm-svn: 321164
2017-12-20 12:13:57 +01:00
def : ARMPat<(ARMusatnoshift GPRnopc:$Rn, imm0_31:$imm),
(USAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
def : ARMV6Pat<(int_arm_ssat16 GPRnopc:$a, imm1_16:$pos),
(SSAT16 imm1_16:$pos, GPRnopc:$a)>;
def : ARMV6Pat<(int_arm_usat16 GPRnopc:$a, imm0_15:$pos),
(USAT16 imm0_15:$pos, GPRnopc:$a)>;
Add builtins for ssat/usat, similar to RealView's __ssat and __usat intrinsics. llvm-svn: 109813
2010-07-30 00:48:09 +02:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
//===----------------------------------------------------------------------===//
// Bitwise Instructions.
//
add floating point registers implement SINT_TO_FP llvm-svn: 30673
2006-09-29 23:20:16 +02:00
Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right) llvm-svn: 57524
2008-10-14 22:36:24 +02:00
defm AND : AsI1_bin_irs<0b0000, "and",
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>;
Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right) llvm-svn: 57524
2008-10-14 22:36:24 +02:00
defm ORR : AsI1_bin_irs<0b1100, "orr",
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
IIC_iBITi, IIC_iBITr, IIC_iBITsr, or, 1>;
Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right) llvm-svn: 57524
2008-10-14 22:36:24 +02:00
defm EOR : AsI1_bin_irs<0b0001, "eor",
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
IIC_iBITi, IIC_iBITr, IIC_iBITsr, xor, 1>;
Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right) llvm-svn: 57524
2008-10-14 22:36:24 +02:00
defm BIC : AsI1_bin_irs<0b1110, "bic",
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub. llvm-svn: 115008
2010-09-29 02:27:46 +02:00
IIC_iBITi, IIC_iBITr, IIC_iBITsr,
ARM: Tidy up. Remove unused template parameters. llvm-svn: 161222
2012-08-03 00:08:27 +02:00
BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
add floating point registers implement SINT_TO_FP llvm-svn: 30673
2006-09-29 23:20:16 +02:00
Add fixme. llvm-svn: 136375
2011-07-28 21:46:12 +02:00
// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
// like in the actual instruction encoding. The complexity of mapping the mask
// to the lsb/msb pair should be handled by ISel, not encapsulated in the
// instruction description.
ARM Binary encoding information for BFC/BFI instructions. llvm-svn: 117072
2010-10-22 00:03:21 +02:00
def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
ARM Binary encoding information for BFC/BFI instructions. llvm-svn: 117072
2010-10-22 00:03:21 +02:00
"bfc", "\t$Rd, $imm", "$src = $Rd",
[(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
Add bfc to armv6t2. llvm-svn: 74868
2009-07-07 00:23:46 +02:00
Requires<[IsARM, HasV6T2]> {
ARM Binary encoding information for BFC/BFI instructions. llvm-svn: 117072
2010-10-22 00:03:21 +02:00
bits<4> Rd;
bits<10> imm;
Add bfc to armv6t2. llvm-svn: 74868
2009-07-07 00:23:46 +02:00
let Inst{27-21} = 0b0111110;
let Inst{6-0} = 0b0011111;
ARM Binary encoding information for BFC/BFI instructions. llvm-svn: 117072
2010-10-22 00:03:21 +02:00
let Inst{15-12} = Rd;
let Inst{11-7} = imm{4-0}; // lsb
Add fixme. llvm-svn: 136375
2011-07-28 21:46:12 +02:00
let Inst{20-16} = imm{9-5}; // msb
Add bfc to armv6t2. llvm-svn: 74868
2009-07-07 00:23:46 +02:00
}
Added BFI for disassembly only. A8.6.18 BFI - Bitfield insert (Encoding A1) llvm-svn: 96462
2010-02-17 07:31:48 +01:00
// A8.6.18 BFI - Bitfield insert (Encoding A1)
Tidy up. 80 columns. llvm-svn: 137277
2011-08-11 01:23:47 +02:00
def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
"bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
[(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
bf_inv_mask_imm:$imm))]>,
Requires<[IsARM, HasV6T2]> {
ARM Binary encoding information for BFC/BFI instructions. llvm-svn: 117072
2010-10-22 00:03:21 +02:00
bits<4> Rd;
bits<4> Rn;
bits<10> imm;
Added BFI for disassembly only. A8.6.18 BFI - Bitfield insert (Encoding A1) llvm-svn: 96462
2010-02-17 07:31:48 +01:00
let Inst{27-21} = 0b0111110;
let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
ARM Binary encoding information for BFC/BFI instructions. llvm-svn: 117072
2010-10-22 00:03:21 +02:00
let Inst{15-12} = Rd;
let Inst{11-7} = imm{4-0}; // lsb
let Inst{20-16} = imm{9-5}; // width
let Inst{3-0} = Rn;
Added BFI for disassembly only. A8.6.18 BFI - Bitfield insert (Encoding A1) llvm-svn: 96462
2010-02-17 07:31:48 +01:00
}
ARM binary encodings for MVN variants. llvm-svn: 117076
2010-10-22 00:19:32 +02:00
def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
"mvn", "\t$Rd, $Rm",
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
[(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
ARM binary encodings for MVN variants. llvm-svn: 117076
2010-10-22 00:19:32 +02:00
bits<4> Rd;
bits<4> Rm;
For MVNr and MVNs, we need to set Inst{25} = 0 so as not to confuse the decoder. llvm-svn: 94955
2010-01-31 12:22:28 +01:00
let Inst{25} = 0;
ARM binary encodings for MVN variants. llvm-svn: 117076
2010-10-22 00:19:32 +02:00
let Inst{19-16} = 0b0000;
My previous patch (r84124) for setting the encoding bits 4 and 7 of DPSoRegFrm was wrong and too aggressive in the sense that DPSoRegFrm includes both constant shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and Inst{7} = 0). The 'rr' fragment of the multiclass definitions actually means register/register with no shift, see A8-11. llvm-svn: 86319
2009-11-07 01:54:36 +01:00
let Inst{11-4} = 0b00000000;
ARM binary encodings for MVN variants. llvm-svn: 117076
2010-10-22 00:19:32 +02:00
let Inst{15-12} = Rd;
let Inst{3-0} = Rm;
[ARM] Add support for unpredictable MVN instructions. This fixes bugzilla 33011 https://bugs.llvm.org/show_bug.cgi?id=33011 Defines bits {19-16} as zero or unpredictable as specified by the ARM ARM in sections A8.8.116 and A8.8.117. It fixes also the usage of PC register as destination register for MVN register-shifted register version as specified in A8.8.117. Differential Revision: https://reviews.llvm.org/D41905 llvm-svn: 323954
2018-02-01 13:06:57 +01:00
let Unpredictable{19-16} = 0b1111;
Set instruction encoding bits 4 and 7 for ARM register-register and register-shifted-register instructions. Patch by Johnny Chen. llvm-svn: 84124
2009-10-14 21:00:24 +02:00
}
Tidy up. 80 columns. llvm-svn: 136705
2011-08-02 20:16:36 +02:00
def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
[(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
Sched<[WriteALU]> {
ARM binary encodings for MVN variants. llvm-svn: 117076
2010-10-22 00:19:32 +02:00
bits<4> Rd;
bits<12> shift;
For MVNr and MVNs, we need to set Inst{25} = 0 so as not to confuse the decoder. llvm-svn: 94955
2010-01-31 12:22:28 +01:00
let Inst{25} = 0;
ARM binary encodings for MVN variants. llvm-svn: 117076
2010-10-22 00:19:32 +02:00
let Inst{19-16} = 0b0000;
let Inst{15-12} = Rd;
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
let Inst{11-5} = shift{11-5};
let Inst{4} = 0;
let Inst{3-0} = shift{3-0};
[ARM] Add support for unpredictable MVN instructions. This fixes bugzilla 33011 https://bugs.llvm.org/show_bug.cgi?id=33011 Defines bits {19-16} as zero or unpredictable as specified by the ARM ARM in sections A8.8.116 and A8.8.117. It fixes also the usage of PC register as destination register for MVN register-shifted register version as specified in A8.8.117. Differential Revision: https://reviews.llvm.org/D41905 llvm-svn: 323954
2018-02-01 13:06:57 +01:00
let Unpredictable{19-16} = 0b1111;
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
}
[ARM] Add support for unpredictable MVN instructions. This fixes bugzilla 33011 https://bugs.llvm.org/show_bug.cgi?id=33011 Defines bits {19-16} as zero or unpredictable as specified by the ARM ARM in sections A8.8.116 and A8.8.117. It fixes also the usage of PC register as destination register for MVN register-shifted register version as specified in A8.8.117. Differential Revision: https://reviews.llvm.org/D41905 llvm-svn: 323954
2018-02-01 13:06:57 +01:00
def MVNsr : AsI1<0b1111, (outs GPRnopc:$Rd), (ins so_reg_reg:$shift),
Tidy up. 80 columns. llvm-svn: 136705
2011-08-02 20:16:36 +02:00
DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
[ARM] Add support for unpredictable MVN instructions. This fixes bugzilla 33011 https://bugs.llvm.org/show_bug.cgi?id=33011 Defines bits {19-16} as zero or unpredictable as specified by the ARM ARM in sections A8.8.116 and A8.8.117. It fixes also the usage of PC register as destination register for MVN register-shifted register version as specified in A8.8.117. Differential Revision: https://reviews.llvm.org/D41905 llvm-svn: 323954
2018-02-01 13:06:57 +01:00
[(set GPRnopc:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
Sched<[WriteALU]> {
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
bits<4> Rd;
bits<12> shift;
let Inst{25} = 0;
let Inst{19-16} = 0b0000;
let Inst{15-12} = Rd;
let Inst{11-8} = shift{11-8};
let Inst{7} = 0;
let Inst{6-5} = shift{6-5};
let Inst{4} = 1;
let Inst{3-0} = shift{3-0};
[ARM] Add support for unpredictable MVN instructions. This fixes bugzilla 33011 https://bugs.llvm.org/show_bug.cgi?id=33011 Defines bits {19-16} as zero or unpredictable as specified by the ARM ARM in sections A8.8.116 and A8.8.117. It fixes also the usage of PC register as destination register for MVN register-shifted register version as specified in A8.8.117. Differential Revision: https://reviews.llvm.org/D41905 llvm-svn: 323954
2018-02-01 13:06:57 +01:00
let Unpredictable{19-16} = 0b1111;
For MVNr and MVNs, we need to set Inst{25} = 0 so as not to confuse the decoder. llvm-svn: 94955
2010-01-31 12:22:28 +01:00
}
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 llvm-svn: 119548
2010-11-17 21:13:28 +01:00
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
ARM binary encodings for MVN variants. llvm-svn: 117076
2010-10-22 00:19:32 +02:00
IIC_iMVNi, "mvn", "\t$Rd, $imm",
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
[(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
ARM binary encodings for MVN variants. llvm-svn: 117076
2010-10-22 00:19:32 +02:00
bits<4> Rd;
bits<12> imm;
let Inst{25} = 1;
let Inst{19-16} = 0b0000;
let Inst{15-12} = Rd;
let Inst{11-0} = imm;
Fix arm jit encoding bug introduced by 75048. Some instructions', e.g. MOVi, bit 25 should be set. llvm-svn: 81310
2009-09-09 03:47:07 +02:00
}
fix the names of the 64bit fp register initial support for returning 64bit floating point numbers llvm-svn: 30692
2006-10-02 21:30:56 +02:00
[ARM] Prefer BIC over BFC in ARM mode. BIC is generally faster, and it can put the output in a different register from the input. We already do this in Thumb2 mode; not sure why the equivalent fix never got applied to ARM mode. Differential Revision: https://reviews.llvm.org/D31797 llvm-svn: 299803
2017-04-08 00:01:23 +02:00
let AddedComplexity = 1 in
[ARM] Cleanup so_imm* tblgen defintions No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
2015-01-06 16:55:09 +01:00
def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
(BICri GPR:$src, mod_imm_not:$imm)>;
implement a ArgumentLayout class to factor code common to LowerFORMAL_ARGUMENTS and LowerCALL implement FMDRR add support for f64 function arguments llvm-svn: 30754
2006-10-05 18:48:49 +02:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
//===----------------------------------------------------------------------===//
// Multiply Instructions.
//
ARM binary encoding for some of the multiply instructions. llvm-svn: 117080
2010-10-22 00:52:30 +02:00
class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
bits<4> Rd;
bits<4> Rm;
bits<4> Rn;
let Inst{19-16} = Rd;
let Inst{11-8} = Rm;
let Inst{3-0} = Rn;
}
class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
bits<4> RdLo;
bits<4> RdHi;
bits<4> Rm;
bits<4> Rn;
More ARM multiply instruction encoding information. llvm-svn: 117108
2010-10-22 19:16:17 +02:00
let Inst{19-16} = RdHi;
let Inst{15-12} = RdLo;
ARM binary encoding for some of the multiply instructions. llvm-svn: 117080
2010-10-22 00:52:30 +02:00
let Inst{11-8} = Rm;
let Inst{3-0} = Rn;
}
Patch to implement UMLAL/SMLAL instructions for the ARM architecture This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 163136
2012-09-04 16:37:49 +02:00
class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
bits<4> RdLo;
bits<4> RdHi;
bits<4> Rm;
bits<4> Rn;
let Inst{19-16} = RdHi;
let Inst{15-12} = RdLo;
let Inst{11-8} = Rm;
let Inst{3-0} = Rn;
}
fix the names of the 64bit fp register initial support for returning 64bit floating point numbers llvm-svn: 30692
2006-10-02 21:30:56 +02:00
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
2011-07-08 19:40:42 +02:00
// FIXME: The v5 pseudos are only necessary for the additional Constraint
// property. Remove them when it's possible to add those properties
Fix typos found by http://github.com/lyda/misspell-check llvm-svn: 157885
2012-06-02 12:20:22 +02:00
// on an individual MachineInstr, not just an instruction description.
ARM let TableGen handle a few two-operand aliases. No need for these explicit aliases anymore. Nuke 'em. llvm-svn: 155173
2012-04-20 01:59:26 +02:00
let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
Tidy up. 80 columns, whitespace, et. al. llvm-svn: 155399
2012-04-24 00:04:10 +02:00
def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
(ins GPRnopc:$Rn, GPRnopc:$Rm),
IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
[(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV6]>,
Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
A8.6.105 MUL Inst{15-12} should be specified as 0b0000. rdar://problem/9231168 ARM disassembler discrepancy: erroneously accepting MUL llvm-svn: 128862
2011-04-05 01:57:05 +02:00
let Inst{15-12} = 0b0000;
Added soft fail cases for the disassembler when decoding MUL instructions on ARM. llvm-svn: 153250
2012-03-22 14:14:39 +01:00
let Unpredictable{15-12} = 0b1111;
A8.6.105 MUL Inst{15-12} should be specified as 0b0000. rdar://problem/9231168 ARM disassembler discrepancy: erroneously accepting MUL llvm-svn: 128862
2011-04-05 01:57:05 +02:00
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Model operand restrictions of mul-like instructions on ARMv5 via earlyclobber stuff. This should fix PRs 2313 and 8157. Unfortunately, no testcase, since it'd be dependent on register assignments. llvm-svn: 122663
2011-01-01 21:38:38 +01:00
let Constraints = "@earlyclobber $Rd" in
Added soft fail cases for the disassembler when decoding MUL instructions on ARM. llvm-svn: 153250
2012-03-22 14:14:39 +01:00
def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
Tidy up. 80 columns, whitespace, et. al. llvm-svn: 155399
2012-04-24 00:04:10 +02:00
pred:$p, cc_out:$s),
4, IIC_iMUL32,
[(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
(MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, NoV6, UseMulOps]>,
Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
2011-07-08 19:40:42 +02:00
}
Add MLA alias for ARMv4 support. Fix MLA defs to use register class GPRnopc. Add encoding tests for multiply instructions. (Alias for MUL/SMLAL/UMLAL added by r199026.) Patch by Zhaoshi. llvm-svn: 199491
2014-01-17 14:53:08 +01:00
def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
Tidy up. 80 columns, whitespace, et. al. llvm-svn: 155399
2012-04-24 00:04:10 +02:00
IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
Add MLA alias for ARMv4 support. Fix MLA defs to use register class GPRnopc. Add encoding tests for multiply instructions. (Alias for MUL/SMLAL/UMLAL added by r199026.) Patch by Zhaoshi. llvm-svn: 199491
2014-01-17 14:53:08 +01:00
[(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV6, UseMulOps]>,
Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {
ARM binary encoding for some of the multiply instructions. llvm-svn: 117080
2010-10-22 00:52:30 +02:00
bits<4> Ra;
let Inst{15-12} = Ra;
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
2011-07-08 19:40:42 +02:00
let Constraints = "@earlyclobber $Rd" in
Add MLA alias for ARMv4 support. Fix MLA defs to use register class GPRnopc. Add encoding tests for multiply instructions. (Alias for MUL/SMLAL/UMLAL added by r199026.) Patch by Zhaoshi. llvm-svn: 199491
2014-01-17 14:53:08 +01:00
def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
pred:$p, cc_out:$s), 4, IIC_iMAC32,
[(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
(MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, NoV6]>,
Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
2011-07-08 19:40:42 +02:00
Fix encoding for ARM MLS instruction. llvm-svn: 119855
2010-11-19 23:22:37 +01:00
def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
[(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV6T2, UseMulOps]>,
Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {
ARM binary encoding for some of the multiply instructions. llvm-svn: 117080
2010-10-22 00:52:30 +02:00
bits<4> Rd;
bits<4> Rm;
bits<4> Rn;
Fix encoding for ARM MLS instruction. llvm-svn: 119855
2010-11-19 23:22:37 +01:00
bits<4> Ra;
ARM binary encoding for some of the multiply instructions. llvm-svn: 117080
2010-10-22 00:52:30 +02:00
let Inst{19-16} = Rd;
Fix encoding for ARM MLS instruction. llvm-svn: 119855
2010-11-19 23:22:37 +01:00
let Inst{15-12} = Ra;
ARM binary encoding for some of the multiply instructions. llvm-svn: 117080
2010-10-22 00:52:30 +02:00
let Inst{11-8} = Rm;
let Inst{3-0} = Rn;
}
Added ARM::mls for armv6t2. llvm-svn: 74866
2009-07-07 00:05:45 +02:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// Extra precision multiplies with low / high results
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 01:46:26 +01:00
let hasSideEffects = 0 in {
Mark a bunch of instructions commutable. llvm-svn: 74237
2009-06-26 02:19:44 +02:00
let isCommutable = 1 in {
ARM binary encoding for some of the multiply instructions. llvm-svn: 117080
2010-10-22 00:52:30 +02:00
def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
2011-07-08 19:40:42 +02:00
(ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
[ARM] Replace some C++ selection code with TableGen patterns. NFC. Differential Revision: https://reviews.llvm.org/D30794 llvm-svn: 297768
2017-03-14 19:43:37 +01:00
"smull", "\t$RdLo, $RdHi, $Rn, $Rm",
[(set GPR:$RdLo, GPR:$RdHi,
(smullohi GPR:$Rn, GPR:$Rm))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV6]>,
Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
ARM binary encoding for some of the multiply instructions. llvm-svn: 117080
2010-10-22 00:52:30 +02:00
def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
2011-07-08 19:40:42 +02:00
(ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
[ARM] Replace some C++ selection code with TableGen patterns. NFC. Differential Revision: https://reviews.llvm.org/D30794 llvm-svn: 297768
2017-03-14 19:43:37 +01:00
"umull", "\t$RdLo, $RdHi, $Rn, $Rm",
[(set GPR:$RdLo, GPR:$RdHi,
(umullohi GPR:$Rn, GPR:$Rm))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV6]>,
Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Model operand restrictions of mul-like instructions on ARMv5 via earlyclobber stuff. This should fix PRs 2313 and 8157. Unfortunately, no testcase, since it'd be dependent on register assignments. llvm-svn: 122663
2011-01-01 21:38:38 +01:00
let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
2011-07-08 19:40:42 +02:00
def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
Clean whitespace. llvm-svn: 127900
2011-03-18 20:47:14 +01:00
(ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
[ARM] Replace some C++ selection code with TableGen patterns. NFC. Differential Revision: https://reviews.llvm.org/D30794 llvm-svn: 297768
2017-03-14 19:43:37 +01:00
4, IIC_iMUL64,
[(set GPR:$RdLo, GPR:$RdHi,
(smullohi GPR:$Rn, GPR:$Rm))],
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
2011-07-08 19:40:42 +02:00
(SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, NoV6]>,
Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>;
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
2011-07-08 19:40:42 +02:00
def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
Clean whitespace. llvm-svn: 127900
2011-03-18 20:47:14 +01:00
(ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
[ARM] Replace some C++ selection code with TableGen patterns. NFC. Differential Revision: https://reviews.llvm.org/D30794 llvm-svn: 297768
2017-03-14 19:43:37 +01:00
4, IIC_iMUL64,
[(set GPR:$RdLo, GPR:$RdHi,
(umullohi GPR:$Rn, GPR:$Rm))],
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
2011-07-08 19:40:42 +02:00
(UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, NoV6]>,
Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>;
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
2011-07-08 19:40:42 +02:00
}
Model operand restrictions of mul-like instructions on ARMv5 via earlyclobber stuff. This should fix PRs 2313 and 8157. Unfortunately, no testcase, since it'd be dependent on register assignments. llvm-svn: 122663
2011-01-01 21:38:38 +01:00
}
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
2011-07-08 19:40:42 +02:00
// Multiply + accumulate
Patch to implement UMLAL/SMLAL instructions for the ARM architecture This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 163136
2012-09-04 16:37:49 +02:00
def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
(ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
Model operand restrictions of mul-like instructions on ARMv5 via earlyclobber stuff. This should fix PRs 2313 and 8157. Unfortunately, no testcase, since it'd be dependent on register assignments. llvm-svn: 122663
2011-01-01 21:38:38 +01:00
"smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
Patch to implement UMLAL/SMLAL instructions for the ARM architecture This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 163136
2012-09-04 16:37:49 +02:00
def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
(ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
Model operand restrictions of mul-like instructions on ARMv5 via earlyclobber stuff. This should fix PRs 2313 and 8157. Unfortunately, no testcase, since it'd be dependent on register assignments. llvm-svn: 122663
2011-01-01 21:38:38 +01:00
"umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
ARM binary encoding for some of the multiply instructions. llvm-svn: 117080
2010-10-22 00:52:30 +02:00
def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
[ARM] Enable isel of UMAAL TargetLowering and DAGToDAG are used to combine ADDC, ADDE and UMLAL dags into UMAAL. Selection is split into the two phases because it is easier to match the two patterns at those different times. Differential Revision: http://http://reviews.llvm.org/D21461 llvm-svn: 273165
2016-06-20 18:47:09 +02:00
(ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
IIC_iMAC64,
ARM binary encoding for some of the multiply instructions. llvm-svn: 117080
2010-10-22 00:52:30 +02:00
"umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> {
ARM binary encoding for some of the multiply instructions. llvm-svn: 117080
2010-10-22 00:52:30 +02:00
bits<4> RdLo;
bits<4> RdHi;
bits<4> Rm;
bits<4> Rn;
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy. llvm-svn: 137641
2011-08-15 22:08:25 +02:00
let Inst{19-16} = RdHi;
let Inst{15-12} = RdLo;
ARM binary encoding for some of the multiply instructions. llvm-svn: 117080
2010-10-22 00:52:30 +02:00
let Inst{11-8} = Rm;
let Inst{3-0} = Rn;
}
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
2011-07-08 19:40:42 +02:00
ARM: add constraint that RdLo != Rn != RdHi for v5 MLA insts. llvm-svn: 199212
2014-01-14 14:05:47 +01:00
let Constraints =
"@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
2011-07-08 19:40:42 +02:00
def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
Patch to implement UMLAL/SMLAL instructions for the ARM architecture This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 163136
2012-09-04 16:37:49 +02:00
(ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
4, IIC_iMAC64, [],
Patch to implement UMLAL/SMLAL instructions for the ARM architecture This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 163136
2012-09-04 16:37:49 +02:00
(SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
pred:$p, cc_out:$s)>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, NoV6]>,
Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
2011-07-08 19:40:42 +02:00
def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
Patch to implement UMLAL/SMLAL instructions for the ARM architecture This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 163136
2012-09-04 16:37:49 +02:00
(ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
4, IIC_iMAC64, [],
Patch to implement UMLAL/SMLAL instructions for the ARM architecture This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 163136
2012-09-04 16:37:49 +02:00
(UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
pred:$p, cc_out:$s)>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, NoV6]>,
Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
Patch to implement UMLAL/SMLAL instructions for the ARM architecture This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 163136
2012-09-04 16:37:49 +02:00
}
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 01:46:26 +01:00
} // hasSideEffects
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// Most significant word multiply
More ARM multiply instruction encoding information. llvm-svn: 117108
2010-10-22 19:16:17 +02:00
def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
[(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV6]>,
Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls. llvm-svn: 58789
2008-11-06 02:21:28 +01:00
let Inst{15-12} = 0b1111;
}
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. llvm-svn: 38501
2007-07-10 20:08:01 +02:00
More ARM multiply instruction encoding information. llvm-svn: 117108
2010-10-22 19:16:17 +02:00
def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
[ARM] Add codegen for SMMULR, SMMLAR and SMMLSR This patch teaches the Arm back-end to generate the SMMULR, SMMLAR and SMMLSR instructions from equivalent IR patterns. Differential Revision: https://reviews.llvm.org/D41775 llvm-svn: 322361
2018-01-12 10:24:41 +01:00
IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
[(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, (i32 0)))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV6]>,
Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
Added SEL, SXTB16, SXTAB16, UXTAB16, SMMULR, SMMLAR, SMMLSR, SMUAD, and SMUSD, for disassembly only. llvm-svn: 96806
2010-02-22 22:50:40 +01:00
let Inst{15-12} = 0b1111;
}
More ARM multiply instruction encoding information. llvm-svn: 117108
2010-10-22 19:16:17 +02:00
def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
[(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV6, UseMulOps]>,
Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
More ARM multiply instruction encoding information. llvm-svn: 117108
2010-10-22 19:16:17 +02:00
def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
[ARM] Add codegen for SMMULR, SMMLAR and SMMLSR This patch teaches the Arm back-end to generate the SMMULR, SMMLAR and SMMLSR instructions from equivalent IR patterns. Differential Revision: https://reviews.llvm.org/D41775 llvm-svn: 322361
2018-01-12 10:24:41 +01:00
IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
[(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV6]>,
Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
More ARM multiply instruction encoding information. llvm-svn: 117108
2010-10-22 19:16:17 +02:00
def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
Remove incorrect pattern for ARM SMML instruction. Patch by Meador Inge. llvm-svn: 156989
2012-05-17 15:12:13 +02:00
IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV6, UseMulOps]>,
Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
More ARM multiply instruction encoding information. llvm-svn: 117108
2010-10-22 19:16:17 +02:00
def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
[ARM] Add codegen for SMMULR, SMMLAR and SMMLSR This patch teaches the Arm back-end to generate the SMMULR, SMMLAR and SMMLSR instructions from equivalent IR patterns. Differential Revision: https://reviews.llvm.org/D41775 llvm-svn: 322361
2018-01-12 10:24:41 +01:00
IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
[(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV6]>,
Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
Added SEL, SXTB16, SXTAB16, UXTAB16, SMMULR, SMMLAR, SMMLSR, SMUAD, and SMUSD, for disassembly only. llvm-svn: 96806
2010-02-22 22:50:40 +01:00
[ARM] Cleanup of smul and smla instruction descriptions Removed the SDNode argument passed to the AI_smul and AI_smla multiclass definitions as they are always mul. Differential Revision: http://reviews.llvm.org/D18791 llvm-svn: 265409
2016-04-05 18:01:25 +02:00
multiclass AI_smul<string opc> {
More ARM multiply instuction binary encodings. llvm-svn: 117121
2010-10-22 20:35:16 +02:00
def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
[ARM] Add missing patterns for DSP muls Using a PatLeaf for sext_16_node allowed matching smulbb and smlabb instructions once the operands had been sign extended. But we also need to use sext_inreg operands along with sext_16_node to catch a few more cases that enable use to remove the unnecessary sxth. Differential Revision: https://reviews.llvm.org/D55992 llvm-svn: 350613
2019-01-08 11:12:36 +01:00
[(set GPR:$Rd, (bb_mul GPR:$Rn, GPR:$Rm))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV5TE]>,
Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
More ARM multiply instuction binary encodings. llvm-svn: 117121
2010-10-22 20:35:16 +02:00
def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
[ARM] Add missing patterns for DSP muls Using a PatLeaf for sext_16_node allowed matching smulbb and smlabb instructions once the operands had been sign extended. But we also need to use sext_inreg operands along with sext_16_node to catch a few more cases that enable use to remove the unnecessary sxth. Differential Revision: https://reviews.llvm.org/D55992 llvm-svn: 350613
2019-01-08 11:12:36 +01:00
[(set GPR:$Rd, (bt_mul GPR:$Rn, GPR:$Rm))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV5TE]>,
Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
More ARM multiply instuction binary encodings. llvm-svn: 117121
2010-10-22 20:35:16 +02:00
def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
[ARM] Add missing patterns for DSP muls Using a PatLeaf for sext_16_node allowed matching smulbb and smlabb instructions once the operands had been sign extended. But we also need to use sext_inreg operands along with sext_16_node to catch a few more cases that enable use to remove the unnecessary sxth. Differential Revision: https://reviews.llvm.org/D55992 llvm-svn: 350613
2019-01-08 11:12:36 +01:00
[(set GPR:$Rd, (tb_mul GPR:$Rn, GPR:$Rm))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV5TE]>,
Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
More ARM multiply instuction binary encodings. llvm-svn: 117121
2010-10-22 20:35:16 +02:00
def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
[ARM] Add missing patterns for DSP muls Using a PatLeaf for sext_16_node allowed matching smulbb and smlabb instructions once the operands had been sign extended. But we also need to use sext_inreg operands along with sext_16_node to catch a few more cases that enable use to remove the unnecessary sxth. Differential Revision: https://reviews.llvm.org/D55992 llvm-svn: 350613
2019-01-08 11:12:36 +01:00
[(set GPR:$Rd, (tt_mul GPR:$Rn, GPR:$Rm))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV5TE]>,
Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
More ARM multiply instuction binary encodings. llvm-svn: 117121
2010-10-22 20:35:16 +02:00
def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
[ARM] Move SMULW[B|T] isel to DAG Combine Create nodes for smulwb and smulwt and move their selection from DAGToDAG to DAG combine. smlawb and smlawt can then be selected using tablegen. Added some helper functions to detect shift patterns as well as a wrapper around SimplifyDemandBits. Added a couple of extra tests. Differential Revision: https://reviews.llvm.org/D30708 llvm-svn: 297716
2017-03-14 10:13:22 +01:00
[(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV5TE]>,
Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
More ARM multiply instuction binary encodings. llvm-svn: 117121
2010-10-22 20:35:16 +02:00
def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
[ARM] Move SMULW[B|T] isel to DAG Combine Create nodes for smulwb and smulwt and move their selection from DAGToDAG to DAG combine. smlawb and smlawt can then be selected using tablegen. Added some helper functions to detect shift patterns as well as a wrapper around SimplifyDemandBits. Added a couple of extra tests. Differential Revision: https://reviews.llvm.org/D30708 llvm-svn: 297716
2017-03-14 10:13:22 +01:00
[(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV5TE]>,
Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
}
add double <-> int conversion llvm-svn: 30858
2006-10-10 20:55:14 +02:00
ARM instruction table was modified by adding information to generate multiply instruction of V5TE. llvm-svn: 41626
2007-08-31 01:25:47 +02:00
[ARM] Cleanup of smul and smla instruction descriptions Removed the SDNode argument passed to the AI_smul and AI_smla multiclass definitions as they are always mul. Differential Revision: http://reviews.llvm.org/D18791 llvm-svn: 265409
2016-04-05 18:01:25 +02:00
multiclass AI_smla<string opc> {
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeSMLAInstruction" in {
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
More ARM multiply instuction binary encodings. llvm-svn: 117121
2010-10-22 20:35:16 +02:00
IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
[(set GPRnopc:$Rd, (add GPR:$Ra,
[ARM] Add missing patterns for DSP muls Using a PatLeaf for sext_16_node allowed matching smulbb and smlabb instructions once the operands had been sign extended. But we also need to use sext_inreg operands along with sext_16_node to catch a few more cases that enable use to remove the unnecessary sxth. Differential Revision: https://reviews.llvm.org/D55992 llvm-svn: 350613
2019-01-08 11:12:36 +01:00
(bb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV5TE, UseMulOps]>,
Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
More ARM multiply instuction binary encodings. llvm-svn: 117121
2010-10-22 20:35:16 +02:00
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
More ARM multiply instuction binary encodings. llvm-svn: 117121
2010-10-22 20:35:16 +02:00
IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
[ARM] Add missing patterns for DSP muls Using a PatLeaf for sext_16_node allowed matching smulbb and smlabb instructions once the operands had been sign extended. But we also need to use sext_inreg operands along with sext_16_node to catch a few more cases that enable use to remove the unnecessary sxth. Differential Revision: https://reviews.llvm.org/D55992 llvm-svn: 350613
2019-01-08 11:12:36 +01:00
[(set GPRnopc:$Rd, (add GPR:$Ra,
(bt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV5TE, UseMulOps]>,
Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
More ARM multiply instuction binary encodings. llvm-svn: 117121
2010-10-22 20:35:16 +02:00
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
More ARM multiply instuction binary encodings. llvm-svn: 117121
2010-10-22 20:35:16 +02:00
IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
[ARM] Add missing patterns for DSP muls Using a PatLeaf for sext_16_node allowed matching smulbb and smlabb instructions once the operands had been sign extended. But we also need to use sext_inreg operands along with sext_16_node to catch a few more cases that enable use to remove the unnecessary sxth. Differential Revision: https://reviews.llvm.org/D55992 llvm-svn: 350613
2019-01-08 11:12:36 +01:00
[(set GPRnopc:$Rd, (add GPR:$Ra,
(tb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV5TE, UseMulOps]>,
Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
More ARM multiply instuction binary encodings. llvm-svn: 117121
2010-10-22 20:35:16 +02:00
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
More ARM multiply instuction binary encodings. llvm-svn: 117121
2010-10-22 20:35:16 +02:00
IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
[ARM] Add missing patterns for DSP muls Using a PatLeaf for sext_16_node allowed matching smulbb and smlabb instructions once the operands had been sign extended. But we also need to use sext_inreg operands along with sext_16_node to catch a few more cases that enable use to remove the unnecessary sxth. Differential Revision: https://reviews.llvm.org/D55992 llvm-svn: 350613
2019-01-08 11:12:36 +01:00
[(set GPRnopc:$Rd, (add GPR:$Ra,
(tt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV5TE, UseMulOps]>,
Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
More ARM multiply instuction binary encodings. llvm-svn: 117121
2010-10-22 20:35:16 +02:00
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
More ARM multiply instuction binary encodings. llvm-svn: 117121
2010-10-22 20:35:16 +02:00
IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
[ARM] Move SMULW[B|T] isel to DAG Combine Create nodes for smulwb and smulwt and move their selection from DAGToDAG to DAG combine. smlawb and smlawt can then be selected using tablegen. Added some helper functions to detect shift patterns as well as a wrapper around SimplifyDemandBits. Added a couple of extra tests. Differential Revision: https://reviews.llvm.org/D30708 llvm-svn: 297716
2017-03-14 10:13:22 +01:00
[(set GPRnopc:$Rd,
(add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasV5TE, UseMulOps]>,
Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
More ARM multiply instuction binary encodings. llvm-svn: 117121
2010-10-22 20:35:16 +02:00
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
More ARM multiply instuction binary encodings. llvm-svn: 117121
2010-10-22 20:35:16 +02:00
IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
[ARM] Move SMULW[B|T] isel to DAG Combine Create nodes for smulwb and smulwt and move their selection from DAGToDAG to DAG combine. smlawb and smlawt can then be selected using tablegen. Added some helper functions to detect shift patterns as well as a wrapper around SimplifyDemandBits. Added a couple of extra tests. Differential Revision: https://reviews.llvm.org/D30708 llvm-svn: 297716
2017-03-14 10:13:22 +01:00
[(set GPRnopc:$Rd,
(add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))]>,
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
Requires<[IsARM, HasV5TE, UseMulOps]>,
Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
}
implement fadds, faddd, fmuls and fmuld llvm-svn: 30801
2006-10-07 15:46:42 +02:00
[ARM] Cleanup of smul and smla instruction descriptions Removed the SDNode argument passed to the AI_smul and AI_smla multiclass definitions as they are always mul. Differential Revision: http://reviews.llvm.org/D18791 llvm-svn: 265409
2016-04-05 18:01:25 +02:00
defm SMUL : AI_smul<"smul">;
defm SMLA : AI_smla<"smla">;
add double <-> int conversion llvm-svn: 30858
2006-10-10 20:55:14 +02:00
Remove no-longer-true comments. These are for the assembler, also. llvm-svn: 137375
2011-08-12 00:30:30 +02:00
// Halfword multiply accumulate long: SMLAL<x><y>.
[ARM] Enable SMLAL[B|T] isel Enable the selection of the 64-bit signed multiply accumulate instructions which operate on 16-bit operands. These are enabled for ARMv5TE onwards for ARM and for V6T2 and other DSP enabled Thumb architectures. Differential Revision: https://reviews.llvm.org/D30044 llvm-svn: 297809
2017-03-15 09:27:11 +01:00
class SMLAL<bits<2> opc1, string asm>
: AMulxyI64<0b0001010, opc1,
(outs GPRnopc:$RdLo, GPRnopc:$RdHi),
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
IIC_iMAC64, asm, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
Requires<[IsARM, HasV5TE]>,
Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
def SMLALBB : SMLAL<0b00, "smlalbb">;
def SMLALBT : SMLAL<0b10, "smlalbt">;
def SMLALTB : SMLAL<0b01, "smlaltb">;
def SMLALTT : SMLAL<0b11, "smlaltt">;
def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
(SMLALBB $Rn, $Rm, $RLo, $RHi)>;
def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
(SMLALBT $Rn, $Rm, $RLo, $RHi)>;
def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
(SMLALTB $Rn, $Rm, $RLo, $RHi)>;
def : ARMV5TEPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
(SMLALTT $Rn, $Rm, $RLo, $RHi)>;
Add halfword multiply accumulate long SMLALBB/BT/TB/TT for disassembly only. llvm-svn: 96019
2010-02-12 22:59:23 +01:00
Remove no-longer-true comments. These are for the assembler, also. llvm-svn: 137375
2011-08-12 00:30:30 +02:00
// Helper class for AI_smld.
Add the encoding information for the rest of the ARM mode multiply instructions. llvm-svn: 117133
2010-10-22 21:15:30 +02:00
class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
InstrItinClass itin, string opc, string asm>
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
: AI<oops, iops, MulFrm, itin, opc, asm, []>,
Requires<[IsARM, HasV6]> {
Add the encoding information for the rest of the ARM mode multiply instructions. llvm-svn: 117133
2010-10-22 21:15:30 +02:00
bits<4> Rn;
bits<4> Rm;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
let Inst{27-23} = 0b01110;
ARM encoding and assembly parsing of SMLAD{X} instructions. Fix encoding of destination register. Add tests. llvm-svn: 135796
2011-07-22 22:11:20 +02:00
let Inst{22} = long;
let Inst{21-20} = 0b00;
Add the encoding information for the rest of the ARM mode multiply instructions. llvm-svn: 117133
2010-10-22 21:15:30 +02:00
let Inst{11-8} = Rm;
ARM encoding and assembly parsing of SMLAD{X} instructions. Fix encoding of destination register. Add tests. llvm-svn: 135796
2011-07-22 22:11:20 +02:00
let Inst{7} = 0;
let Inst{6} = sub;
let Inst{5} = swap;
let Inst{4} = 1;
Add the encoding information for the rest of the ARM mode multiply instructions. llvm-svn: 117133
2010-10-22 21:15:30 +02:00
let Inst{3-0} = Rn;
}
class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
InstrItinClass itin, string opc, string asm>
: AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
bits<4> Rd;
let Inst{15-12} = 0b1111;
let Inst{19-16} = Rd;
}
class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
InstrItinClass itin, string opc, string asm>
: AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
bits<4> Ra;
ARM encoding and assembly parsing of SMLAD{X} instructions. Fix encoding of destination register. Add tests. llvm-svn: 135796
2011-07-22 22:11:20 +02:00
bits<4> Rd;
let Inst{19-16} = Rd;
Add the encoding information for the rest of the ARM mode multiply instructions. llvm-svn: 117133
2010-10-22 21:15:30 +02:00
let Inst{15-12} = Ra;
}
class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
InstrItinClass itin, string opc, string asm>
: AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
bits<4> RdLo;
bits<4> RdHi;
let Inst{19-16} = RdHi;
let Inst{15-12} = RdLo;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
}
multiclass AI_smld<bit sub, string opc> {
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">,
Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">,
Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
NoItinerary,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
!strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">,
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
NoItinerary,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
!strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">,
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>;
Added a bunch of instructions for disassembly only: o signed/unsigned add/subtract o signed/unsigned halving add/subtract o unsigned sum of absolute difference [and accumulate] o signed/unsigned saturate o signed multiply accumulate/subtract [long] dual llvm-svn: 96795
2010-02-22 19:50:54 +01:00
}
defm SMLA : AI_smld<0, "smla">;
defm SMLS : AI_smld<1, "smls">;
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
def : ARMV6Pat<(int_arm_smlad GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
(SMLAD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>;
def : ARMV6Pat<(int_arm_smladx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
(SMLADX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>;
def : ARMV6Pat<(int_arm_smlsd GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
(SMLSD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>;
def : ARMV6Pat<(int_arm_smlsdx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
(SMLSDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>;
def : ARMV6Pat<(ARMSmlald GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
(SMLALD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
def : ARMV6Pat<(ARMSmlaldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
(SMLALDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
def : ARMV6Pat<(ARMSmlsld GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
(SMLSLD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
def : ARMV6Pat<(ARMSmlsldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
(SMLSLDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
Added SEL, SXTB16, SXTAB16, UXTAB16, SMMULR, SMMLAR, SMMLSR, SMUAD, and SMUSD, for disassembly only. llvm-svn: 96806
2010-02-22 22:50:40 +01:00
multiclass AI_sdml<bit sub, string opc> {
Tidy up. 80 columns. llvm-svn: 137277
2011-08-11 01:23:47 +02:00
def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">,
Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
Tidy up. 80 columns. llvm-svn: 137277
2011-08-11 01:23:47 +02:00
def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">,
Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
Added SEL, SXTB16, SXTAB16, UXTAB16, SMMULR, SMMLAR, SMMLSR, SMUAD, and SMUSD, for disassembly only. llvm-svn: 96806
2010-02-22 22:50:40 +01:00
}
defm SMUA : AI_sdml<0, "smua">;
defm SMUS : AI_sdml<1, "smus">;
implement FUITOS and FUITOD llvm-svn: 30803
2006-10-07 16:24:52 +02:00
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
def : ARMV6Pat<(int_arm_smuad GPRnopc:$Rn, GPRnopc:$Rm),
(SMUAD GPRnopc:$Rn, GPRnopc:$Rm)>;
def : ARMV6Pat<(int_arm_smuadx GPRnopc:$Rn, GPRnopc:$Rm),
(SMUADX GPRnopc:$Rn, GPRnopc:$Rm)>;
def : ARMV6Pat<(int_arm_smusd GPRnopc:$Rn, GPRnopc:$Rm),
(SMUSD GPRnopc:$Rn, GPRnopc:$Rm)>;
def : ARMV6Pat<(int_arm_smusdx GPRnopc:$Rn, GPRnopc:$Rm),
(SMUSDX GPRnopc:$Rn, GPRnopc:$Rm)>;
Add LLVM support for Swift. llvm-svn: 164899
2012-09-29 23:43:49 +02:00
//===----------------------------------------------------------------------===//
// Division Instructions (ARMv7-A with virtualization extension)
//
def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
"sdiv", "\t$Rd, $Rn, $Rm",
[(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasDivideInARM]>,
Sched<[WriteDIV]>;
Add LLVM support for Swift. llvm-svn: 164899
2012-09-29 23:43:49 +02:00
def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
"udiv", "\t$Rd, $Rn, $Rm",
[(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
[ARM] Classification Improvements to ARM Sched-Model. NFCI. This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
2017-02-02 22:08:12 +01:00
Requires<[IsARM, HasDivideInARM]>,
Sched<[WriteDIV]>;
Add LLVM support for Swift. llvm-svn: 164899
2012-09-29 23:43:49 +02:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
//===----------------------------------------------------------------------===//
// Misc. Arithmetic Instructions.
//
uint <-> double conversion llvm-svn: 30862
2006-10-10 22:38:57 +02:00
Fix bit initializer which was one bit too long, but worked so long as we silently dropped the leading 0 llvm-svn: 214372
2014-07-31 03:43:51 +02:00
def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*. llvm-svn: 117165
2010-10-23 00:12:16 +02:00
IIC_iUNAr, "clz", "\t$Rd, $Rm",
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 07:01:06 +02:00
[(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
Sched<[WriteALU]>;
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*. llvm-svn: 117165
2010-10-23 00:12:16 +02:00
def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
IIC_iUNAr, "rbit", "\t$Rd, $Rm",
[ARM] Replace ARMISD::RBIT with ISD::BITREVERSE ISD::BITREVERSE matches "rbit" completely, so remove ARMISD::RBIT and mark ISD::BITREVERSE as legal, adding a test for lowering. llvm-svn: 253047
2015-11-13 17:05:22 +01:00
[(set GPR:$Rd, (bitreverse GPR:$Rm))]>,
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 07:01:06 +02:00
Requires<[IsARM, HasV6T2]>,
Sched<[WriteALU]>;
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*. llvm-svn: 117165
2010-10-23 00:12:16 +02:00
def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
IIC_iUNAr, "rev", "\t$Rd, $Rm",
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 07:01:06 +02:00
[(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
Sched<[WriteALU]>;
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*. llvm-svn: 117165
2010-10-23 00:12:16 +02:00
Teach dag combine to match halfword byteswap patterns. 1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8) => (bswap x) >> 16 2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8)) => (rotl (bswap x) 16) This allows us to eliminate most of the def : Pat patterns for ARM rev16 revsh instructions. It catches many more cases for ARM and x86. rdar://9609108 llvm-svn: 133503
2011-06-21 08:01:08 +02:00
let AddedComplexity = 5 in
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*. llvm-svn: 117165
2010-10-23 00:12:16 +02:00
def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
IIC_iUNAr, "rev16", "\t$Rd, $Rm",
Teach dag combine to match halfword byteswap patterns. 1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8) => (bswap x) >> 16 2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8)) => (rotl (bswap x) 16) This allows us to eliminate most of the def : Pat patterns for ARM rev16 revsh instructions. It catches many more cases for ARM and x86. rdar://9609108 llvm-svn: 133503
2011-06-21 08:01:08 +02:00
[(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 07:01:06 +02:00
Requires<[IsARM, HasV6]>,
Sched<[WriteALU]>;
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*. llvm-svn: 117165
2010-10-23 00:12:16 +02:00
Add support bswap16 to/from memory compiling to rev16 on ARM/Thumb The current patterns for REV16 misses mostn __builtin_bswap16() due to legalization promoting the operands to from load/stores toi32s and then truncing/extending them. This patch adds new patterns that catch the resultant DAGs and codegens them to rev16 instructions. Tests included. rdar://15353652 llvm-svn: 208620
2014-05-12 21:53:52 +02:00
def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)),
(REV16 (LDRH addrmode3:$addr))>;
def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
(STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
Teach dag combine to match halfword byteswap patterns. 1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8) => (bswap x) >> 16 2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8)) => (rotl (bswap x) 16) This allows us to eliminate most of the def : Pat patterns for ARM rev16 revsh instructions. It catches many more cases for ARM and x86. rdar://9609108 llvm-svn: 133503
2011-06-21 08:01:08 +02:00
let AddedComplexity = 5 in
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*. llvm-svn: 117165
2010-10-23 00:12:16 +02:00
def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
IIC_iUNAr, "revsh", "\t$Rd, $Rm",
Teach dag combine to match halfword byteswap patterns. 1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8) => (bswap x) >> 16 2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8)) => (rotl (bswap x) 16) This allows us to eliminate most of the def : Pat patterns for ARM rev16 revsh instructions. It catches many more cases for ARM and x86. rdar://9609108 llvm-svn: 133503
2011-06-21 08:01:08 +02:00
[(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 07:01:06 +02:00
Requires<[IsARM, HasV6]>,
Sched<[WriteALU]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Another revsh pattern. rdar://9609059 llvm-svn: 133064
2011-06-15 19:17:48 +02:00
def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
(and (srl GPR:$Rm, (i32 8)), 0xFF)),
(REVSH GPR:$Rm)>;
ARM tighten up the register classes for the PKH instructions. llvm-svn: 139748
2011-09-15 00:52:14 +02:00
def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
(ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
ARM PKH shift ammount operand printing tweaks. Move the shift operator and special value (32 encoded as 0 for PKHTB) handling into the instruction printer. This cleans up a bit of the disassembler special casing for these instructions, more easily handles not printing the operand at all for "lsl #0" and prepares for correct asm parsing of these operands. llvm-svn: 135626
2011-07-20 23:40:26 +02:00
IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
ARM tighten up the register classes for the PKH instructions. llvm-svn: 139748
2011-09-15 00:52:14 +02:00
[(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
(and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
0xFFFF0000)))]>,
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 07:01:06 +02:00
Requires<[IsARM, HasV6]>,
Sched<[WriteALUsi, ReadALU]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// Alternate cases for PKHBT where identities eliminate some nodes.
ARM tighten up the register classes for the PKH instructions. llvm-svn: 139748
2011-09-15 00:52:14 +02:00
def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
(PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
(PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid printing "lsl #0". This fixes the remaining parts of pr7792. Make corresponding changes for encoding/decoding these instructions. llvm-svn: 111251
2010-08-17 19:23:19 +02:00
Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee that the high halfword is zero. The shift need not be exactly 16 bits. llvm-svn: 111196
2010-08-17 00:26:55 +02:00
// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
// will match the pattern below.
ARM tighten up the register classes for the PKH instructions. llvm-svn: 139748
2011-09-15 00:52:14 +02:00
def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
(ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
ARM PKH shift ammount operand printing tweaks. Move the shift operator and special value (32 encoded as 0 for PKHTB) handling into the instruction printer. This cleans up a bit of the disassembler special casing for these instructions, more easily handles not printing the operand at all for "lsl #0" and prepares for correct asm parsing of these operands. llvm-svn: 135626
2011-07-20 23:40:26 +02:00
IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
ARM tighten up the register classes for the PKH instructions. llvm-svn: 139748
2011-09-15 00:52:14 +02:00
[(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
(and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
0xFFFF)))]>,
ARM scheduler model: Add scheduler info to more instructions and resource descriptions for compares llvm-svn: 178844
2013-04-05 07:01:06 +02:00
Requires<[IsARM, HasV6]>,
Sched<[WriteALUsi, ReadALU]>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// Alternate cases for PKHTB where identities eliminate some nodes. Note that
// a shift amount of 0 is *not legal* here, it is PKHBT instead.
ARM: Fix incorrect pack pattern A "pkhtb x, x, y asr #num" uses the lower 16 bits of "y asr #num" and packs them in the bottom half of "x". An arithmetic and logic shift are only equivalent in this context if the shift amount is 16. We would be shifting in ones into the bottom 16bits instead of zeros if "y" is negative. radar://14338767 llvm-svn: 185712
2013-07-05 20:28:39 +02:00
// We also can not replace a srl (17..31) by an arithmetic shift we would use in
// pkhtb src1, src2, asr (17..31).
ARM tighten up the register classes for the PKH instructions. llvm-svn: 139748
2011-09-15 00:52:14 +02:00
def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
ARM: Fix incorrect pack pattern A "pkhtb x, x, y asr #num" uses the lower 16 bits of "y asr #num" and packs them in the bottom half of "x". An arithmetic and logic shift are only equivalent in this context if the shift amount is 16. We would be shifting in ones into the bottom 16bits instead of zeros if "y" is negative. radar://14338767 llvm-svn: 185712
2013-07-05 20:28:39 +02:00
(srl GPRnopc:$src2, imm16:$sh)),
(PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
ARM: Add a pack pattern for matching arithmetic shift right llvm-svn: 185714
2013-07-05 20:57:49 +02:00
def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
(sra GPRnopc:$src2, imm16_31:$sh)),
(PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
ARM tighten up the register classes for the PKH instructions. llvm-svn: 139748
2011-09-15 00:52:14 +02:00
def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
(and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
(PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
implement FUITOS and FUITOD llvm-svn: 30803
2006-10-07 16:24:52 +02:00
[ARMv8] Add CRC instructions. Patch by Bradley Smith! llvm-svn: 190928
2013-09-18 11:45:55 +02:00
//===----------------------------------------------------------------------===//
// CRC Instructions
//
// Polynomials:
// + CRC32{B,H,W} 0x04C11DB7
// + CRC32C{B,H,W} 0x1EDC6F41
//
class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
: AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
!strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
[(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
ARM: Add subtarget feature for CRC Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend. Differential Revision: http://llvm-reviews.chandlerc.com/D2036 llvm-svn: 193599
2013-10-29 10:47:35 +01:00
Requires<[IsARM, HasV8, HasCRC]> {
[ARMv8] Add CRC instructions. Patch by Bradley Smith! llvm-svn: 190928
2013-09-18 11:45:55 +02:00
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
let Inst{31-28} = 0b1110;
let Inst{27-23} = 0b00010;
let Inst{22-21} = sz;
let Inst{20} = 0;
let Inst{19-16} = Rn;
let Inst{15-12} = Rd;
let Inst{11-10} = 0b00;
let Inst{9} = C;
let Inst{8} = 0;
let Inst{7-4} = 0b0100;
let Inst{3-0} = Rm;
let Unpredictable{11-8} = 0b1101;
}
def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
[ARM] Add v8.1a "Privileged Access Never" extension Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8504 llvm-svn: 235087
2015-04-16 13:34:25 +02:00
//===----------------------------------------------------------------------===//
// ARMv8.1a Privilege Access Never extension
//
// SETPAN #imm1
def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan",
"\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> {
bits<1> imm;
let Inst{31-28} = 0b1111;
let Inst{27-20} = 0b00010001;
let Inst{19-16} = 0b0000;
let Inst{15-10} = 0b000000;
let Inst{9} = imm;
let Inst{8} = 0b0;
let Inst{7-4} = 0b0000;
let Inst{3-0} = 0b0000;
let Unpredictable{19-16} = 0b1111;
let Unpredictable{15-10} = 0b111111;
let Unpredictable{8} = 0b1;
let Unpredictable{3-0} = 0b1111;
}
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
//===----------------------------------------------------------------------===//
// Comparison Instructions...
//
Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right) llvm-svn: 57524
2008-10-14 22:36:24 +02:00
defm CMP : AI1_cmp_irs<0b1010, "cmp",
[ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC) Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
2016-03-08 17:23:54 +01:00
IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, ARMcmp>;
Reapply r112176 without removing the other CMN patterns (that was unintentional). llvm-svn: 112206
2010-08-26 20:33:51 +02:00
Refactor the ARM CMPz* patterns to just use the normal CMP instructions when possible. They were duplicates for everything exception the source pattern before. llvm-svn: 121179
2010-12-07 21:41:06 +01:00
// ARMcmpZ can re-use the above instruction definitions.
[ARM] Cleanup so_imm* tblgen defintions No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
2015-01-06 16:55:09 +01:00
def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm),
(CMPri GPR:$src, mod_imm:$imm)>;
Refactor the ARM CMPz* patterns to just use the normal CMP instructions when possible. They were duplicates for everything exception the source pattern before. llvm-svn: 121179
2010-12-07 21:41:06 +01:00
def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
(CMPrr GPR:$src, GPR:$rhs)>;
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
(CMPrsi GPR:$src, so_reg_imm:$rhs)>;
def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
(CMPrsr GPR:$src, so_reg_reg:$rhs)>;
Refactor the ARM CMPz* patterns to just use the normal CMP instructions when possible. They were duplicates for everything exception the source pattern before. llvm-svn: 121179
2010-12-07 21:41:06 +01:00
Re-enable the CMN instruction. We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> llvm-svn: 158302
2012-06-11 10:07:26 +02:00
// CMN register-integer
let isCompare = 1, Defs = [CPSR] in {
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
Re-enable the CMN instruction. We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> llvm-svn: 158302
2012-06-11 10:07:26 +02:00
"cmn", "\t$Rn, $imm",
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
[(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
Sched<[WriteCMP, ReadALU]> {
Re-enable the CMN instruction. We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> llvm-svn: 158302
2012-06-11 10:07:26 +02:00
bits<4> Rn;
bits<12> imm;
let Inst{25} = 1;
let Inst{20} = 1;
let Inst{19-16} = Rn;
let Inst{15-12} = 0b0000;
let Inst{11-0} = imm;
let Unpredictable{15-12} = 0b1111;
}
// CMN register-register/shift
def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
"cmn", "\t$Rn, $Rm",
[(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
Re-enable the CMN instruction. We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> llvm-svn: 158302
2012-06-11 10:07:26 +02:00
bits<4> Rn;
bits<4> Rm;
let isCommutable = 1;
let Inst{25} = 0;
let Inst{20} = 1;
let Inst{19-16} = Rn;
let Inst{15-12} = 0b0000;
let Inst{11-4} = 0b00000000;
let Inst{3-0} = Rm;
let Unpredictable{15-12} = 0b1111;
}
def CMNzrsi : AI1<0b1011, (outs),
(ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
"cmn", "\t$Rn, $shift",
[(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
GPR:$Rn, so_reg_imm:$shift)]>,
Sched<[WriteCMPsi, ReadALU]> {
Re-enable the CMN instruction. We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> llvm-svn: 158302
2012-06-11 10:07:26 +02:00
bits<4> Rn;
bits<12> shift;
let Inst{25} = 0;
let Inst{20} = 1;
let Inst{19-16} = Rn;
let Inst{15-12} = 0b0000;
let Inst{11-5} = shift{11-5};
let Inst{4} = 0;
let Inst{3-0} = shift{3-0};
let Unpredictable{15-12} = 0b1111;
}
def CMNzrsr : AI1<0b1011, (outs),
(ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
"cmn", "\t$Rn, $shift",
[(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
GPRnopc:$Rn, so_reg_reg:$shift)]>,
Sched<[WriteCMPsr, ReadALU]> {
Re-enable the CMN instruction. We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> llvm-svn: 158302
2012-06-11 10:07:26 +02:00
bits<4> Rn;
bits<12> shift;
let Inst{25} = 0;
let Inst{20} = 1;
let Inst{19-16} = Rn;
let Inst{15-12} = 0b0000;
let Inst{11-8} = shift{11-8};
let Inst{7} = 0;
let Inst{6-5} = shift{6-5};
let Inst{4} = 1;
let Inst{3-0} = shift{3-0};
let Unpredictable{15-12} = 0b1111;
}
}
[ARM] Cleanup so_imm* tblgen defintions No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
2015-01-06 16:55:09 +01:00
def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm),
(CMNri GPR:$src, mod_imm_neg:$imm)>;
Re-enable the CMN instruction. We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> llvm-svn: 158302
2012-06-11 10:07:26 +02:00
[ARM] Cleanup so_imm* tblgen defintions No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
2015-01-06 16:55:09 +01:00
def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
(CMNri GPR:$src, mod_imm_neg:$imm)>;
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// Note that TST/TEQ don't set all the same flags that CMP does!
Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug. llvm-svn: 58800
2008-11-06 09:47:38 +01:00
defm TST : AI1_cmp_irs<0b1000, "tst",
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. llvm-svn: 115010
2010-09-29 02:49:25 +02:00
IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
[ARM] Add v8.1a "Privileged Access Never" extension Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8504 llvm-svn: 235087
2015-04-16 13:34:25 +02:00
BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1,
"DecodeTSTInstruction">;
Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug. llvm-svn: 58800
2008-11-06 09:47:38 +01:00
defm TEQ : AI1_cmp_irs<0b1001, "teq",
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. llvm-svn: 115010
2010-09-29 02:49:25 +02:00
IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 llvm-svn: 119548
2010-11-17 21:13:28 +01:00
BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
- Divides the comparisons in two types: comparisons that only use N and Z flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP). - Defines the instructions: TST, TEQ (ARM) and TST (Thumb). llvm-svn: 35573
2007-04-02 03:30:03 +02:00
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. llvm-svn: 108258
2010-07-13 21:27:42 +02:00
// Pseudo i64 compares for some floating point compares.
let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
Defs = [CPSR] in {
def BCCi64 : PseudoInst<(outs),
80 column cleanup. llvm-svn: 111266
2010-08-17 20:39:16 +02:00
(ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
ARM PseudoInst instructions don't need or use an assembler string. Get rid of the operand to the pattern. llvm-svn: 119607
2010-11-18 02:38:26 +01:00
IIC_Br,
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
[(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
Sched<[WriteBr]>;
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. llvm-svn: 108258
2010-07-13 21:27:42 +02:00
def BCCZi64 : PseudoInst<(outs),
ARM PseudoInst instructions don't need or use an assembler string. Get rid of the operand to the pattern. llvm-svn: 119607
2010-11-18 02:38:26 +01:00
(ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
[(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
Sched<[WriteBr]>;
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. llvm-svn: 108258
2010-07-13 21:27:42 +02:00
} // usesCustomInserter
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
// Conditional moves
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 01:46:26 +01:00
let hasSideEffects = 0 in {
Implement ARMBaseInstrInfo::commuteInstruction() for MOVCCr. A MOVCCr instruction can be commuted by inverting the condition. This can help reduce register pressure and remove unnecessary copies in some cases. <rdar://problem/11182914> llvm-svn: 154033
2012-04-04 20:23:42 +02:00
Handle ARM MOVCC optimization in PeepholeOptimizer. Use the target independent select analysis hooks. llvm-svn: 162060
2012-08-17 01:14:20 +02:00
let isCommutable = 1, isSelect = 1 in
ARM: use TableGen patterns to select CMOV operations. Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
2013-08-22 11:57:11 +02:00
def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$false, GPR:$Rm, cmovpred:$p),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
4, IIC_iCMOVr,
ARM: use TableGen patterns to select CMOV operations. Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
2013-08-22 11:57:11 +02:00
[(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
cmovpred:$p))]>,
RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
Implement ARMBaseInstrInfo::commuteInstruction() for MOVCCr. A MOVCCr instruction can be commuted by inverting the condition. This can help reduce register pressure and remove unnecessary copies in some cases. <rdar://problem/11182914> llvm-svn: 154033
2012-04-04 20:23:42 +02:00
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
ARM: use TableGen patterns to select CMOV operations. Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
2013-08-22 11:57:11 +02:00
(ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4, IIC_iCMOVsr,
[(set GPR:$Rd,
(ARMcmov GPR:$false, so_reg_imm:$shift,
cmovpred:$p))]>,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
ARM: use TableGen patterns to select CMOV operations. Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
2013-08-22 11:57:11 +02:00
(ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
4, IIC_iCMOVsr,
ARM: use TableGen patterns to select CMOV operations. Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
2013-08-22 11:57:11 +02:00
[(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
cmovpred:$p))]>,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
2011-07-21 20:54:16 +02:00
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 llvm-svn: 119548
2010-11-17 21:13:28 +01:00
let isMoveImm = 1 in
ARM: use TableGen patterns to select CMOV operations. Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
2013-08-22 11:57:11 +02:00
def MOVCCi16
: ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4, IIC_iMOVi,
[(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
cmovpred:$p))]>,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
Sched<[WriteALU]>;
Allow use of the 16-bit literal move instruction in CMOVs for ARM mode. llvm-svn: 115884
2010-10-07 02:42:42 +02:00
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 llvm-svn: 119548
2010-11-17 21:13:28 +01:00
let isMoveImm = 1 in
Properly pseudo-ize ARM MOVCCi and MOVCCi16. llvm-svn: 127442
2011-03-11 02:09:28 +01:00
def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
[ARM] Cleanup so_imm* tblgen defintions No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
2015-01-06 16:55:09 +01:00
(ins GPR:$false, mod_imm:$imm, cmovpred:$p),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
4, IIC_iCMOVi,
[ARM] Cleanup so_imm* tblgen defintions No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
2015-01-06 16:55:09 +01:00
[(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
ARM: use TableGen patterns to select CMOV operations. Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
2013-08-22 11:57:11 +02:00
cmovpred:$p))]>,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
Add conditional mvn instructions. llvm-svn: 118935
2010-11-12 23:42:47 +01:00
Add conditional move of large immediate. llvm-svn: 118968
2010-11-13 03:25:14 +01:00
// Two instruction predicate mov immediate.
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 llvm-svn: 119548
2010-11-17 21:13:28 +01:00
let isMoveImm = 1 in
ARM: use TableGen patterns to select CMOV operations. Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
2013-08-22 11:57:11 +02:00
def MOVCCi32imm
: ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$false, i32imm:$src, cmovpred:$p),
8, IIC_iCMOVix2,
[(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
cmovpred:$p))]>,
ARM: make sure ARM-mode pseudo-inst requires IsARM I'd forgotten that "Requires" blocks override rather than add to the constraints, so my pseudo-instruction was being selected in Thumb mode leading to nonsense instructions. rdar://problem/14817358 llvm-svn: 189096
2013-08-23 12:16:39 +02:00
RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
Add conditional move of large immediate. llvm-svn: 118968
2010-11-13 03:25:14 +01:00
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 llvm-svn: 119548
2010-11-17 21:13:28 +01:00
let isMoveImm = 1 in
Properly pseudo-ize ARM MVNCCi. llvm-svn: 127482
2011-03-11 20:55:55 +01:00
def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
[ARM] Cleanup so_imm* tblgen defintions No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
2015-01-06 16:55:09 +01:00
(ins GPR:$false, mod_imm:$imm, cmovpred:$p),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
4, IIC_iCMOVi,
[ARM] Cleanup so_imm* tblgen defintions No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
2015-01-06 16:55:09 +01:00
[(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
ARM: use TableGen patterns to select CMOV operations. Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
2013-08-22 11:57:11 +02:00
cmovpred:$p))]>,
ARM sched model: Add more ALU and CMP instructions Reapply of 183258. llvm-svn: 183321
2013-06-05 18:36:51 +02:00
RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
Optimize a couple of common patterns involving conditional moves where the false value is zero. Instead of a cmov + op, issue an conditional op instead. e.g. cmp r9, r4 mov r4, #0 moveq r4, #1 orr lr, lr, r4 should be: cmp r9, r4 orreq lr, lr, #1 That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y). It's possible to extend this to ADD and SUB but I don't think they are common. rdar://8659097 llvm-svn: 151224
2012-02-23 02:19:06 +01:00
Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. llvm-svn: 222801
2014-11-26 01:46:26 +01:00
} // hasSideEffects
ARM backend contribution from Apple. llvm-svn: 33353
2007-01-19 08:51:42 +01:00
Change conditional instructions definitions, e.g. ANDCC, ARMPseudoExpand and t2PseudoExpand. llvm-svn: 153135
2012-03-20 22:28:05 +01:00
Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics. llvm-svn: 91003
2009-12-10 01:11:09 +01:00
//===----------------------------------------------------------------------===//
// Atomic operations intrinsics
//
More simple cleanup of ARM asm operand definitions. llvm-svn: 135958
2011-07-25 22:38:18 +02:00
def MemBarrierOptOperand : AsmOperandClass {
let Name = "MemBarrierOpt";
let ParserMethod = "parseMemBarrierOptOperand";
}
Overhaul memory barriers in the ARM backend. Radar 8601999. There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. llvm-svn: 117756
2010-10-30 02:54:37 +02:00
def memb_opt : Operand<i32> {
let PrintMethod = "printMemBOption";
Add support for parsing dmb/dsb instructions llvm-svn: 125055
2011-02-07 23:09:15 +01:00
let ParserMatchClass = MemBarrierOptOperand;
Tighten operand checking on memory barrier instructions. llvm-svn: 137176
2011-08-10 01:25:42 +02:00
let DecoderMethod = "DecodeMemBarrierOption";
Overhaul memory barriers in the ARM backend. Radar 8601999. There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. llvm-svn: 117756
2010-10-30 02:54:37 +02:00
}
ARM: ISB cannot be passed the same options as DMB ISB should only accepts full system sync, other options are reserved llvm-svn: 183656
2013-06-10 16:17:08 +02:00
def InstSyncBarrierOptOperand : AsmOperandClass {
let Name = "InstSyncBarrierOpt";
let ParserMethod = "parseInstSyncBarrierOptOperand";
}
def instsyncb_opt : Operand<i32> {
let PrintMethod = "printInstSyncBOption";
let ParserMatchClass = InstSyncBarrierOptOperand;
let DecoderMethod = "DecodeInstSyncBarrierOption";
}
[AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction This adds the Armv8.4-A Trace synchronization barrier (TSB) instruction. Differential Revision: https://reviews.llvm.org/D48918 llvm-svn: 336418
2018-07-06 10:03:12 +02:00
def TraceSyncBarrierOptOperand : AsmOperandClass {
let Name = "TraceSyncBarrierOpt";
let ParserMethod = "parseTraceSyncBarrierOptOperand";
}
def tsb_opt : Operand<i32> {
let PrintMethod = "printTraceSyncBOption";
let ParserMatchClass = TraceSyncBarrierOptOperand;
}
[ARM] Implement ISB memory barrier intrinsic Adds support for __builtin_arm_isb. Also corrects DSB and ISB instructions modelling by adding has-side-effects property. llvm-svn: 212276
2014-07-03 18:00:41 +02:00
// Memory barriers protect the atomic sequences
ARM memory barrier instructions are not predicable llvm-svn: 91305
2009-12-14 19:31:20 +01:00
let hasSideEffects = 1 in {
Overhaul memory barriers in the ARM backend. Radar 8601999. There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. llvm-svn: 117756
2010-10-30 02:54:37 +02:00
def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
[ARMv8] Implement the new DMB/DSB operands. This removes the custom ISD Node: MEMBARRIER and replaces it with an intrinsic. llvm-svn: 190055
2013-09-05 17:35:24 +02:00
"dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
Overhaul memory barriers in the ARM backend. Radar 8601999. There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. llvm-svn: 117756
2010-10-30 02:54:37 +02:00
Requires<[IsARM, HasDB]> {
bits<4> opt;
Add instruction encoding for DMB/DSB llvm-svn: 91053
2009-12-10 19:35:32 +01:00
let Inst{31-4} = 0xf57ff05;
Overhaul memory barriers in the ARM backend. Radar 8601999. There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. llvm-svn: 117756
2010-10-30 02:54:37 +02:00
let Inst{3-0} = opt;
Add instruction encoding for DMB/DSB llvm-svn: 91053
2009-12-10 19:35:32 +01:00
}
Added for disassembly only the variants of DMB, DSB, and ISB. llvm-svn: 96540
2010-02-18 01:19:08 +01:00
Overhaul memory barriers in the ARM backend. Radar 8601999. There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. llvm-svn: 117756
2010-10-30 02:54:37 +02:00
def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
[ARMv8] Implement the new DMB/DSB operands. This removes the custom ISD Node: MEMBARRIER and replaces it with an intrinsic. llvm-svn: 190055
2013-09-05 17:35:24 +02:00
"dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
Overhaul memory barriers in the ARM backend. Radar 8601999. There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. llvm-svn: 117756
2010-10-30 02:54:37 +02:00
Requires<[IsARM, HasDB]> {
bits<4> opt;
let Inst{31-4} = 0xf57ff04;
let Inst{3-0} = opt;
Added for disassembly only the variants of DMB, DSB, and ISB. llvm-svn: 96540
2010-02-18 01:19:08 +01:00
}
Update comments. These are for assembler, too. llvm-svn: 135107
2011-07-14 01:33:10 +02:00
// ISB has only full system option
ARM: ISB cannot be passed the same options as DMB ISB should only accepts full system sync, other options are reserved llvm-svn: 183656
2013-06-10 16:17:08 +02:00
def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
[ARM] Implement ISB memory barrier intrinsic Adds support for __builtin_arm_isb. Also corrects DSB and ISB instructions modelling by adding has-side-effects property. llvm-svn: 212276
2014-07-03 18:00:41 +02:00
"isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
Overhaul memory barriers in the ARM backend. Radar 8601999. There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. llvm-svn: 117756
2010-10-30 02:54:37 +02:00
Requires<[IsARM, HasDB]> {
ARM ISB instruction assembly parsing. The ISB instruction takes an optional operand, just like DMB/DSB. Typically only 'sy' is meaningful. llvm-svn: 135156
2011-07-14 20:00:31 +02:00
bits<4> opt;
Cleaned up the for-disassembly-only entries in the arm instruction table so that the memory barrier variants (other than 'SY' full system domain read and write) are treated as one instruction with option operand. llvm-svn: 110951
2010-08-12 22:46:17 +02:00
let Inst{31-4} = 0xf57ff06;
ARM ISB instruction assembly parsing. The ISB instruction takes an optional operand, just like DMB/DSB. Typically only 'sy' is meaningful. llvm-svn: 135156
2011-07-14 20:00:31 +02:00
let Inst{3-0} = opt;
Added for disassembly only the variants of DMB, DSB, and ISB. llvm-svn: 96540
2010-02-18 01:19:08 +01:00
}
[AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction This adds the Armv8.4-A Trace synchronization barrier (TSB) instruction. Differential Revision: https://reviews.llvm.org/D48918 llvm-svn: 336418
2018-07-06 10:03:12 +02:00
let hasNoSchedulingInfo = 1 in
def TSB : AInoP<(outs), (ins tsb_opt:$opt), MiscFrm, NoItinerary,
"tsb", "\t$opt", []>, Requires<[IsARM, HasV8_4a]> {
let Inst{31-0} = 0xe320f012;
}
[ARM] Implement ISB memory barrier intrinsic Adds support for __builtin_arm_isb. Also corrects DSB and ISB instructions modelling by adding has-side-effects property. llvm-svn: 212276
2014-07-03 18:00:41 +02:00
}
Added for disassembly only the variants of DMB, DSB, and ISB. llvm-svn: 96540
2010-02-18 01:19:08 +01:00
[ARM][v8.5A] Add speculation barrier to ARM & Thumb instruction sets This is a new barrier which limits speculative execution of the instructions following it. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52477 llvm-svn: 343213
2018-09-27 15:41:14 +02:00
// Armv8.5-A speculation barrier
def SB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "sb", "", []>,
[ARM] Add command-line option for SB SB (Speculative Barrier) is only mandatory from 8.5 onwards but is optional from Armv8.0-A. This patch adds a command line option to enable SB, as it was previously only possible to enable by selecting -march=armv8.5-a. This patch also renames FeatureSpecRestrict to FeatureSB. Reviewed By: olista01, LukeCheeseman Differential Revision: https://reviews.llvm.org/D55990 llvm-svn: 350299
2019-01-03 13:09:12 +01:00
Requires<[IsARM, HasSB]>, Sched<[]> {
[ARM][v8.5A] Add speculation barrier to ARM & Thumb instruction sets This is a new barrier which limits speculative execution of the instructions following it. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52477 llvm-svn: 343213
2018-09-27 15:41:14 +02:00
let Inst{31-0} = 0xf57ff070;
let Unpredictable = 0x000fff0f;
let hasSideEffects = 1;
}
[ARM] Use the load-acquire/store-release instructions optimally in AArch32. Patch by Artyom Skrobov. llvm-svn: 191428
2013-09-26 14:22:36 +02:00
let usesCustomInserter = 1, Defs = [CPSR] in {
Typo. llvm-svn: 154953
2012-04-17 23:48:36 +02:00
// Pseudo instruction that combines movs + predicated rsbmi
Reapply r141365 now that PR11107 is fixed. llvm-svn: 141591
2011-10-11 00:59:55 +02:00
// to implement integer ABS
[ARM] Use the load-acquire/store-release instructions optimally in AArch32. Patch by Artyom Skrobov. llvm-svn: 191428
2013-09-26 14:22:36 +02:00
def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress. llvm-svn: 91090
2009-12-11 02:42:04 +01:00
}
[ARM] Set Defs = [CPSR] for COPY_STRUCT_BYVAL, as it clobbers CPSR. Fixes PR35023. Reviewers: MatzeB, t.p.northover, sunfish, qcolombet, efriedma Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D55909 llvm-svn: 349935
2018-12-21 19:07:10 +01:00
let usesCustomInserter = 1, Defs = [CPSR] in {
ARM: support struct byval in llvm We handle struct byval by inserting a pseudo op, which will be expanded to a loop at ExpandISelPseudos. A separate patch for clang will be submitted to enable struct byval. rdar://9877866 llvm-svn: 157793
2012-06-01 04:44:42 +02:00
def COPY_STRUCT_BYVAL_I32 : PseudoInst<
ARM: properly handle alignment for struct byval. Factor out the expansion code into a function. This change is to be enabled in clang. rdar://9877866 llvm-svn: 157830
2012-06-01 21:33:18 +02:00
(outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
ARM: support struct byval in llvm We handle struct byval by inserting a pseudo op, which will be expanded to a loop at ExpandISelPseudos. A separate patch for clang will be submitted to enable struct byval. rdar://9877866 llvm-svn: 157793
2012-06-01 04:44:42 +02:00
NoItinerary,
ARM: properly handle alignment for struct byval. Factor out the expansion code into a function. This change is to be enabled in clang. rdar://9877866 llvm-svn: 157830
2012-06-01 21:33:18 +02:00
[(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
ARM: support struct byval in llvm We handle struct byval by inserting a pseudo op, which will be expanded to a loop at ExpandISelPseudos. A separate patch for clang will be submitted to enable struct byval. rdar://9877866 llvm-svn: 157793
2012-06-01 04:44:42 +02:00
}
[ARM] Modify codegen for memcpy intrinsic to prefer LDM/STM. We were previously codegen'ing memcpy as regular load/store operations and hoping that the register allocator would allocate registers in ascending order so that we could apply an LDM/STM combine after register allocation. According to the commit that first introduced this code (r37179), we planned to teach the register allocator to allocate the registers in ascending order. This never got implemented, and up to now we've been stuck with very poor codegen. A much simpler approach for achieving better codegen is to create MEMCPY pseudo instructions, attach scratch virtual registers to them and then, post register allocation, expand the MEMCPYs into LDM/STM pairs using the scratch registers. The register allocator will have picked arbitrary registers which we sort when expanding the MEMCPY. This approach also avoids the need to repeatedly calculate offsets which ultimately ought to be eliminated pre-RA in order to decrease register pressure. Fixes PR9199 and PR23768. [This is based on Peter Collingbourne's r238473 which was reverted.] Differential Revision: http://reviews.llvm.org/D13239 Change-Id: I727543c2e94136e0f80b8e22d5642d7b9ee5b458 Author: Peter Collingbourne <peter@pcc.me.uk> llvm-svn: 249322
2015-10-05 16:49:54 +02:00
let hasPostISelHook = 1, Constraints = "$newdst = $dst, $newsrc = $src" in {
// %newsrc, %newdst = MEMCPY %dst, %src, N, ...N scratch regs...
// Copies N registers worth of memory from address %src to address %dst
// and returns the incremented addresses. N scratch register will
// be attached for the copy to use.
def MEMCPY : PseudoInst<
(outs GPR:$newdst, GPR:$newsrc),
(ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops),
NoItinerary,
[(set GPR:$newdst, GPR:$newsrc,
(ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>;
}
ARM: implement ldrex, strex and clrex intrinsics Intrinsics already existed for the 64-bit variants, so these support operations of size at most 32-bits. llvm-svn: 186392
2013-07-16 11:46:55 +02:00
def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
}]>;
def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
}]>;
def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
}]>;
def strex_1 : PatFrag<(ops node:$val, node:$ptr),
(int_arm_strex node:$val, node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
}]>;
def strex_2 : PatFrag<(ops node:$val, node:$ptr),
(int_arm_strex node:$val, node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
}]>;
def strex_4 : PatFrag<(ops node:$val, node:$ptr),
(int_arm_strex node:$val, node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
}]>;
ARM: add intrinsics for the v8 ldaex/stlex We've already got versions without the barriers, so this just adds IR-level support for generating the new v8 ones. rdar://problem/16227836 llvm-svn: 204813
2014-03-26 15:39:31 +01:00
def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
}]>;
def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
}]>;
def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
}]>;
def stlex_1 : PatFrag<(ops node:$val, node:$ptr),
(int_arm_stlex node:$val, node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
}]>;
def stlex_2 : PatFrag<(ops node:$val, node:$ptr),
(int_arm_stlex node:$val, node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
}]>;
def stlex_4 : PatFrag<(ops node:$val, node:$ptr),
(int_arm_stlex node:$val, node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
}]>;
Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress. llvm-svn: 91090
2009-12-11 02:42:04 +01:00
let mayLoad = 1 in {
ARM: rename addrmode7 to addr_offset_none. Use a more descriptive name so the code is more self-documenting. llvm-svn: 136704
2011-08-02 20:07:32 +02:00
def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
[ARMv8] Add MC support for the new load/store acquire/release instructions. llvm-svn: 189388
2013-08-27 19:38:16 +02:00
NoItinerary, "ldrexb", "\t$Rt, $addr",
ARM: implement ldrex, strex and clrex intrinsics Intrinsics already existed for the 64-bit variants, so these support operations of size at most 32-bits. llvm-svn: 186392
2013-07-16 11:46:55 +02:00
[(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
Tidy up. 80 columns. llvm-svn: 136705
2011-08-02 20:16:36 +02:00
def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
ARM: implement ldrex, strex and clrex intrinsics Intrinsics already existed for the 64-bit variants, so these support operations of size at most 32-bits. llvm-svn: 186392
2013-07-16 11:46:55 +02:00
NoItinerary, "ldrexh", "\t$Rt, $addr",
[(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
ARM: implement ldrex, strex and clrex intrinsics Intrinsics already existed for the 64-bit variants, so these support operations of size at most 32-bits. llvm-svn: 186392
2013-07-16 11:46:55 +02:00
NoItinerary, "ldrex", "\t$Rt, $addr",
[(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs to load/store i64 values. Since there's no current support to explicitly declare such restrictions, implement it by using specific hardcoded register pairs during isel. llvm-svn: 132248
2011-05-28 06:07:29 +02:00
let hasExtraDefRegAllocReq = 1 in
[ARMv8] Add MC support for the new load/store acquire/release instructions. llvm-svn: 189388
2013-08-27 19:38:16 +02:00
def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
Separate decoding for STREXD and LDREXD to make each work better. llvm-svn: 137476
2011-08-12 19:58:32 +02:00
let DecoderMethod = "DecodeDoubleRegLoad";
Fix decoding support for STREXD and LDREXD. llvm-svn: 137356
2011-08-11 23:34:58 +02:00
}
[ARMv8] Add MC support for the new load/store acquire/release instructions. llvm-svn: 189388
2013-08-27 19:38:16 +02:00
def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
ARM: add intrinsics for the v8 ldaex/stlex We've already got versions without the barriers, so this just adds IR-level support for generating the new v8 ones. rdar://problem/16227836 llvm-svn: 204813
2014-03-26 15:39:31 +01:00
NoItinerary, "ldaexb", "\t$Rt, $addr",
[(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
[ARMv8] Add MC support for the new load/store acquire/release instructions. llvm-svn: 189388
2013-08-27 19:38:16 +02:00
def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
ARM: add intrinsics for the v8 ldaex/stlex We've already got versions without the barriers, so this just adds IR-level support for generating the new v8 ones. rdar://problem/16227836 llvm-svn: 204813
2014-03-26 15:39:31 +01:00
NoItinerary, "ldaexh", "\t$Rt, $addr",
[(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
[ARMv8] Add MC support for the new load/store acquire/release instructions. llvm-svn: 189388
2013-08-27 19:38:16 +02:00
def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
ARM: add intrinsics for the v8 ldaex/stlex We've already got versions without the barriers, so this just adds IR-level support for generating the new v8 ones. rdar://problem/16227836 llvm-svn: 204813
2014-03-26 15:39:31 +01:00
NoItinerary, "ldaex", "\t$Rt, $addr",
[(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
[ARMv8] Add MC support for the new load/store acquire/release instructions. llvm-svn: 189388
2013-08-27 19:38:16 +02:00
let hasExtraDefRegAllocReq = 1 in
def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
let DecoderMethod = "DecodeDoubleRegLoad";
}
Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress. llvm-svn: 91090
2009-12-11 02:42:04 +01:00
}
ARM mode LDREX*/STREX* binary encodings. llvm-svn: 117695
2010-10-29 21:58:57 +02:00
let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
ARM: rename addrmode7 to addr_offset_none. Use a more descriptive name so the code is more self-documenting. llvm-svn: 136704
2011-08-02 20:07:32 +02:00
def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
ARM: implement ldrex, strex and clrex intrinsics Intrinsics already existed for the 64-bit variants, so these support operations of size at most 32-bits. llvm-svn: 186392
2013-07-16 11:46:55 +02:00
NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
ARM: add intrinsics for the v8 ldaex/stlex We've already got versions without the barriers, so this just adds IR-level support for generating the new v8 ones. rdar://problem/16227836 llvm-svn: 204813
2014-03-26 15:39:31 +01:00
[(set GPR:$Rd, (strex_1 GPR:$Rt,
addr_offset_none:$addr))]>;
ARM: rename addrmode7 to addr_offset_none. Use a more descriptive name so the code is more self-documenting. llvm-svn: 136704
2011-08-02 20:07:32 +02:00
def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
ARM: implement ldrex, strex and clrex intrinsics Intrinsics already existed for the 64-bit variants, so these support operations of size at most 32-bits. llvm-svn: 186392
2013-07-16 11:46:55 +02:00
NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
ARM: add intrinsics for the v8 ldaex/stlex We've already got versions without the barriers, so this just adds IR-level support for generating the new v8 ones. rdar://problem/16227836 llvm-svn: 204813
2014-03-26 15:39:31 +01:00
[(set GPR:$Rd, (strex_2 GPR:$Rt,
addr_offset_none:$addr))]>;
ARM: rename addrmode7 to addr_offset_none. Use a more descriptive name so the code is more self-documenting. llvm-svn: 136704
2011-08-02 20:07:32 +02:00
def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
ARM: implement ldrex, strex and clrex intrinsics Intrinsics already existed for the 64-bit variants, so these support operations of size at most 32-bits. llvm-svn: 186392
2013-07-16 11:46:55 +02:00
NoItinerary, "strex", "\t$Rd, $Rt, $addr",
ARM: add intrinsics for the v8 ldaex/stlex We've already got versions without the barriers, so this just adds IR-level support for generating the new v8 ones. rdar://problem/16227836 llvm-svn: 204813
2014-03-26 15:39:31 +01:00
[(set GPR:$Rd, (strex_4 GPR:$Rt,
addr_offset_none:$addr))]>;
Add missed mayStore flag to STREXD / t2STREXD llvm-svn: 148742
2012-01-23 23:57:52 +01:00
let hasExtraSrcRegAllocReq = 1 in
ARM mode LDREX*/STREX* binary encodings. llvm-svn: 117695
2010-10-29 21:58:57 +02:00
def STREXD : AIstrex<0b01, (outs GPR:$Rd),
Remove hard coded registers in ARM ldrexd and strexd instructions This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
2012-11-16 22:55:34 +01:00
(ins GPRPairOp:$Rt, addr_offset_none:$addr),
NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
Separate decoding for STREXD and LDREXD to make each work better. llvm-svn: 137476
2011-08-12 19:58:32 +02:00
let DecoderMethod = "DecodeDoubleRegStore";
Fix decoding support for STREXD and LDREXD. llvm-svn: 137356
2011-08-11 23:34:58 +02:00
}
[ARMv8] Add MC support for the new load/store acquire/release instructions. llvm-svn: 189388
2013-08-27 19:38:16 +02:00
def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
ARM: add intrinsics for the v8 ldaex/stlex We've already got versions without the barriers, so this just adds IR-level support for generating the new v8 ones. rdar://problem/16227836 llvm-svn: 204813
2014-03-26 15:39:31 +01:00
[(set GPR:$Rd,
(stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
[ARMv8] Add MC support for the new load/store acquire/release instructions. llvm-svn: 189388
2013-08-27 19:38:16 +02:00
def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
ARM: add intrinsics for the v8 ldaex/stlex We've already got versions without the barriers, so this just adds IR-level support for generating the new v8 ones. rdar://problem/16227836 llvm-svn: 204813
2014-03-26 15:39:31 +01:00
[(set GPR:$Rd,
(stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
[ARMv8] Add MC support for the new load/store acquire/release instructions. llvm-svn: 189388
2013-08-27 19:38:16 +02:00
def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
ARM: add intrinsics for the v8 ldaex/stlex We've already got versions without the barriers, so this just adds IR-level support for generating the new v8 ones. rdar://problem/16227836 llvm-svn: 204813
2014-03-26 15:39:31 +01:00
[(set GPR:$Rd,
(stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
[ARMv8] Add MC support for the new load/store acquire/release instructions. llvm-svn: 189388
2013-08-27 19:38:16 +02:00
let hasExtraSrcRegAllocReq = 1 in
def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
(ins GPRPairOp:$Rt, addr_offset_none:$addr),
NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
let DecoderMethod = "DecodeDoubleRegStore";
}
Add missed mayStore flag to STREXD / t2STREXD llvm-svn: 148742
2012-01-23 23:57:52 +01:00
}
Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress. llvm-svn: 91090
2009-12-11 02:42:04 +01:00
ARM: implement ldrex, strex and clrex intrinsics Intrinsics already existed for the 64-bit variants, so these support operations of size at most 32-bits. llvm-svn: 186392
2013-07-16 11:46:55 +02:00
def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
[(int_arm_clrex)]>,
Support clrex instruction on ARMv6k. Patch by Andrew Turner. llvm-svn: 256505
2015-12-28 18:47:23 +01:00
Requires<[IsARM, HasV6K]> {
ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS. llvm-svn: 117702
2010-10-29 22:21:36 +02:00
let Inst{31-0} = 0b11110101011111111111000000011111;
Added CLREX (Clear-Exclusive) for disassembly only. A8.6.30 llvm-svn: 96523
2010-02-17 23:37:58 +01:00
}
ARM: implement ldrex, strex and clrex intrinsics Intrinsics already existed for the 64-bit variants, so these support operations of size at most 32-bits. llvm-svn: 186392
2013-07-16 11:46:55 +02:00
def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
(STREXB GPR:$Rt, addr_offset_none:$addr)>;
def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
(STREXH GPR:$Rt, addr_offset_none:$addr)>;
ARM: add intrinsics for the v8 ldaex/stlex We've already got versions without the barriers, so this just adds IR-level support for generating the new v8 ones. rdar://problem/16227836 llvm-svn: 204813
2014-03-26 15:39:31 +01:00
def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
(STLEXB GPR:$Rt, addr_offset_none:$addr)>;
def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
(STLEXH GPR:$Rt, addr_offset_none:$addr)>;
[ARM] Use the load-acquire/store-release instructions optimally in AArch32. Patch by Artyom Skrobov. llvm-svn: 191428
2013-09-26 14:22:36 +02:00
class acquiring_load<PatFrag base>
: PatFrag<(ops node:$ptr), (base node:$ptr), [{
AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
NFC: make AtomicOrdering an enum class Summary: In the context of http://wg21.link/lwg2445 C++ uses the concept of 'stronger' ordering but doesn't define it properly. This should be fixed in C++17 barring a small question that's still open. The code currently plays fast and loose with the AtomicOrdering enum. Using an enum class is one step towards tightening things. I later also want to tighten related enums, such as clang's AtomicOrderingKind (which should be shared with LLVM as a 'C++ ABI' enum). This change touches a few lines of code which can be improved later, I'd like to keep it as NFC for now as it's already quite complex. I have related changes for clang. As a follow-up I'll add: bool operator<(AtomicOrdering, AtomicOrdering) = delete; bool operator>(AtomicOrdering, AtomicOrdering) = delete; bool operator<=(AtomicOrdering, AtomicOrdering) = delete; bool operator>=(AtomicOrdering, AtomicOrdering) = delete; This is separate so that clang and LLVM changes don't need to be in sync. Reviewers: jyknight, reames Subscribers: jyknight, llvm-commits Differential Revision: http://reviews.llvm.org/D18775 llvm-svn: 265602
2016-04-06 23:19:33 +02:00
return isAcquireOrStronger(Ordering);
[ARM] Use the load-acquire/store-release instructions optimally in AArch32. Patch by Artyom Skrobov. llvm-svn: 191428
2013-09-26 14:22:36 +02:00
}]>;
def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
class releasing_store<PatFrag base>
: PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
NFC: make AtomicOrdering an enum class Summary: In the context of http://wg21.link/lwg2445 C++ uses the concept of 'stronger' ordering but doesn't define it properly. This should be fixed in C++17 barring a small question that's still open. The code currently plays fast and loose with the AtomicOrdering enum. Using an enum class is one step towards tightening things. I later also want to tighten related enums, such as clang's AtomicOrderingKind (which should be shared with LLVM as a 'C++ ABI' enum). This change touches a few lines of code which can be improved later, I'd like to keep it as NFC for now as it's already quite complex. I have related changes for clang. As a follow-up I'll add: bool operator<(AtomicOrdering, AtomicOrdering) = delete; bool operator>(AtomicOrdering, AtomicOrdering) = delete; bool operator<=(AtomicOrdering, AtomicOrdering) = delete; bool operator>=(AtomicOrdering, AtomicOrdering) = delete; This is separate so that clang and LLVM changes don't need to be in sync. Reviewers: jyknight, reames Subscribers: jyknight, llvm-commits Differential Revision: http://reviews.llvm.org/D18775 llvm-svn: 265602
2016-04-06 23:19:33 +02:00
return isReleaseOrStronger(Ordering);
[ARM] Use the load-acquire/store-release instructions optimally in AArch32. Patch by Artyom Skrobov. llvm-svn: 191428
2013-09-26 14:22:36 +02:00
}]>;
def atomic_store_release_8 : releasing_store<atomic_store_8>;
def atomic_store_release_16 : releasing_store<atomic_store_16>;
def atomic_store_release_32 : releasing_store<atomic_store_32>;
let AddedComplexity = 8 in {
def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
}
[ARM] Avoid using ARM instructions in Thumb mode The Requires class overrides the target requirements of an instruction, rather than adding to them, so all ARM instructions need to include the IsARM predicate when they have overwitten requirements. This caused the swp and swpb instructions to be allowed in thumb mode assembly, and the ARM encoding of CDP to be selected in codegen (which is different for conditional instructions). Differential Revision: https://reviews.llvm.org/D29283 llvm-svn: 293634
2017-01-31 15:35:01 +01:00
// SWP/SWPB are deprecated in V6/V7 and optional in v7VE.
// FIXME Use InstAlias to generate LDREX/STREX pairs instead.
ARM SWP instructions store, too, not just load. llvm-svn: 136096
2011-07-26 19:11:05 +02:00
let mayLoad = 1, mayStore = 1 in {
Tidy up. 80 columns, whitespace, et. al. llvm-svn: 155399
2012-04-24 00:04:10 +02:00
def SWP : AIswp<0, (outs GPRnopc:$Rt),
ARMv8: SWP and SWPB are obsoleted on ARMv8. llvm-svn: 188288
2013-08-13 18:40:47 +02:00
(ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
[ARM] Avoid using ARM instructions in Thumb mode The Requires class overrides the target requirements of an instruction, rather than adding to them, so all ARM instructions need to include the IsARM predicate when they have overwitten requirements. This caused the swp and swpb instructions to be allowed in thumb mode assembly, and the ARM encoding of CDP to be selected in codegen (which is different for conditional instructions). Differential Revision: https://reviews.llvm.org/D29283 llvm-svn: 293634
2017-01-31 15:35:01 +01:00
Requires<[IsARM,PreV8]>;
Tidy up. 80 columns, whitespace, et. al. llvm-svn: 155399
2012-04-24 00:04:10 +02:00
def SWPB: AIswp<1, (outs GPRnopc:$Rt),
ARMv8: SWP and SWPB are obsoleted on ARMv8. llvm-svn: 188288
2013-08-13 18:40:47 +02:00
(ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
[ARM] Avoid using ARM instructions in Thumb mode The Requires class overrides the target requirements of an instruction, rather than adding to them, so all ARM instructions need to include the IsARM predicate when they have overwitten requirements. This caused the swp and swpb instructions to be allowed in thumb mode assembly, and the ARM encoding of CDP to be selected in codegen (which is different for conditional instructions). Differential Revision: https://reviews.llvm.org/D29283 llvm-svn: 293634
2017-01-31 15:35:01 +01:00
Requires<[IsARM,PreV8]>;
Add SWP (Swap) and SWPB (Swap Byte) for disassembly only. llvm-svn: 96010
2010-02-12 21:48:24 +01:00
}
ARM TLS: implement "general dynamic", "initial exec" and "local exec" models. llvm-svn: 36506
2007-04-27 15:54:47 +02:00
//===----------------------------------------------------------------------===//
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
// Coprocessor Instructions.
Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2, MRRC, MRRc2. For disassembly only. llvm-svn: 95955
2010-02-12 02:44:23 +01:00
//
Range checking for CDP[2] immediates. llvm-svn: 135092
2011-07-14 00:01:08 +02:00
def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
- Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions. - Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t hem. llvm-svn: 123927
2011-01-20 19:06:58 +01:00
NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
Fold ARM coprocessor intrinsics patterns into the instructions defs whenever it's possible. llvm-svn: 130764
2011-05-03 19:29:29 +02:00
[(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings) llvm-svn: 194261
2013-11-08 17:16:30 +01:00
imm:$CRm, imm:$opc2)]>,
[ARM] Avoid using ARM instructions in Thumb mode The Requires class overrides the target requirements of an instruction, rather than adding to them, so all ARM instructions need to include the IsARM predicate when they have overwitten requirements. This caused the swp and swpb instructions to be allowed in thumb mode assembly, and the ARM encoding of CDP to be selected in codegen (which is different for conditional instructions). Differential Revision: https://reviews.llvm.org/D29283 llvm-svn: 293634
2017-01-31 15:35:01 +01:00
Requires<[IsARM,PreV8]> {
- Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions. - Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t hem. llvm-svn: 123927
2011-01-20 19:06:58 +01:00
bits<4> opc1;
bits<4> CRn;
bits<4> CRd;
bits<4> cop;
bits<3> opc2;
bits<4> CRm;
let Inst{3-0} = CRm;
let Inst{4} = 0;
let Inst{7-5} = opc2;
let Inst{11-8} = cop;
let Inst{15-12} = CRd;
let Inst{19-16} = CRn;
let Inst{23-20} = opc1;
[ARM] Assembler support for the ARMv8.2a dot product instructions Commit r310480 added the AArch64 ARMv8.2a dot product instructions; this adds the AArch32 instructions. Differential Revision: https://reviews.llvm.org/D36575 llvm-svn: 310701
2017-08-11 11:52:30 +02:00
let DecoderNamespace = "CoProc";
- Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions. - Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t hem. llvm-svn: 123927
2011-01-20 19:06:58 +01:00
}
This reverts r155000. The cdp2 instruction should have the same restrictions as cdp on the co-processor registers. VFP instructions on v8/AArch32 share the same encoding space as cdp2. llvm-svn: 184445
2013-06-20 19:42:36 +02:00
def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
Range checking for CDP[2] immediates. llvm-svn: 135092
2011-07-14 00:01:08 +02:00
c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
- Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions. - Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t hem. llvm-svn: 123927
2011-01-20 19:06:58 +01:00
NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
Fold ARM coprocessor intrinsics patterns into the instructions defs whenever it's possible. llvm-svn: 130764
2011-05-03 19:29:29 +02:00
[(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings) llvm-svn: 194261
2013-11-08 17:16:30 +01:00
imm:$CRm, imm:$opc2)]>,
[ARM] Avoid using ARM instructions in Thumb mode The Requires class overrides the target requirements of an instruction, rather than adding to them, so all ARM instructions need to include the IsARM predicate when they have overwitten requirements. This caused the swp and swpb instructions to be allowed in thumb mode assembly, and the ARM encoding of CDP to be selected in codegen (which is different for conditional instructions). Differential Revision: https://reviews.llvm.org/D29283 llvm-svn: 293634
2017-01-31 15:35:01 +01:00
Requires<[IsARM,PreV8]> {
Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2, MRRC, MRRc2. For disassembly only. llvm-svn: 95955
2010-02-12 02:44:23 +01:00
let Inst{31-28} = 0b1111;
- Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions. - Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t hem. llvm-svn: 123927
2011-01-20 19:06:58 +01:00
bits<4> opc1;
bits<4> CRn;
bits<4> CRd;
bits<4> cop;
bits<3> opc2;
bits<4> CRm;
let Inst{3-0} = CRm;
let Inst{4} = 0;
let Inst{7-5} = opc2;
let Inst{11-8} = cop;
let Inst{15-12} = CRd;
let Inst{19-16} = CRn;
let Inst{23-20} = opc1;
[ARM] Assembler support for the ARMv8.2a dot product instructions Commit r310480 added the AArch64 ARMv8.2a dot product instructions; this adds the AArch32 instructions. Differential Revision: https://reviews.llvm.org/D36575 llvm-svn: 310701
2017-08-11 11:52:30 +02:00
let DecoderNamespace = "CoProc";
Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2, MRRC, MRRc2. For disassembly only. llvm-svn: 95955
2010-02-12 02:44:23 +01:00
}
Apply again changes to support ARM memory asm parsing. I removed all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128689
2011-04-01 01:26:08 +02:00
class ACI<dag oops, dag iops, string opc, string asm,
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 14:39:30 +02:00
list<dag> pattern, IndexMode im = IndexModeNone>
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
: I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 14:39:30 +02:00
opc, asm, "", pattern> {
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
let Inst{27-25} = 0b110;
}
class ACInoP<dag oops, dag iops, string opc, string asm,
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 14:39:30 +02:00
list<dag> pattern, IndexMode im = IndexModeNone>
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
: InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 14:39:30 +02:00
opc, asm, "", pattern> {
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
let Inst{31-28} = 0b1111;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
let Inst{27-25} = 0b110;
}
[ARM] Assembler support for the ARMv8.2a dot product instructions Commit r310480 added the AArch64 ARMv8.2a dot product instructions; this adds the AArch32 instructions. Differential Revision: https://reviews.llvm.org/D36575 llvm-svn: 310701
2017-08-11 11:52:30 +02:00
let DecoderNamespace = "CoProc" in {
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 14:39:30 +02:00
multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> {
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 14:39:30 +02:00
asm, "\t$cop, $CRd, $addr", pattern> {
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
bits<13> addr;
bits<4> cop;
bits<4> CRd;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
let Inst{24} = 1; // P = 1
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
let Inst{23} = addr{8};
let Inst{22} = Dbit;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
let Inst{21} = 0; // W = 0
let Inst{20} = load;
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
let Inst{19-16} = addr{12-9};
let Inst{15-12} = CRd;
let Inst{11-8} = cop;
let Inst{7-0} = addr{7-0};
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeCopMemInstruction";
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
}
ARM: Correct printing of pre-indexed operands. According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
2013-04-12 20:47:25 +02:00
def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 14:39:30 +02:00
asm, "\t$cop, $CRd, $addr!", [], IndexModePre> {
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
bits<13> addr;
bits<4> cop;
bits<4> CRd;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
let Inst{24} = 1; // P = 1
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
let Inst{23} = addr{8};
let Inst{22} = Dbit;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
let Inst{21} = 1; // W = 1
let Inst{20} = load;
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
let Inst{19-16} = addr{12-9};
let Inst{15-12} = CRd;
let Inst{11-8} = cop;
let Inst{7-0} = addr{7-0};
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeCopMemInstruction";
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
}
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
postidx_imm8s4:$offset),
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 14:39:30 +02:00
asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> {
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
bits<9> offset;
bits<4> addr;
bits<4> cop;
bits<4> CRd;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
let Inst{24} = 0; // P = 0
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
let Inst{23} = offset{8};
let Inst{22} = Dbit;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
let Inst{21} = 1; // W = 1
let Inst{20} = load;
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
let Inst{19-16} = addr;
let Inst{15-12} = CRd;
let Inst{11-8} = cop;
let Inst{7-0} = offset{7-0};
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeCopMemInstruction";
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
}
def _OPTION : ACI<(outs),
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
(ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
ARM parsing and encoding for the <option> form of LDC/STC instructions. llvm-svn: 141786
2011-10-12 19:34:41 +02:00
coproc_option_imm:$option),
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 14:39:30 +02:00
asm, "\t$cop, $CRd, $addr, $option", []> {
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
bits<8> option;
bits<4> addr;
bits<4> cop;
bits<4> CRd;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
let Inst{24} = 0; // P = 0
let Inst{23} = 1; // U = 1
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
let Inst{22} = Dbit;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
let Inst{21} = 0; // W = 0
let Inst{20} = load;
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
let Inst{19-16} = addr;
let Inst{15-12} = CRd;
let Inst{11-8} = cop;
let Inst{7-0} = option;
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeCopMemInstruction";
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
}
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
}
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 14:39:30 +02:00
multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> {
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 14:39:30 +02:00
asm, "\t$cop, $CRd, $addr", pattern> {
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
bits<13> addr;
bits<4> cop;
bits<4> CRd;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
let Inst{24} = 1; // P = 1
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
let Inst{23} = addr{8};
let Inst{22} = Dbit;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
let Inst{21} = 0; // W = 0
let Inst{20} = load;
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
let Inst{19-16} = addr{12-9};
let Inst{15-12} = CRd;
let Inst{11-8} = cop;
let Inst{7-0} = addr{7-0};
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeCopMemInstruction";
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
}
ARM: Correct printing of pre-indexed operands. According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
2013-04-12 20:47:25 +02:00
def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 14:39:30 +02:00
asm, "\t$cop, $CRd, $addr!", [], IndexModePre> {
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
bits<13> addr;
bits<4> cop;
bits<4> CRd;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
let Inst{24} = 1; // P = 1
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
let Inst{23} = addr{8};
let Inst{22} = Dbit;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
let Inst{21} = 1; // W = 1
let Inst{20} = load;
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
let Inst{19-16} = addr{12-9};
let Inst{15-12} = CRd;
let Inst{11-8} = cop;
let Inst{7-0} = addr{7-0};
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeCopMemInstruction";
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
}
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
postidx_imm8s4:$offset),
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 14:39:30 +02:00
asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> {
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
bits<9> offset;
bits<4> addr;
bits<4> cop;
bits<4> CRd;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
let Inst{24} = 0; // P = 0
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
let Inst{23} = offset{8};
let Inst{22} = Dbit;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
let Inst{21} = 1; // W = 1
let Inst{20} = load;
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
let Inst{19-16} = addr;
let Inst{15-12} = CRd;
let Inst{11-8} = cop;
let Inst{7-0} = offset{7-0};
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeCopMemInstruction";
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
}
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
def _OPTION : ACInoP<(outs),
(ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
ARM parsing and encoding for the <option> form of LDC/STC instructions. llvm-svn: 141786
2011-10-12 19:34:41 +02:00
coproc_option_imm:$option),
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 14:39:30 +02:00
asm, "\t$cop, $CRd, $addr, $option", []> {
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
bits<8> option;
bits<4> addr;
bits<4> cop;
bits<4> CRd;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
let Inst{24} = 0; // P = 0
let Inst{23} = 1; // U = 1
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
let Inst{22} = Dbit;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
let Inst{21} = 0; // W = 0
let Inst{20} = load;
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
2011-10-11 23:55:36 +02:00
let Inst{19-16} = addr;
let Inst{15-12} = CRd;
let Inst{11-8} = cop;
let Inst{7-0} = option;
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
let DecoderMethod = "DecodeCopMemInstruction";
}
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
}
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 14:39:30 +02:00
defm LDC : LdStCop <1, 0, "ldc", [(int_arm_ldc imm:$cop, imm:$CRd, addrmode5:$addr)]>;
defm LDCL : LdStCop <1, 1, "ldcl", [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)]>;
[ARM] Avoid using ARM instructions in Thumb mode The Requires class overrides the target requirements of an instruction, rather than adding to them, so all ARM instructions need to include the IsARM predicate when they have overwitten requirements. This caused the swp and swpb instructions to be allowed in thumb mode assembly, and the ARM encoding of CDP to be selected in codegen (which is different for conditional instructions). Differential Revision: https://reviews.llvm.org/D29283 llvm-svn: 293634
2017-01-31 15:35:01 +01:00
defm LDC2 : LdSt2Cop<1, 0, "ldc2", [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
defm LDC2L : LdSt2Cop<1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
[ARM] Add backend support for load/store intrinsics. Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
2016-05-31 14:39:30 +02:00
defm STC : LdStCop <0, 0, "stc", [(int_arm_stc imm:$cop, imm:$CRd, addrmode5:$addr)]>;
defm STCL : LdStCop <0, 1, "stcl", [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)]>;
[ARM] Avoid using ARM instructions in Thumb mode The Requires class overrides the target requirements of an instruction, rather than adding to them, so all ARM instructions need to include the IsARM predicate when they have overwitten requirements. This caused the swp and swpb instructions to be allowed in thumb mode assembly, and the ARM encoding of CDP to be selected in codegen (which is different for conditional instructions). Differential Revision: https://reviews.llvm.org/D29283 llvm-svn: 293634
2017-01-31 15:35:01 +01:00
defm STC2 : LdSt2Cop<0, 0, "stc2", [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
defm STC2L : LdSt2Cop<0, 1, "stc2l", [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
[ARM] Assembler support for the ARMv8.2a dot product instructions Commit r310480 added the AArch64 ARMv8.2a dot product instructions; this adds the AArch32 instructions. Differential Revision: https://reviews.llvm.org/D36575 llvm-svn: 310701
2017-08-11 11:52:30 +02:00
} // DecoderNamespace = "CoProc"
Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change. llvm-svn: 123910
2011-01-20 14:17:59 +01:00
//===----------------------------------------------------------------------===//
Remove no-longer-true comments. These are for the assembler, also. llvm-svn: 137375
2011-08-12 00:30:30 +02:00
// Move between coprocessor and ARM core register.
Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change. llvm-svn: 123910
2011-01-20 14:17:59 +01:00
//
Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2, MRRC, MRRc2. For disassembly only. llvm-svn: 95955
2010-02-12 02:44:23 +01:00
Fold ARM coprocessor intrinsics patterns into the instructions defs whenever it's possible. llvm-svn: 130764
2011-05-03 19:29:29 +02:00
class MovRCopro<string opc, bit direction, dag oops, dag iops,
list<dag> pattern>
Change MRC and MRC2 instructions to model the output register properly llvm-svn: 128085
2011-03-22 16:06:24 +01:00
: ABI<0b1110, oops, iops, NoItinerary, opc,
Fold ARM coprocessor intrinsics patterns into the instructions defs whenever it's possible. llvm-svn: 130764
2011-05-03 19:29:29 +02:00
"\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change. llvm-svn: 123910
2011-01-20 14:17:59 +01:00
let Inst{20} = direction;
Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2, MRRC, MRRc2. For disassembly only. llvm-svn: 95955
2010-02-12 02:44:23 +01:00
let Inst{4} = 1;
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
2011-01-13 22:46:02 +01:00
bits<4> Rt;
bits<4> cop;
bits<3> opc1;
bits<3> opc2;
bits<4> CRm;
bits<4> CRn;
Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change. llvm-svn: 123910
2011-01-20 14:17:59 +01:00
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
2011-01-13 22:46:02 +01:00
let Inst{15-12} = Rt;
let Inst{11-8} = cop;
let Inst{23-21} = opc1;
let Inst{7-5} = opc2;
let Inst{3-0} = CRm;
let Inst{19-16} = CRn;
[ARM] Assembler support for the ARMv8.2a dot product instructions Commit r310480 added the AArch64 ARMv8.2a dot product instructions; this adds the AArch32 instructions. Differential Revision: https://reviews.llvm.org/D36575 llvm-svn: 310701
2017-08-11 11:52:30 +02:00
let DecoderNamespace = "CoProc";
Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2, MRRC, MRRc2. For disassembly only. llvm-svn: 95955
2010-02-12 02:44:23 +01:00
}
Change MRC and MRC2 instructions to model the output register properly llvm-svn: 128085
2011-03-22 16:06:24 +01:00
def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
Fold ARM coprocessor intrinsics patterns into the instructions defs whenever it's possible. llvm-svn: 130764
2011-05-03 19:29:29 +02:00
(outs),
ARM MCR/MCR2 assembly parsing operand constraints. The immediate operands are restricted to 0-7. Enforce that when parsing assembly. llvm-svn: 135189
2011-07-14 23:19:17 +02:00
(ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
c_imm:$CRm, imm0_7:$opc2),
Fold ARM coprocessor intrinsics patterns into the instructions defs whenever it's possible. llvm-svn: 130764
2011-05-03 19:29:29 +02:00
[(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
Add an instruction deprecation feature to TableGen. The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. llvm-svn: 190598
2013-09-12 12:28:05 +02:00
imm:$CRm, imm:$opc2)]>,
ComplexDeprecationPredicate<"MCR">;
ARM optional operand on MRC/MCR assembly instructions. rdar://11058464 llvm-svn: 152883
2012-03-16 01:45:58 +01:00
def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
(MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
c_imm:$CRm, 0, pred:$p)>;
Change MRC and MRC2 instructions to model the output register properly llvm-svn: 128085
2011-03-22 16:06:24 +01:00
def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. llvm-svn: 181705
2013-05-13 16:10:04 +02:00
(outs GPRwithAPSR:$Rt),
ARM assembly parsing for MRC/MRC2/MRRC/MRRC2. Add range checking to the immediate operands. Update tests accordingly. llvm-svn: 135521
2011-07-19 22:35:35 +02:00
(ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
imm0_7:$opc2), []>;
ARM optional operand on MRC/MCR assembly instructions. rdar://11058464 llvm-svn: 152883
2012-03-16 01:45:58 +01:00
def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. llvm-svn: 181705
2013-05-13 16:10:04 +02:00
(MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
ARM optional operand on MRC/MCR assembly instructions. rdar://11058464 llvm-svn: 152883
2012-03-16 01:45:58 +01:00
c_imm:$CRm, 0, pred:$p)>;
Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change. llvm-svn: 123910
2011-01-20 14:17:59 +01:00
Add a few ARM coprocessor intrinsics. Testcases included llvm-svn: 130763
2011-05-03 19:29:22 +02:00
def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
(MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
Fold ARM coprocessor intrinsics patterns into the instructions defs whenever it's possible. llvm-svn: 130764
2011-05-03 19:29:29 +02:00
class MovRCopro2<string opc, bit direction, dag oops, dag iops,
list<dag> pattern>
Change MRC and MRC2 instructions to model the output register properly llvm-svn: 128085
2011-03-22 16:06:24 +01:00
: ABXI<0b1110, oops, iops, NoItinerary,
Fold ARM coprocessor intrinsics patterns into the instructions defs whenever it's possible. llvm-svn: 130764
2011-05-03 19:29:29 +02:00
!strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. llvm-svn: 181705
2013-05-13 16:10:04 +02:00
let Inst{31-24} = 0b11111110;
Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change. llvm-svn: 123910
2011-01-20 14:17:59 +01:00
let Inst{20} = direction;
Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2, MRRC, MRRc2. For disassembly only. llvm-svn: 95955
2010-02-12 02:44:23 +01:00
let Inst{4} = 1;
Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change. llvm-svn: 123910
2011-01-20 14:17:59 +01:00
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
2011-01-13 22:46:02 +01:00
bits<4> Rt;
bits<4> cop;
bits<3> opc1;
bits<3> opc2;
bits<4> CRm;
bits<4> CRn;
Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change. llvm-svn: 123910
2011-01-20 14:17:59 +01:00
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
2011-01-13 22:46:02 +01:00
let Inst{15-12} = Rt;
let Inst{11-8} = cop;
let Inst{23-21} = opc1;
let Inst{7-5} = opc2;
let Inst{3-0} = CRm;
let Inst{19-16} = CRn;
[ARM] Assembler support for the ARMv8.2a dot product instructions Commit r310480 added the AArch64 ARMv8.2a dot product instructions; this adds the AArch32 instructions. Differential Revision: https://reviews.llvm.org/D36575 llvm-svn: 310701
2017-08-11 11:52:30 +02:00
let DecoderNamespace = "CoProc";
Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2, MRRC, MRRc2. For disassembly only. llvm-svn: 95955
2010-02-12 02:44:23 +01:00
}
Change MRC and MRC2 instructions to model the output register properly llvm-svn: 128085
2011-03-22 16:06:24 +01:00
def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
Fold ARM coprocessor intrinsics patterns into the instructions defs whenever it's possible. llvm-svn: 130764
2011-05-03 19:29:29 +02:00
(outs),
ARM MCR/MCR2 assembly parsing operand constraints. The immediate operands are restricted to 0-7. Enforce that when parsing assembly. llvm-svn: 135189
2011-07-14 23:19:17 +02:00
(ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
c_imm:$CRm, imm0_7:$opc2),
Fold ARM coprocessor intrinsics patterns into the instructions defs whenever it's possible. llvm-svn: 130764
2011-05-03 19:29:29 +02:00
[(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings) llvm-svn: 194261
2013-11-08 17:16:30 +01:00
imm:$CRm, imm:$opc2)]>,
[ARM] Avoid using ARM instructions in Thumb mode The Requires class overrides the target requirements of an instruction, rather than adding to them, so all ARM instructions need to include the IsARM predicate when they have overwitten requirements. This caused the swp and swpb instructions to be allowed in thumb mode assembly, and the ARM encoding of CDP to be selected in codegen (which is different for conditional instructions). Differential Revision: https://reviews.llvm.org/D29283 llvm-svn: 293634
2017-01-31 15:35:01 +01:00
Requires<[IsARM,PreV8]>;
TableGen/ARM64: print aliases even if they have syntax variants. To get at least one use of the change (and some actual tests) in with its commit, I've enabled the AArch64 & ARM64 NEON mov aliases. llvm-svn: 208867
2014-05-15 13:16:32 +02:00
def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
ARM optional operand on MRC/MCR assembly instructions. rdar://11058464 llvm-svn: 152883
2012-03-16 01:45:58 +01:00
(MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
c_imm:$CRm, 0)>;
Change MRC and MRC2 instructions to model the output register properly llvm-svn: 128085
2011-03-22 16:06:24 +01:00
def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. llvm-svn: 181705
2013-05-13 16:10:04 +02:00
(outs GPRwithAPSR:$Rt),
ARM assembly parsing for MRC/MRC2/MRRC/MRRC2. Add range checking to the immediate operands. Update tests accordingly. llvm-svn: 135521
2011-07-19 22:35:35 +02:00
(ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings) llvm-svn: 194261
2013-11-08 17:16:30 +01:00
imm0_7:$opc2), []>,
[ARM] Avoid using ARM instructions in Thumb mode The Requires class overrides the target requirements of an instruction, rather than adding to them, so all ARM instructions need to include the IsARM predicate when they have overwitten requirements. This caused the swp and swpb instructions to be allowed in thumb mode assembly, and the ARM encoding of CDP to be selected in codegen (which is different for conditional instructions). Differential Revision: https://reviews.llvm.org/D29283 llvm-svn: 293634
2017-01-31 15:35:01 +01:00
Requires<[IsARM,PreV8]>;
TableGen/ARM64: print aliases even if they have syntax variants. To get at least one use of the change (and some actual tests) in with its commit, I've enabled the AArch64 & ARM64 NEON mov aliases. llvm-svn: 208867
2014-05-15 13:16:32 +02:00
def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. llvm-svn: 181705
2013-05-13 16:10:04 +02:00
(MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
ARM optional operand on MRC/MCR assembly instructions. rdar://11058464 llvm-svn: 152883
2012-03-16 01:45:58 +01:00
c_imm:$CRm, 0)>;
Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2, MRRC, MRRc2. For disassembly only. llvm-svn: 95955
2010-02-12 02:44:23 +01:00
Add a few ARM coprocessor intrinsics. Testcases included llvm-svn: 130763
2011-05-03 19:29:22 +02:00
def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
imm:$CRm, imm:$opc2),
(MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
Re-commit of r238201 with fix for building with shared libraries. llvm-svn: 238739
2015-06-01 14:02:47 +02:00
class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag>
pattern = []>
: ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
pattern> {
Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change. llvm-svn: 123910
2011-01-20 14:17:59 +01:00
let Inst{23-21} = 0b010;
let Inst{20} = direction;
Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2, MRRC, MRRc2. For disassembly only. llvm-svn: 95955
2010-02-12 02:44:23 +01:00
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
2011-01-13 22:46:02 +01:00
bits<4> Rt;
bits<4> Rt2;
bits<4> cop;
Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc llvm-svn: 123837
2011-01-19 17:56:52 +01:00
bits<4> opc1;
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
2011-01-13 22:46:02 +01:00
bits<4> CRm;
Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change. llvm-svn: 123910
2011-01-20 14:17:59 +01:00
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
2011-01-13 22:46:02 +01:00
let Inst{15-12} = Rt;
let Inst{19-16} = Rt2;
let Inst{11-8} = cop;
Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc llvm-svn: 123837
2011-01-19 17:56:52 +01:00
let Inst{7-4} = opc1;
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
2011-01-13 22:46:02 +01:00
let Inst{3-0} = CRm;
Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2, MRRC, MRRc2. For disassembly only. llvm-svn: 95955
2010-02-12 02:44:23 +01:00
}
Fold ARM coprocessor intrinsics patterns into the instructions defs whenever it's possible. llvm-svn: 130764
2011-05-03 19:29:29 +02:00
def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
Re-commit of r238201 with fix for building with shared libraries. llvm-svn: 238739
2015-06-01 14:02:47 +02:00
(outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt,
GPRnopc:$Rt2, c_imm:$CRm),
Tidy up. 80 columns, whitespace, et. al. llvm-svn: 155399
2012-04-24 00:04:10 +02:00
[(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
GPRnopc:$Rt2, imm:$CRm)]>;
Re-commit of r238201 with fix for building with shared libraries. llvm-svn: 238739
2015-06-01 14:02:47 +02:00
def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */,
(outs GPRnopc:$Rt, GPRnopc:$Rt2),
(ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>;
Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change. llvm-svn: 123910
2011-01-20 14:17:59 +01:00
[ARM] Add support for mrrc/mrrc2 intrinsics. Reapplying patch as it was reverted when it was first committed because of an assertion failure when the mrrc2 intrinsic was called in ARM mode. The failure was happening because the instruction was being built in ARMISelDAGToDAG.cpp and the tablegen description for mrrc2 instruction doesn't allow you to use a predicate. The ARM architecture manuals do say that mrrc2 in ARM mode can be predicated with AL in assembly but this has no effect on the encoding of the instruction as the top 4 bits will always be 1111 not 1110 which is the encoding for the condition AL. Differential Revision: http://reviews.llvm.org/D21408 llvm-svn: 272982
2016-06-17 02:52:41 +02:00
class MovRRCopro2<string opc, bit direction, dag oops, dag iops,
list<dag> pattern = []>
: ABXI<0b1100, oops, iops, NoItinerary,
[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings) llvm-svn: 194261
2013-11-08 17:16:30 +01:00
!strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
[ARM] Avoid using ARM instructions in Thumb mode The Requires class overrides the target requirements of an instruction, rather than adding to them, so all ARM instructions need to include the IsARM predicate when they have overwitten requirements. This caused the swp and swpb instructions to be allowed in thumb mode assembly, and the ARM encoding of CDP to be selected in codegen (which is different for conditional instructions). Differential Revision: https://reviews.llvm.org/D29283 llvm-svn: 293634
2017-01-31 15:35:01 +01:00
Requires<[IsARM,PreV8]> {
Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2, MRRC, MRRc2. For disassembly only. llvm-svn: 95955
2010-02-12 02:44:23 +01:00
let Inst{31-28} = 0b1111;
Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change. llvm-svn: 123910
2011-01-20 14:17:59 +01:00
let Inst{23-21} = 0b010;
let Inst{20} = direction;
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
2011-01-13 22:46:02 +01:00
bits<4> Rt;
bits<4> Rt2;
bits<4> cop;
Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc llvm-svn: 123837
2011-01-19 17:56:52 +01:00
bits<4> opc1;
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
2011-01-13 22:46:02 +01:00
bits<4> CRm;
Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change. llvm-svn: 123910
2011-01-20 14:17:59 +01:00
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
2011-01-13 22:46:02 +01:00
let Inst{15-12} = Rt;
let Inst{19-16} = Rt2;
let Inst{11-8} = cop;
Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc llvm-svn: 123837
2011-01-19 17:56:52 +01:00
let Inst{7-4} = opc1;
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
2011-01-13 22:46:02 +01:00
let Inst{3-0} = CRm;
Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. llvm-svn: 155001
2012-04-18 15:12:50 +02:00
[ARM] Add support for mrrc/mrrc2 intrinsics. Reapplying patch as it was reverted when it was first committed because of an assertion failure when the mrrc2 intrinsic was called in ARM mode. The failure was happening because the instruction was being built in ARMISelDAGToDAG.cpp and the tablegen description for mrrc2 instruction doesn't allow you to use a predicate. The ARM architecture manuals do say that mrrc2 in ARM mode can be predicated with AL in assembly but this has no effect on the encoding of the instruction as the top 4 bits will always be 1111 not 1110 which is the encoding for the condition AL. Differential Revision: http://reviews.llvm.org/D21408 llvm-svn: 272982
2016-06-17 02:52:41 +02:00
let DecoderMethod = "DecoderForMRRC2AndMCRR2";
Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2, MRRC, MRRc2. For disassembly only. llvm-svn: 95955
2010-02-12 02:44:23 +01:00
}
Fold ARM coprocessor intrinsics patterns into the instructions defs whenever it's possible. llvm-svn: 130764
2011-05-03 19:29:29 +02:00
def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
[ARM] Add support for mrrc/mrrc2 intrinsics. Reapplying patch as it was reverted when it was first committed because of an assertion failure when the mrrc2 intrinsic was called in ARM mode. The failure was happening because the instruction was being built in ARMISelDAGToDAG.cpp and the tablegen description for mrrc2 instruction doesn't allow you to use a predicate. The ARM architecture manuals do say that mrrc2 in ARM mode can be predicated with AL in assembly but this has no effect on the encoding of the instruction as the top 4 bits will always be 1111 not 1110 which is the encoding for the condition AL. Differential Revision: http://reviews.llvm.org/D21408 llvm-svn: 272982
2016-06-17 02:52:41 +02:00
(outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt,
GPRnopc:$Rt2, c_imm:$CRm),
Tidy up. 80 columns, whitespace, et. al. llvm-svn: 155399
2012-04-24 00:04:10 +02:00
[(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
GPRnopc:$Rt2, imm:$CRm)]>;
[ARM] Add support for mrrc/mrrc2 intrinsics. Reapplying patch as it was reverted when it was first committed because of an assertion failure when the mrrc2 intrinsic was called in ARM mode. The failure was happening because the instruction was being built in ARMISelDAGToDAG.cpp and the tablegen description for mrrc2 instruction doesn't allow you to use a predicate. The ARM architecture manuals do say that mrrc2 in ARM mode can be predicated with AL in assembly but this has no effect on the encoding of the instruction as the top 4 bits will always be 1111 not 1110 which is the encoding for the condition AL. Differential Revision: http://reviews.llvm.org/D21408 llvm-svn: 272982
2016-06-17 02:52:41 +02:00
def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */,
(outs GPRnopc:$Rt, GPRnopc:$Rt2),
(ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>;
Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change. llvm-svn: 123910
2011-01-20 14:17:59 +01:00
Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only. llvm-svn: 95999
2010-02-12 19:55:33 +01:00
//===----------------------------------------------------------------------===//
ARM assembly parsing of MRS instruction. Teach the parser to recognize the APSR and SPSR system register names. Add and update tests accordingly. llvm-svn: 135527
2011-07-19 23:59:29 +02:00
// Move between special register and ARM core register
Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only. llvm-svn: 95999
2010-02-12 19:55:33 +01:00
//
Add assembly parsing support for "msr" and also fix its encoding. Also add testcases for the disassembler to make sure it still works for "msr". llvm-svn: 125948
2011-02-18 20:45:59 +01:00
// Move to ARM core register from Special Register
Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors. llvm-svn: 155002
2012-04-18 16:09:07 +02:00
def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
ARM assembly parsing of MRS instruction. Teach the parser to recognize the APSR and SPSR system register names. Add and update tests accordingly. llvm-svn: 135527
2011-07-19 23:59:29 +02:00
"mrs", "\t$Rd, apsr", []> {
Fix MRS encoding for arm and thumb. llvm-svn: 123778
2011-01-18 22:31:35 +01:00
bits<4> Rd;
let Inst{23-16} = 0b00001111;
Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors. llvm-svn: 155002
2012-04-18 16:09:07 +02:00
let Unpredictable{19-17} = 0b111;
Fix MRS encoding for arm and thumb. llvm-svn: 123778
2011-01-18 22:31:35 +01:00
let Inst{15-12} = Rd;
Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors. llvm-svn: 155002
2012-04-18 16:09:07 +02:00
let Inst{11-0} = 0b000000000000;
let Unpredictable{11-0} = 0b110100001111;
Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only. llvm-svn: 95999
2010-02-12 19:55:33 +01:00
}
ARM target does not use printAliasInstr machinery which forces having special checks in ArmInstPrinter::printInstruction. This patch addresses this issue. Not all special checks could be removed: either they involve elaborated conditions under which the alias is emitted (e.g. ldm/stm on sp may be pop/push but only if the number of registers is >= 2) or the number of registers is multivalued (like happens again with ldm/stm) and they do not match the InstAlias pattern which assumes single-valued operands in the pattern. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20237 llvm-svn: 271667
2016-06-03 15:19:43 +02:00
def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p), 0>,
Tidy up. 80 columns, whitespace, et. al. llvm-svn: 155399
2012-04-24 00:04:10 +02:00
Requires<[IsARM]>;
ARM assembly parsing of MRS instruction. Teach the parser to recognize the APSR and SPSR system register names. Add and update tests accordingly. llvm-svn: 135527
2011-07-19 23:59:29 +02:00
Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors. llvm-svn: 155002
2012-04-18 16:09:07 +02:00
// The MRSsys instruction is the MRS instruction from the ARM ARM,
// section B9.3.9, with the R bit set to 1.
def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
ARM assembly parsing of MRS instruction. Teach the parser to recognize the APSR and SPSR system register names. Add and update tests accordingly. llvm-svn: 135527
2011-07-19 23:59:29 +02:00
"mrs", "\t$Rd, spsr", []> {
Fix MRS encoding for arm and thumb. llvm-svn: 123778
2011-01-18 22:31:35 +01:00
bits<4> Rd;
let Inst{23-16} = 0b01001111;
Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors. llvm-svn: 155002
2012-04-18 16:09:07 +02:00
let Unpredictable{19-16} = 0b1111;
Fix MRS encoding for arm and thumb. llvm-svn: 123778
2011-01-18 22:31:35 +01:00
let Inst{15-12} = Rd;
Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors. llvm-svn: 155002
2012-04-18 16:09:07 +02:00
let Inst{11-0} = 0b000000000000;
let Unpredictable{11-0} = 0b110100001111;
Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only. llvm-svn: 95999
2010-02-12 19:55:33 +01:00
}
ARM: implement MRS/MSR (banked reg) system instructions. These are system-only instructions for CPUs with virtualization extensions, allowing a hypervisor easy access to all of the various different AArch32 registers. rdar://problem/17861345 llvm-svn: 215700
2014-08-15 12:47:12 +02:00
// However, the MRS (banked register) system instruction (ARMv7VE) *does* have a
// separate encoding (distinguished by bit 5.
def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked),
NoItinerary, "mrs", "\t$Rd, $banked", []>,
Requires<[IsARM, HasVirtualization]> {
bits<6> banked;
bits<4> Rd;
let Inst{23} = 0;
let Inst{22} = banked{5}; // R bit
Fix wrong encoding of MRSBanked. Patch by Matthew Wahab. Change-Id: Ia2a001ca2760028ea360fe77b56f203a219eefbc llvm-svn: 222920
2014-11-28 16:01:06 +01:00
let Inst{21-20} = 0b00;
ARM: implement MRS/MSR (banked reg) system instructions. These are system-only instructions for CPUs with virtualization extensions, allowing a hypervisor easy access to all of the various different AArch32 registers. rdar://problem/17861345 llvm-svn: 215700
2014-08-15 12:47:12 +02:00
let Inst{19-16} = banked{3-0};
let Inst{15-12} = Rd;
let Inst{11-9} = 0b001;
let Inst{8} = banked{4};
let Inst{7-0} = 0b00000000;
}
Add assembly parsing support for "msr" and also fix its encoding. Also add testcases for the disassembler to make sure it still works for "msr". llvm-svn: 125948
2011-02-18 20:45:59 +01:00
// Move from ARM core register to Special Register
//
ARM: implement MRS/MSR (banked reg) system instructions. These are system-only instructions for CPUs with virtualization extensions, allowing a hypervisor easy access to all of the various different AArch32 registers. rdar://problem/17861345 llvm-svn: 215700
2014-08-15 12:47:12 +02:00
// No need to have both system and application versions of MSR (immediate) or
// MSR (register), the encodings are the same and the assembly parser has no way
// to distinguish between them. The mask operand contains the special register
// (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be
// accessed in the special register.
[ARM] MSR instructions implicitly set CPSR The MSR instructions can write to the CPSR, but we did not model this fact, so we could emit them in the middle of IT blocks, changing the condition flags for later instructions in the block. The tests use two calls to llvm.write_register.i32 because it is valid to use these instructions at the end of an IT block, which if conversion does do in some cases. With two calls, the first clobbers the flags, so a branch has to be used to make the second one conditional. Differential Revision: http://reviews.llvm.org/D21139 llvm-svn: 272154
2016-06-08 17:26:34 +02:00
let Defs = [CPSR] in
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs. llvm-svn: 142626
2011-10-21 00:23:58 +02:00
def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
"msr", "\t$mask, $Rn", []> {
Add assembly parsing support for "msr" and also fix its encoding. Also add testcases for the disassembler to make sure it still works for "msr". llvm-svn: 125948
2011-02-18 20:45:59 +01:00
bits<5> mask;
bits<4> Rn;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
Add assembly parsing support for "msr" and also fix its encoding. Also add testcases for the disassembler to make sure it still works for "msr". llvm-svn: 125948
2011-02-18 20:45:59 +01:00
let Inst{23} = 0;
let Inst{22} = mask{4}; // R bit
let Inst{21-20} = 0b10;
let Inst{19-16} = mask{3-0};
let Inst{15-12} = 0b1111;
let Inst{11-4} = 0b00000000;
let Inst{3-0} = Rn;
Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only. llvm-svn: 95999
2010-02-12 19:55:33 +01:00
}
[ARM] MSR instructions implicitly set CPSR The MSR instructions can write to the CPSR, but we did not model this fact, so we could emit them in the middle of IT blocks, changing the condition flags for later instructions in the block. The tests use two calls to llvm.write_register.i32 because it is valid to use these instructions at the end of an IT block, which if conversion does do in some cases. With two calls, the first clobbers the flags, so a branch has to be used to make the second one conditional. Differential Revision: http://reviews.llvm.org/D21139 llvm-svn: 272154
2016-06-08 17:26:34 +02:00
let Defs = [CPSR] in
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary,
"msr", "\t$mask, $imm", []> {
Add assembly parsing support for "msr" and also fix its encoding. Also add testcases for the disassembler to make sure it still works for "msr". llvm-svn: 125948
2011-02-18 20:45:59 +01:00
bits<5> mask;
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
bits<12> imm;
Added for disassembly the following instructions: o Store Return State (SRSW, SRS) o Load/Store Coprocessor (LDC/STC and friends) o MSR (immediate) llvm-svn: 96380
2010-02-16 21:04:27 +01:00
Add assembly parsing support for "msr" and also fix its encoding. Also add testcases for the disassembler to make sure it still works for "msr". llvm-svn: 125948
2011-02-18 20:45:59 +01:00
let Inst{23} = 0;
let Inst{22} = mask{4}; // R bit
let Inst{21-20} = 0b10;
let Inst{19-16} = mask{3-0};
let Inst{15-12} = 0b1111;
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
let Inst{11-0} = imm;
Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only. llvm-svn: 95999
2010-02-12 19:55:33 +01:00
}
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
ARM: implement MRS/MSR (banked reg) system instructions. These are system-only instructions for CPUs with virtualization extensions, allowing a hypervisor easy access to all of the various different AArch32 registers. rdar://problem/17861345 llvm-svn: 215700
2014-08-15 12:47:12 +02:00
// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
// separate encoding (distinguished by bit 5.
def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn),
NoItinerary, "msr", "\t$banked, $Rn", []>,
Requires<[IsARM, HasVirtualization]> {
bits<6> banked;
bits<4> Rn;
let Inst{23} = 0;
let Inst{22} = banked{5}; // R bit
let Inst{21-20} = 0b10;
let Inst{19-16} = banked{3-0};
let Inst{15-12} = 0b1111;
let Inst{11-9} = 0b001;
let Inst{8} = banked{4};
let Inst{7-4} = 0b0000;
let Inst{3-0} = Rn;
}
ARM: add VLA extension for WoA Itanium ABI The armv7-windows-itanium environment is nearly identical to the MSVC ABI. It has a few divergences, mostly revolving around the use of the Itanium ABI for C++. VLA support is one of the extensions that are amongst the set of the extensions. This adds support for proper VLA emission for this environment. This is somewhat similar to the handling for __chkstk emission on X86 and the large stack frame emission for ARM. The invocation style for chkstk is still controlled via the -mcmodel flag to clang. Make an explicit note that this is an extension. llvm-svn: 210489
2014-06-09 22:18:42 +02:00
// Dynamic stack allocation yields a _chkstk for Windows targets. These calls
// are needed to probe the stack when allocating more than
// 4k bytes in one go. Touching the stack at 4K increments is necessary to
// ensure that the guard pages used by the OS virtual memory manager are
// allocated in correct sequence.
// The main point of having separate instruction are extra unmodelled effects
// (compared to ordinary calls) like stack pointer change.
def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone,
[SDNPHasChain, SDNPSideEffect]>;
let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in
def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>;
ARM: address WoA division limitation We now emit the compiler generated divide by zero check that was needed for the MSVC routines. We construct a psuedo-instruction for the DBZ check as the operation requires splitting up the BB. For the 64-bit operations, we need to custom expand the node as we need to insert the DBZ check and then emit the libcall to the appropriate name. Because this is target specific, it seemed better to reproduce the expansion operation from the target-agnostic type legalization rather than sink this there to avoid the duplication. The division library calls now match MSVC semantically. llvm-svn: 248561
2015-09-25 07:15:46 +02:00
def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK,
[SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
let usesCustomInserter = 1, Defs = [CPSR] in
ARM: restrict register class for WIN__DBZCHK WIN__DBZCHK will insert a CBZ instruction into the stream. This instruction reserves 3 bits for the condition register (rn). As such, we must ensure that we restrict the register to a low register. Use the tGPR class instead of GPR to ensure that this is properly constrained. In debug builds, we would attempt to use lr as a condition register which would silently get truncated with no hint that the register selection was incorrect. llvm-svn: 267080
2016-04-22 01:53:19 +02:00
def WIN__DBZCHK : PseudoInst<(outs), (ins tGPR:$divisor), NoItinerary,
[(win__dbzchk tGPR:$divisor)]>;
ARM: address WoA division limitation We now emit the compiler generated divide by zero check that was needed for the MSVC routines. We construct a psuedo-instruction for the DBZ check as the operation requires splitting up the BB. For the 64-bit operations, we need to custom expand the node as we need to insert the DBZ check and then emit the libcall to the appropriate name. Because this is target specific, it seemed better to reproduce the expansion operation from the target-agnostic type legalization rather than sink this there to avoid the duplication. The division library calls now match MSVC semantically. llvm-svn: 248561
2015-09-25 07:15:46 +02:00
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
//===----------------------------------------------------------------------===//
// TLS Instructions
//
// __aeabi_read_tp preserves the registers r1-r3.
Clean whitespace. llvm-svn: 127900
2011-03-18 20:47:14 +01:00
// This is a pseudo inst so that we can get the encoding right,
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
// complete with fixup for the aeabi_read_tp function.
ARM: Fix TPsoft for Thumb mode Reviewed at http://reviews.llvm.org/D4230 llvm-svn: 211601
2014-06-24 17:45:59 +02:00
// TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
// is defined in "ARMInstrThumb.td".
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
let isCall = 1,
Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
ARM: Fix TPsoft for Thumb mode Reviewed at http://reviews.llvm.org/D4230 llvm-svn: 211601
2014-06-24 17:45:59 +02:00
def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
[ARM] Add the option to directly access TLS pointer This patch enables choice for accessing thread local storage pointer (like '-mtp' in gcc). Differential Revision: https://reviews.llvm.org/D34408 llvm-svn: 309381
2017-07-28 14:54:57 +02:00
[(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>,
Requires<[IsARM, IsReadTPSoft]>;
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
}
[ARM] Add the option to directly access TLS pointer This patch enables choice for accessing thread local storage pointer (like '-mtp' in gcc). Differential Revision: https://reviews.llvm.org/D34408 llvm-svn: 309381
2017-07-28 14:54:57 +02:00
// Reading thread pointer from coprocessor register
def : ARMPat<(ARMthread_pointer), (MRC 15, 0, 13, 0, 3)>,
Requires<[IsARM, IsReadTPHard]>;
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
//===----------------------------------------------------------------------===//
// SJLJ Exception handling intrinsics
// eh_sjlj_setjmp() is an instruction sequence to store the return
// address and save #0 in R0 for the non-longjmp case.
// Since by its nature we may be coming from some other function to get
// here, and we're using the stack frame for the containing function to
// save/restore registers, we can't keep anything live in regs across
// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
Fix a ton of comment typos found by codespell. Patch by Luis Felipe Strano Moraes! llvm-svn: 129558
2011-04-15 07:18:47 +02:00
// when we get here from a longjmp(). We force everything out of registers
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
// except for our own input by listing the relevant registers in Defs. By
// doing so, we also cause the prologue/epilogue code to actively preserve
// all of the callee-saved resgisters, which is exactly what we want.
// A constant value is passed in $val, and we use the location as a scratch.
//
// These are pseudo-instructions and are lowered to individual MC-insts, so
// no encoding information is necessary.
let Defs =
Fix for setjmp/longjmp exception handling on ARM. setjmp clobbers CPSR. rdar://problem/9556069 llvm-svn: 132699
2011-06-07 02:08:49 +02:00
[ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
Use RegisterTuples to generate pseudo-registers. The QQ and QQQQ registers are not 'real', they are pseudo-registers used to model some vld and vst instructions. This makes the call clobber lists longer, but I intend to get rid of those soon. llvm-svn: 148151
2012-01-13 23:55:42 +01:00
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
NoItinerary,
[(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
Requires<[IsARM, HasVFP2]>;
}
let Defs =
Fix for setjmp/longjmp exception handling on ARM. setjmp clobbers CPSR. rdar://problem/9556069 llvm-svn: 132699
2011-06-07 02:08:49 +02:00
[ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
Add missing usesCustomInserter flag on Int_eh_sjlj_setjmp_nofp. Noticed by inspection; I don't have a testcase for this. llvm-svn: 147188
2011-12-22 23:12:44 +01:00
hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
NoItinerary,
[(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
Requires<[IsARM, NoVFP]>;
}
ARM target code clean up. Check for iOS, not Darwin where it makes sense. llvm-svn: 146981
2011-12-20 19:26:50 +01:00
// FIXME: Non-IOS version(s)
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
Defs = [ R7, LR, SP ] in {
def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
NoItinerary,
[(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
ARM: convert isTargetIOS checks to isTargetDarwin. The distinction is mostly useful in the front-end. By the time we get here, there are very few situations where we actually want different behaviour for Darwin and IOS (in fact Darwin mostly just exists in a few tests). So this should reduce any surprising weirdness for anyone using it. No functional change on anything anyone actually cares about. llvm-svn: 224035
2014-12-11 19:49:37 +01:00
Requires<[IsARM]>;
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
}
Fix __builtin_setjmp in combination with sjlj exception handling. llvm.eh.sjlj.setjmp was used as part of the SjLj exception handling style but is also used in clang to implement __builtin_setjmp. The ARM backend needs to output additional dispatch tables for the SjLj exception handling style, these tables however can't be emitted if llvm.eh.sjlj.setjmp is simply used for __builtin_setjmp and no actual landing pad blocks exist. To solve this issue a new llvm.eh.sjlj.setup_dispatch intrinsic is introduced which is used instead of llvm.eh.sjlj.setjmp in the SjLj exception handling lowering, so we can differentiate between the case where we actually need to setup a dispatch table and the case where we just need the __builtin_setjmp semantic. Differential Revision: http://reviews.llvm.org/D9313 llvm-svn: 242481
2015-07-17 00:34:16 +02:00
let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in
def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary,
[(ARMeh_sjlj_setup_dispatch)]>;
Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering all registers. Previously, the register we being marked as implicitly defined, but not killed. In some cases this would cause the register scavenger to spill a dead register. Also, use an empty register mask to simplify the logic and to reduce the memory footprint. rdar://12592448 llvm-svn: 167499
2012-11-07 00:05:24 +01:00
// eh.sjlj.dispatchsetup pseudo-instruction.
// This pseudo is used for both ARM and Thumb. Any differences are handled when
// the pseudo is expanded (which happens before any passes that need the
// instruction size).
let isBarrier = 1 in
Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138> My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo instruction, but on Thumb1 some of those registers cannot be used. This caused massive failures on the testsuite when compiling for Thumb1. While fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp" variant, and I realized that dispatchsetup needs the same thing, so I have added that as well. llvm-svn: 147204
2011-12-23 00:39:48 +01:00
def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
2011-07-08 19:40:42 +02:00
// ARMv4 indirect branch using (MOVr PC, dst)
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
2011-07-14 01:22:26 +02:00
4, IIC_Br, [(brind GPR:$dst)],
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
2011-07-08 19:40:42 +02:00
(MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
ARM sched model: Add branch instructions Reapply 183263. llvm-svn: 183428
2013-06-06 20:21:13 +02:00
Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
Fix ARMv4 support ARMv4 doesn't support the "BX" instruction, which has been introduced with ARMv4t. Adjust the call lowering and tail call implementation accordingly. Further changes are necessary to ensure that presence of the v4t feature is correctly set. Most importantly, the "generic" CPU for thumb-* triples should include ARMv4t, since thumb mode without thumb support would naturally be pointless. Add a couple of asserts to ensure thumb instructions are not emitted without CPU support. Differential Revision: https://reviews.llvm.org/D37030 llvm-svn: 311921
2017-08-28 22:20:47 +02:00
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in
def TAILJMPr4 : ARMPseudoExpand<(outs), (ins GPR:$dst),
4, IIC_Br, [],
(MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
Use TableGen'erated pseudo lowering for ARM. Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
2011-07-08 19:40:42 +02:00
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
// Large immediate handling.
[ARM] Cleanup so_imm* tblgen defintions No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
2015-01-06 16:55:09 +01:00
// 32-bit immediate using two piece mod_imms or movw + movt.
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
// This is a single pseudo instruction, the benefit is that it can be remat'd
// as a single unit instead of having to handle reg inputs.
// FIXME: Remove this when we can do generalized remat.
let isReMaterializable = 1, isMoveImm = 1 in
def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
[(set GPR:$dst, (arm_i32imm:$src))]>,
Requires<[IsARM]>;
ARM: add pseudo-instructions for lit-pool global materialisation These are used by MachO only at the moment, and (much like the existing MOVW/MOVT set) work around the fact that the labels used in the actual instructions often contain PC-dependent components, which means that repeatedly materialising the same global can't be CSEed. With small modifications, it could be adapted to how ELF finds the address of _GLOBAL_OFFSET_TABLE_, which would give similar benefits in PIC mode there. llvm-svn: 196090
2013-12-02 11:35:41 +01:00
def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
[(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
Requires<[IsARM, DontUseMovt]>;
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
// Pseudo instruction that combines movw + movt + add pc (if PIC).
// It also makes it possible to rematerialize the instructions.
// FIXME: Remove this when we can do generalized remat and when machine licm
// can properly the instructions.
let isReMaterializable = 1 in {
def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
IIC_iMOVix2addpc,
[(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
[arm] Fix Unnecessary reloads from GOT. Summary: This fixes PR35221. Use pseudo-instructions to let MachineCSE hoist global address computation. Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39871 llvm-svn: 318081
2017-11-13 21:45:38 +01:00
Requires<[IsARM, UseMovtInPic]>;
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
ARM: add pseudo-instructions for lit-pool global materialisation These are used by MachO only at the moment, and (much like the existing MOVW/MOVT set) work around the fact that the labels used in the actual instructions often contain PC-dependent components, which means that repeatedly materialising the same global can't be CSEed. With small modifications, it could be adapted to how ELF finds the address of _GLOBAL_OFFSET_TABLE_, which would give similar benefits in PIC mode there. llvm-svn: 196090
2013-12-02 11:35:41 +01:00
def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
IIC_iLoadiALU,
[(set GPR:$dst,
(ARMWrapperPIC tglobaladdr:$addr))]>,
[arm] Fix Unnecessary reloads from GOT. Summary: This fixes PR35221. Use pseudo-instructions to let MachineCSE hoist global address computation. Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39871 llvm-svn: 318081
2017-11-13 21:45:38 +01:00
Requires<[IsARM, DontUseMovtInPic]>;
ARM: add pseudo-instructions for lit-pool global materialisation These are used by MachO only at the moment, and (much like the existing MOVW/MOVT set) work around the fact that the labels used in the actual instructions often contain PC-dependent components, which means that repeatedly materialising the same global can't be CSEed. With small modifications, it could be adapted to how ELF finds the address of _GLOBAL_OFFSET_TABLE_, which would give similar benefits in PIC mode there. llvm-svn: 196090
2013-12-02 11:35:41 +01:00
ARM: correctly expand LDR-lit based globals. Quite a major error here: the expansions for the Pseudos with and without folded load were mixed up. Fortunately it only affects ARM-mode, when not using movw/movt, on Darwin. I'm guessing no-one actually uses that combination. llvm-svn: 223986
2014-12-11 00:40:50 +01:00
let AddedComplexity = 10 in
ARM: add pseudo-instructions for lit-pool global materialisation These are used by MachO only at the moment, and (much like the existing MOVW/MOVT set) work around the fact that the labels used in the actual instructions often contain PC-dependent components, which means that repeatedly materialising the same global can't be CSEed. With small modifications, it could be adapted to how ELF finds the address of _GLOBAL_OFFSET_TABLE_, which would give similar benefits in PIC mode there. llvm-svn: 196090
2013-12-02 11:35:41 +01:00
def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
NoItinerary,
[(set GPR:$dst,
(load (ARMWrapperPIC tglobaladdr:$addr)))]>,
[arm] Fix Unnecessary reloads from GOT. Summary: This fixes PR35221. Use pseudo-instructions to let MachineCSE hoist global address computation. Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39871 llvm-svn: 318081
2017-11-13 21:45:38 +01:00
Requires<[IsARM, DontUseMovtInPic]>;
ARM: add pseudo-instructions for lit-pool global materialisation These are used by MachO only at the moment, and (much like the existing MOVW/MOVT set) work around the fact that the labels used in the actual instructions often contain PC-dependent components, which means that repeatedly materialising the same global can't be CSEed. With small modifications, it could be adapted to how ELF finds the address of _GLOBAL_OFFSET_TABLE_, which would give similar benefits in PIC mode there. llvm-svn: 196090
2013-12-02 11:35:41 +01:00
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
let AddedComplexity = 10 in
def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
IIC_iMOVix2ld,
[(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
[arm] Fix Unnecessary reloads from GOT. Summary: This fixes PR35221. Use pseudo-instructions to let MachineCSE hoist global address computation. Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39871 llvm-svn: 318081
2017-11-13 21:45:38 +01:00
Requires<[IsARM, UseMovtInPic]>;
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
} // isReMaterializable
ARM: support TLS accesses on Darwin platforms Darwin TLS accesses most closely resemble ELF's general-dynamic situation, since they have to be able to handle all possible situations. The descriptors and so on are obviously slightly different though. llvm-svn: 257039
2016-01-07 10:03:03 +01:00
// The many different faces of TLS access.
def : ARMPat<(ARMWrapper tglobaltlsaddr :$dst),
(MOVi32imm tglobaltlsaddr :$dst)>,
Requires<[IsARM, UseMovt]>;
def : Pat<(ARMWrapper tglobaltlsaddr:$src),
(LDRLIT_ga_abs tglobaltlsaddr:$src)>,
Requires<[IsARM, DontUseMovt]>;
def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr),
[arm] Fix Unnecessary reloads from GOT. Summary: This fixes PR35221. Use pseudo-instructions to let MachineCSE hoist global address computation. Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39871 llvm-svn: 318081
2017-11-13 21:45:38 +01:00
(MOV_ga_pcrel tglobaltlsaddr:$addr)>, Requires<[IsARM, UseMovtInPic]>;
ARM: support TLS accesses on Darwin platforms Darwin TLS accesses most closely resemble ELF's general-dynamic situation, since they have to be able to handle all possible situations. The descriptors and so on are obviously slightly different though. llvm-svn: 257039
2016-01-07 10:03:03 +01:00
def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr),
(LDRLIT_ga_pcrel tglobaltlsaddr:$addr)>,
[arm] Fix Unnecessary reloads from GOT. Summary: This fixes PR35221. Use pseudo-instructions to let MachineCSE hoist global address computation. Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39871 llvm-svn: 318081
2017-11-13 21:45:38 +01:00
Requires<[IsARM, DontUseMovtInPic]>;
ARM: support TLS accesses on Darwin platforms Darwin TLS accesses most closely resemble ELF's general-dynamic situation, since they have to be able to handle all possible situations. The descriptors and so on are obviously slightly different though. llvm-svn: 257039
2016-01-07 10:03:03 +01:00
let AddedComplexity = 10 in
def : Pat<(load (ARMWrapperPIC tglobaltlsaddr:$addr)),
(MOV_ga_pcrel_ldr tglobaltlsaddr:$addr)>,
[arm] Fix Unnecessary reloads from GOT. Summary: This fixes PR35221. Use pseudo-instructions to let MachineCSE hoist global address computation. Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39871 llvm-svn: 318081
2017-11-13 21:45:38 +01:00
Requires<[IsARM, UseMovtInPic]>;
ARM: support TLS accesses on Darwin platforms Darwin TLS accesses most closely resemble ELF's general-dynamic situation, since they have to be able to handle all possible situations. The descriptors and so on are obviously slightly different though. llvm-svn: 257039
2016-01-07 10:03:03 +01:00
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
// ConstantPool, GlobalAddress, and JumpTable
def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
Requires<[IsARM, UseMovt]>;
ARM: support TLS for WoA Add support for TLS access for Windows on ARM. This generates a similar access to MSVC for ARM. The changes to the tablegen data is needed to support loading an external symbol global that is not for a call. The adjustments to the DAG to DAG transforms are needed to preserve the 32-bit move. llvm-svn: 259676
2016-02-03 19:21:59 +01:00
def : ARMPat<(ARMWrapper texternalsym :$dst), (MOVi32imm texternalsym :$dst)>,
Requires<[IsARM, UseMovt]>;
ARM: remove custom jump table UID We were creating and propagating two separate indices for each jump table (from back in the mists of time). However, the generic index used by other backends is sufficient to emit a unique symbol so this was unneeded. llvm-svn: 237294
2015-05-13 22:28:38 +02:00
def : ARMPat<(ARMWrapperJT tjumptable:$dst),
(LEApcrelJT tjumptable:$dst)>;
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
// TODO: add,sub,and, 3-instr forms?
Eliminate iOS-specific tail call instructions. After register masks were introdruced to represent the call clobbers, it is no longer necessary to have duplicate instruction for iOS. llvm-svn: 154209
2012-04-06 23:17:42 +02:00
// Tail calls. These patterns also apply to Thumb mode.
def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
// Direct calls
ARMPat is equivalent to Requires<[IsARM]>. llvm-svn: 154210
2012-04-06 23:21:59 +02:00
def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call. llvm-svn: 151645
2012-02-28 19:51:51 +01:00
def : ARMPat<(ARMcall_nolink texternalsym:$func),
ARMPat is equivalent to Requires<[IsARM]>. llvm-svn: 154210
2012-04-06 23:21:59 +02:00
(BMOVPCB_CALL texternalsym:$func)>;
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
// zextload i1 -> zextload i8
def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
// extload -> zextload
def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
// smul* and smla*
def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
[ARM] Add missing patterns for DSP muls Using a PatLeaf for sext_16_node allowed matching smulbb and smlabb instructions once the operands had been sign extended. But we also need to use sext_inreg operands along with sext_16_node to catch a few more cases that enable use to remove the unnecessary sxth. Differential Revision: https://reviews.llvm.org/D55992 llvm-svn: 350613
2019-01-08 11:12:36 +01:00
(SMULBB GPR:$a, GPR:$b)>;
def : ARMV5TEPat<(mul sext_16_node:$a, (sext_bottom_16 GPR:$b)),
(SMULBB GPR:$a, GPR:$b)>;
def : ARMV5TEPat<(mul sext_16_node:$a, (sext_top_16 GPR:$b)),
(SMULBT GPR:$a, GPR:$b)>;
def : ARMV5TEPat<(mul (sext_top_16 GPR:$a), sext_16_node:$b),
(SMULTB GPR:$a, GPR:$b)>;
def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, sext_16_node:$b)),
(SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_bottom_16 GPR:$b))),
(SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_top_16 GPR:$b))),
(SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
def : ARMV5MOPat<(add GPR:$acc, (mul (sext_top_16 GPR:$a), sext_16_node:$b)),
(SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
[ARM] ACLE Chapter 9 intrinsics Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
2017-05-04 09:31:28 +02:00
def : ARMV5TEPat<(int_arm_smulbb GPR:$a, GPR:$b),
(SMULBB GPR:$a, GPR:$b)>;
def : ARMV5TEPat<(int_arm_smulbt GPR:$a, GPR:$b),
(SMULBT GPR:$a, GPR:$b)>;
def : ARMV5TEPat<(int_arm_smultb GPR:$a, GPR:$b),
(SMULTB GPR:$a, GPR:$b)>;
def : ARMV5TEPat<(int_arm_smultt GPR:$a, GPR:$b),
(SMULTT GPR:$a, GPR:$b)>;
def : ARMV5TEPat<(int_arm_smulwb GPR:$a, GPR:$b),
(SMULWB GPR:$a, GPR:$b)>;
def : ARMV5TEPat<(int_arm_smulwt GPR:$a, GPR:$b),
(SMULWT GPR:$a, GPR:$b)>;
def : ARMV5TEPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc),
(SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
def : ARMV5TEPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc),
(SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
def : ARMV5TEPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc),
(SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
def : ARMV5TEPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc),
(SMLATT GPR:$a, GPR:$b, GPR:$acc)>;
def : ARMV5TEPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc),
(SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
def : ARMV5TEPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc),
(SMLAWT GPR:$a, GPR:$b, GPR:$acc)>;
DMB can just be a pat referencing MCR. llvm-svn: 127423
2011-03-10 20:27:17 +01:00
// Pre-v7 uses MCR for synchronization barriers.
def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
Requires<[IsARM, HasV6]>;
ARM extend instructions simplification. Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. llvm-svn: 136225
2011-07-27 18:47:19 +02:00
// SXT/UXT with no rotate
ARM cleanup of remaining extend instructions. Refactor the rest of the extend instructions to not artificially distinguish between a rotate of zero and a rotate of any other value. Replace the by-zero versions with Pat<>'s for ISel. llvm-svn: 136226
2011-07-27 19:48:13 +02:00
let AddedComplexity = 16 in {
ARM extend instructions simplification. Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. llvm-svn: 136225
2011-07-27 18:47:19 +02:00
def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
ARM cleanup of remaining extend instructions. Refactor the rest of the extend instructions to not artificially distinguish between a rotate of zero and a rotate of any other value. Replace the by-zero versions with Pat<>'s for ISel. llvm-svn: 136226
2011-07-27 19:48:13 +02:00
def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
(UXTAB GPR:$Rn, GPR:$Rm, 0)>;
def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
(UXTAH GPR:$Rn, GPR:$Rm, 0)>;
}
ARM extend instructions simplification. Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. llvm-svn: 136225
2011-07-27 18:47:19 +02:00
def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
DMB can just be a pat referencing MCR. llvm-svn: 127423
2011-03-10 20:27:17 +01:00
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
(SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
(SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
ARM cleanup of remaining extend instructions. Refactor the rest of the extend instructions to not artificially distinguish between a rotate of zero and a rotate of any other value. Replace the by-zero versions with Pat<>'s for ISel. llvm-svn: 136226
2011-07-27 19:48:13 +02:00
Atomic load/store on ARM/Thumb. I don't really like the patterns, but I'm having trouble coming up with a better way to handle them. I plan on making other targets use the same legalization ARM-without-memory-barriers is using... it's not especially efficient, but if anyone cares, it's not that hard to fix for a given target if there's some better lowering. llvm-svn: 138621
2011-08-26 04:59:24 +02:00
// Atomic load/store patterns
def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM." This wasn't the right way to enforce ordering of atomics. We are already setting the isVolatile bit on memory operands of atomic operations which is good enough to enforce the correct ordering. llvm-svn: 162732
2012-08-28 05:11:27 +02:00
(LDRBrs ldst_so_reg:$src)>;
Atomic load/store on ARM/Thumb. I don't really like the patterns, but I'm having trouble coming up with a better way to handle them. I plan on making other targets use the same legalization ARM-without-memory-barriers is using... it's not especially efficient, but if anyone cares, it's not that hard to fix for a given target if there's some better lowering. llvm-svn: 138621
2011-08-26 04:59:24 +02:00
def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM." This wasn't the right way to enforce ordering of atomics. We are already setting the isVolatile bit on memory operands of atomic operations which is good enough to enforce the correct ordering. llvm-svn: 162732
2012-08-28 05:11:27 +02:00
(LDRBi12 addrmode_imm12:$src)>;
Atomic load/store on ARM/Thumb. I don't really like the patterns, but I'm having trouble coming up with a better way to handle them. I plan on making other targets use the same legalization ARM-without-memory-barriers is using... it's not especially efficient, but if anyone cares, it's not that hard to fix for a given target if there's some better lowering. llvm-svn: 138621
2011-08-26 04:59:24 +02:00
def : ARMPat<(atomic_load_16 addrmode3:$src),
Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM." This wasn't the right way to enforce ordering of atomics. We are already setting the isVolatile bit on memory operands of atomic operations which is good enough to enforce the correct ordering. llvm-svn: 162732
2012-08-28 05:11:27 +02:00
(LDRH addrmode3:$src)>;
Atomic load/store on ARM/Thumb. I don't really like the patterns, but I'm having trouble coming up with a better way to handle them. I plan on making other targets use the same legalization ARM-without-memory-barriers is using... it's not especially efficient, but if anyone cares, it's not that hard to fix for a given target if there's some better lowering. llvm-svn: 138621
2011-08-26 04:59:24 +02:00
def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM." This wasn't the right way to enforce ordering of atomics. We are already setting the isVolatile bit on memory operands of atomic operations which is good enough to enforce the correct ordering. llvm-svn: 162732
2012-08-28 05:11:27 +02:00
(LDRrs ldst_so_reg:$src)>;
Atomic load/store on ARM/Thumb. I don't really like the patterns, but I'm having trouble coming up with a better way to handle them. I plan on making other targets use the same legalization ARM-without-memory-barriers is using... it's not especially efficient, but if anyone cares, it's not that hard to fix for a given target if there's some better lowering. llvm-svn: 138621
2011-08-26 04:59:24 +02:00
def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM." This wasn't the right way to enforce ordering of atomics. We are already setting the isVolatile bit on memory operands of atomic operations which is good enough to enforce the correct ordering. llvm-svn: 162732
2012-08-28 05:11:27 +02:00
(LDRi12 addrmode_imm12:$src)>;
Atomic load/store on ARM/Thumb. I don't really like the patterns, but I'm having trouble coming up with a better way to handle them. I plan on making other targets use the same legalization ARM-without-memory-barriers is using... it's not especially efficient, but if anyone cares, it's not that hard to fix for a given target if there's some better lowering. llvm-svn: 138621
2011-08-26 04:59:24 +02:00
def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
(STRBrs GPR:$val, ldst_so_reg:$ptr)>;
def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
(STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
(STRH GPR:$val, addrmode3:$ptr)>;
def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
(STRrs GPR:$val, ldst_so_reg:$ptr)>;
def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
(STRi12 GPR:$val, addrmode_imm12:$ptr)>;
Reorganize a bit. No functional change, just moving patterns up. llvm-svn: 127422
2011-03-10 20:21:08 +01:00
//===----------------------------------------------------------------------===//
// Thumb Support
//
include "ARMInstrThumb.td"
//===----------------------------------------------------------------------===//
// Thumb2 Support
//
include "ARMInstrThumb2.td"
//===----------------------------------------------------------------------===//
// Floating Point Support
//
include "ARMInstrVFP.td"
//===----------------------------------------------------------------------===//
// Advanced SIMD (NEON) Support
//
include "ARMInstrNEON.td"
[ARM] First MVE instructions: scalar shifts. This introduces a new decoding table for MVE instructions, and starts by adding the family of scalar shift instructions that are part of the MVE architecture extension: saturating shifts within a single GPR, and long shifts across a pair of GPRs (both saturating and normal). Some of these shift instructions have only 3-bit register fields in the encoding, with the low bit fixed. So they can only address an odd or even numbered GPR (depending on the operand), and therefore I add two new register classes, GPREven and GPROdd. Differential Revision: https://reviews.llvm.org/D62668 Change-Id: Iad95d5f83d26aef70c674027a184a6b1e0098d33 llvm-svn: 363051
2019-06-11 14:04:32 +02:00
//===----------------------------------------------------------------------===//
// MVE Support
//
include "ARMInstrMVE.td"
Reorganize ARM assembler aliases. Consolidate the individual declarations together for ease of reference. This mirrors the organization in X86, as well, so is good for consistency. No functional change. llvm-svn: 135179
2011-07-14 21:47:47 +02:00
//===----------------------------------------------------------------------===//
// Assembler aliases
//
// Memory barriers
ARM target does not use printAliasInstr machinery which forces having special checks in ArmInstPrinter::printInstruction. This patch addresses this issue. Not all special checks could be removed: either they involve elaborated conditions under which the alias is emitted (e.g. ldm/stm on sp may be pop/push but only if the number of registers is >= 2) or the number of registers is multivalued (like happens again with ldm/stm) and they do not match the InstAlias pattern which assumes single-valued operands in the pattern. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20237 llvm-svn: 271667
2016-06-03 15:19:43 +02:00
def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>;
def : InstAlias<"dsb", (DSB 0xf), 0>, Requires<[IsARM, HasDB]>;
[ARM][v8.5A] Add speculation barriers SSBB and PSSBB This adds two new barrier instructions which can be used to restrict speculative execution of load instructions. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52484 llvm-svn: 343300
2018-09-28 10:27:56 +02:00
def : InstAlias<"ssbb", (DSB 0x0), 1>, Requires<[IsARM, HasDB]>;
def : InstAlias<"pssbb", (DSB 0x4), 1>, Requires<[IsARM, HasDB]>;
ARM target does not use printAliasInstr machinery which forces having special checks in ArmInstPrinter::printInstruction. This patch addresses this issue. Not all special checks could be removed: either they involve elaborated conditions under which the alias is emitted (e.g. ldm/stm on sp may be pop/push but only if the number of registers is >= 2) or the number of registers is multivalued (like happens again with ldm/stm) and they do not match the InstAlias pattern which assumes single-valued operands in the pattern. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20237 llvm-svn: 271667
2016-06-03 15:19:43 +02:00
def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>;
[ARM] Armv8-R DFB instruction Implement MC support for the Armv8-R 'Data Full Barrier' instruction. Differential Revision: https://reviews.llvm.org/D41430 llvm-svn: 321256
2017-12-21 12:17:49 +01:00
// Armv8-R 'Data Full Barrier'
def : InstAlias<"dfb", (DSB 0xc), 1>, Requires<[IsARM, HasDFB]>;
Reorganize ARM assembler aliases. Consolidate the individual declarations together for ease of reference. This mirrors the organization in X86, as well, so is good for consistency. No functional change. llvm-svn: 135179
2011-07-14 21:47:47 +02:00
// System instructions
def : MnemonicAlias<"swi", "svc">;
// Load / Store Multiple
def : MnemonicAlias<"ldmfd", "ldm">;
def : MnemonicAlias<"ldmia", "ldm">;
Thumb2 parsing and encoding for LDMDB. llvm-svn: 139251
2011-09-07 21:57:53 +02:00
def : MnemonicAlias<"ldmea", "ldmdb">;
Reorganize ARM assembler aliases. Consolidate the individual declarations together for ease of reference. This mirrors the organization in X86, as well, so is good for consistency. No functional change. llvm-svn: 135179
2011-07-14 21:47:47 +02:00
def : MnemonicAlias<"stmfd", "stmdb">;
def : MnemonicAlias<"stmia", "stm">;
def : MnemonicAlias<"stmea", "stm">;
[ARM] Operands for PKHTB alias should be swapped When the shift immediate is zero, PKHTB is an alias for PKHBT, but the order of the input operands needs to be swapped. Differential Revision: http://reviews.llvm.org/D16288 llvm-svn: 258044
2016-01-18 12:56:35 +01:00
// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the
// input operands swapped when the shift amount is zero (i.e., unspecified).
ARM assembly parsing and encoding for PKHBT and PKHTB instructions. llvm-svn: 135682
2011-07-21 19:23:04 +02:00
def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
ARM target does not use printAliasInstr machinery which forces having special checks in ArmInstPrinter::printInstruction. This patch addresses this issue. Not all special checks could be removed: either they involve elaborated conditions under which the alias is emitted (e.g. ldm/stm on sp may be pop/push but only if the number of registers is >= 2) or the number of registers is multivalued (like happens again with ldm/stm) and they do not match the InstAlias pattern which assumes single-valued operands in the pattern. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20237 llvm-svn: 271667
2016-06-03 15:19:43 +02:00
(PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>,
Clean up predicates on ARM target instruction aliases. llvm-svn: 138249
2011-08-22 20:04:24 +02:00
Requires<[IsARM, HasV6]>;
ARM assembly parsing and encoding for PKHBT and PKHTB instructions. llvm-svn: 135682
2011-07-21 19:23:04 +02:00
def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
ARM target does not use printAliasInstr machinery which forces having special checks in ArmInstPrinter::printInstruction. This patch addresses this issue. Not all special checks could be removed: either they involve elaborated conditions under which the alias is emitted (e.g. ldm/stm on sp may be pop/push but only if the number of registers is >= 2) or the number of registers is multivalued (like happens again with ldm/stm) and they do not match the InstAlias pattern which assumes single-valued operands in the pattern. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20237 llvm-svn: 271667
2016-06-03 15:19:43 +02:00
(PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>,
Clean up predicates on ARM target instruction aliases. llvm-svn: 138249
2011-08-22 20:04:24 +02:00
Requires<[IsARM, HasV6]>;
ARM assembly parsing POP/PUSH mnemonics. Aliases for LDM/STM. The single-register versions should encode to LDR/STR with writeback, but we don't (yet) get that correct. Neither does Darwin's system assembler, though, so that's not a deal-breaker of a limitation. llvm-svn: 135702
2011-07-21 21:57:11 +02:00
// PUSH/POP aliases for STM/LDM
Clean up predicates on ARM target instruction aliases. llvm-svn: 138249
2011-08-22 20:04:24 +02:00
def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
ARM assembly parsing support for RSB instruction. Add two-operand instruction aliases. Add parsing and encoding tests for variants of the instruction. llvm-svn: 135712
2011-07-22 00:37:43 +02:00
ARM assembly parsing and encoding support for USAT and USAT16. Use range checked immediate operands for instructions. Add tests. llvm-svn: 136285
2011-07-28 00:34:17 +02:00
// SSAT/USAT optional shift operand.
Clean up predicates on ARM target instruction aliases. llvm-svn: 138249
2011-08-22 20:04:24 +02:00
def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
(SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
Clean up predicates on ARM target instruction aliases. llvm-svn: 138249
2011-08-22 20:04:24 +02:00
def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
(USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
ARM assembly parsing aliases for extend instructions w/o rotate. llvm-svn: 136229
2011-07-27 20:19:32 +02:00
// Extend instruction optional rotate operand.
Clean up predicates on ARM target instruction aliases. llvm-svn: 138249
2011-08-22 20:04:24 +02:00
def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
(SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
Clean up predicates on ARM target instruction aliases. llvm-svn: 138249
2011-08-22 20:04:24 +02:00
def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
(SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
Clean up predicates on ARM target instruction aliases. llvm-svn: 138249
2011-08-22 20:04:24 +02:00
def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
(SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
Clean up predicates on ARM target instruction aliases. llvm-svn: 138249
2011-08-22 20:04:24 +02:00
def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
(SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
Clean up predicates on ARM target instruction aliases. llvm-svn: 138249
2011-08-22 20:04:24 +02:00
def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
(SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
Clean up predicates on ARM target instruction aliases. llvm-svn: 138249
2011-08-22 20:04:24 +02:00
def : ARMInstAlias<"sxth${p} $Rd, $Rm",
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
(SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
ARM assembly parsing aliases for extend instructions w/o rotate. llvm-svn: 136229
2011-07-27 20:19:32 +02:00
Clean up predicates on ARM target instruction aliases. llvm-svn: 138249
2011-08-22 20:04:24 +02:00
def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
(UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
Clean up predicates on ARM target instruction aliases. llvm-svn: 138249
2011-08-22 20:04:24 +02:00
def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
(UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
Clean up predicates on ARM target instruction aliases. llvm-svn: 138249
2011-08-22 20:04:24 +02:00
def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
(UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
Clean up predicates on ARM target instruction aliases. llvm-svn: 138249
2011-08-22 20:04:24 +02:00
def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
(UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
Clean up predicates on ARM target instruction aliases. llvm-svn: 138249
2011-08-22 20:04:24 +02:00
def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
(UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
Clean up predicates on ARM target instruction aliases. llvm-svn: 138249
2011-08-22 20:04:24 +02:00
def : ARMInstAlias<"uxth${p} $Rd, $Rm",
Push GPRnopc through a large number of instruction definitions to tighten operand decoding. llvm-svn: 137189
2011-08-10 02:03:03 +02:00
(UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
ARM assembly parsing and encoding for RFE instruction. Fill in the missing fixed bits and the register operand bits of the instruction encoding. Refactor the definition to make the mode explicit, which is consistent with how loads and stores are normally represented and makes parsing much easier. Add parsing aliases for pseudo-instruction variants. Update the disassembler for the new representations. Add tests for parsing and encoding. llvm-svn: 136479
2011-07-29 20:47:24 +02:00
// RFE aliases
def : MnemonicAlias<"rfefa", "rfeda">;
def : MnemonicAlias<"rfeea", "rfedb">;
def : MnemonicAlias<"rfefd", "rfeia">;
def : MnemonicAlias<"rfeed", "rfeib">;
def : MnemonicAlias<"rfe", "rfeia">;
ARM SRS instruction parsing, diassembly and encoding support. Fix the instruction encoding for operands. Refactor mode to use explicit instruction definitions per FIXME to be more consistent with loads/stores. Fix disassembler accordingly. Add tests. llvm-svn: 136509
2011-07-29 22:26:09 +02:00
// SRS aliases
ARM: Fix pseudo-instructions for SRS (Store Return State). The mapping between SRS pseudo-instructions and SRS native instructions was incorrect, the correct mapping is: srsfa -> srsib srsea -> srsia srsfd -> srsdb srsed -> srsda This fixes <rdar://problem/14214734>. llvm-svn: 185155
2013-06-28 17:09:46 +02:00
def : MnemonicAlias<"srsfa", "srsib">;
def : MnemonicAlias<"srsea", "srsia">;
def : MnemonicAlias<"srsfd", "srsdb">;
def : MnemonicAlias<"srsed", "srsda">;
ARM SRS instruction parsing, diassembly and encoding support. Fix the instruction encoding for operands. Refactor mode to use explicit instruction definitions per FIXME to be more consistent with loads/stores. Fix disassembler accordingly. Add tests. llvm-svn: 136509
2011-07-29 22:26:09 +02:00
def : MnemonicAlias<"srs", "srsia">;
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
ARM support the pre-UAL mnemonic 'qsubaddx' for 'qsax.' llvm-svn: 139796
2011-09-15 18:16:50 +02:00
// QSAX == QSUBADDX
def : MnemonicAlias<"qsubaddx", "qsax">;
Thumb2 assembly parsing and encoding for SASX. llvm-svn: 139843
2011-09-15 23:01:23 +02:00
// SASX == SADDSUBX
def : MnemonicAlias<"saddsubx", "sasx">;
Thumb2 assembly parsing and encoding for SHASX/SHSAX. llvm-svn: 139870
2011-09-16 00:34:29 +02:00
// SHASX == SHADDSUBX
def : MnemonicAlias<"shaddsubx", "shasx">;
// SHSAX == SHSUBADDX
def : MnemonicAlias<"shsubaddx", "shsax">;
Thumb2 assembly parsing and encoding for SSAX. llvm-svn: 139929
2011-09-16 20:37:10 +02:00
// SSAX == SSUBADDX
def : MnemonicAlias<"ssubaddx", "ssax">;
Thumb2 assembly parsing and encoding for UASX. llvm-svn: 140085
2011-09-20 01:05:22 +02:00
// UASX == UADDSUBX
def : MnemonicAlias<"uaddsubx", "uasx">;
Thumb2 assembly parsing and encoding for UHASX/UHSAX. llvm-svn: 140088
2011-09-20 01:13:25 +02:00
// UHASX == UHADDSUBX
def : MnemonicAlias<"uhaddsubx", "uhasx">;
// UHSAX == UHSUBADDX
def : MnemonicAlias<"uhsubaddx", "uhsax">;
Thumb2 assembly parsing and encoding for UQASX/UQSAX. llvm-svn: 140111
2011-09-20 02:18:52 +02:00
// UQASX == UQADDSUBX
def : MnemonicAlias<"uqaddsubx", "uqasx">;
// UQSAX == UQSUBADDX
def : MnemonicAlias<"uqsubaddx", "uqsax">;
Thumb2 assembly parsing and encoding for USAX. llvm-svn: 140119
2011-09-20 02:30:45 +02:00
// USAX == USUBADDX
def : MnemonicAlias<"usubaddx", "usax">;
ARM support the pre-UAL mnemonic 'qsubaddx' for 'qsax.' llvm-svn: 139796
2011-09-15 18:16:50 +02:00
[ARM] Cleanup so_imm* tblgen defintions No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
2015-01-06 16:55:09 +01:00
// "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like
ARM mode 'mov' to 'mvn' assembler alias. llvm-svn: 143237
2011-10-29 00:50:54 +02:00
// for isel.
[ARM] [Assembler] Support negative immediates for A32, T32 and T16 Summary: To support negative immediates for certain arithmetic instructions, the instruction is converted to the inverse instruction with a negated (or inverted) immediate. For example, "ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD instruction. However, "SUB r0, r1, #1" is equivalent. These conversions are different from instruction aliases. An alias maps several assembler instructions onto one encoding. A conversion, however, maps an *invalid* instruction--e.g. with an immediate that cannot be represented in the encoding--to a different (but equivalent) instruction. Several instructions with negative immediates were being converted already, but this was not systematically tested, nor did it cover all instructions. This patch implements all possible substitutions for ARM, Thumb1 and Thumb2 assembler and adds tests. It also adds a feature flag (-mattr=+no-neg-immediates) to turn these substitutions off. This is helpful for users who want their code to assemble to exactly what they wrote. Reviewers: t.p.northover, rovka, samparker, javed.absar, peter.smith, rengolin Reviewed By: javed.absar Subscribers: aadg, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D30571 llvm-svn: 298380
2017-03-21 15:59:17 +01:00
def : ARMInstSubst<"mov${s}${p} $Rd, $imm",
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
(MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
[ARM] [Assembler] Support negative immediates for A32, T32 and T16 Summary: To support negative immediates for certain arithmetic instructions, the instruction is converted to the inverse instruction with a negated (or inverted) immediate. For example, "ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD instruction. However, "SUB r0, r1, #1" is equivalent. These conversions are different from instruction aliases. An alias maps several assembler instructions onto one encoding. A conversion, however, maps an *invalid* instruction--e.g. with an immediate that cannot be represented in the encoding--to a different (but equivalent) instruction. Several instructions with negative immediates were being converted already, but this was not systematically tested, nor did it cover all instructions. This patch implements all possible substitutions for ARM, Thumb1 and Thumb2 assembler and adds tests. It also adds a feature flag (-mattr=+no-neg-immediates) to turn these substitutions off. This is helpful for users who want their code to assemble to exactly what they wrote. Reviewers: t.p.northover, rovka, samparker, javed.absar, peter.smith, rengolin Reviewed By: javed.absar Subscribers: aadg, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D30571 llvm-svn: 298380
2017-03-21 15:59:17 +01:00
def : ARMInstSubst<"mvn${s}${p} $Rd, $imm",
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
(MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
ARM assembly aliases for BIC<-->AND (immediate). When the immediate operand of an AND or BIC instruction isn't representable in the immediate field of the instruction, but the bitwise negation of the immediate is, assemble the instruction as the inverse operation instead with the inverted immediate as the operand. rdar://10550057 llvm-svn: 146283
2011-12-09 23:02:17 +01:00
// Same for AND <--> BIC
[ARM] [Assembler] Support negative immediates for A32, T32 and T16 Summary: To support negative immediates for certain arithmetic instructions, the instruction is converted to the inverse instruction with a negated (or inverted) immediate. For example, "ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD instruction. However, "SUB r0, r1, #1" is equivalent. These conversions are different from instruction aliases. An alias maps several assembler instructions onto one encoding. A conversion, however, maps an *invalid* instruction--e.g. with an immediate that cannot be represented in the encoding--to a different (but equivalent) instruction. Several instructions with negative immediates were being converted already, but this was not systematically tested, nor did it cover all instructions. This patch implements all possible substitutions for ARM, Thumb1 and Thumb2 assembler and adds tests. It also adds a feature flag (-mattr=+no-neg-immediates) to turn these substitutions off. This is helpful for users who want their code to assemble to exactly what they wrote. Reviewers: t.p.northover, rovka, samparker, javed.absar, peter.smith, rengolin Reviewed By: javed.absar Subscribers: aadg, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D30571 llvm-svn: 298380
2017-03-21 15:59:17 +01:00
def : ARMInstSubst<"bic${s}${p} $Rd, $Rn, $imm",
[ARM] Allowing SP/PC for AND/BIC mod_imm_not AND/BIC instructions do accept SP/PC, so the register class should be more generic (rGPR -> GPR) to cope with that case. Adding more tests. llvm-svn: 255034
2015-12-08 19:10:58 +01:00
(ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
ARM assembly aliases for BIC<-->AND (immediate). When the immediate operand of an AND or BIC instruction isn't representable in the immediate field of the instruction, but the bitwise negation of the immediate is, assemble the instruction as the inverse operation instead with the inverted immediate as the operand. rdar://10550057 llvm-svn: 146283
2011-12-09 23:02:17 +01:00
pred:$p, cc_out:$s)>;
[ARM] [Assembler] Support negative immediates for A32, T32 and T16 Summary: To support negative immediates for certain arithmetic instructions, the instruction is converted to the inverse instruction with a negated (or inverted) immediate. For example, "ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD instruction. However, "SUB r0, r1, #1" is equivalent. These conversions are different from instruction aliases. An alias maps several assembler instructions onto one encoding. A conversion, however, maps an *invalid* instruction--e.g. with an immediate that cannot be represented in the encoding--to a different (but equivalent) instruction. Several instructions with negative immediates were being converted already, but this was not systematically tested, nor did it cover all instructions. This patch implements all possible substitutions for ARM, Thumb1 and Thumb2 assembler and adds tests. It also adds a feature flag (-mattr=+no-neg-immediates) to turn these substitutions off. This is helpful for users who want their code to assemble to exactly what they wrote. Reviewers: t.p.northover, rovka, samparker, javed.absar, peter.smith, rengolin Reviewed By: javed.absar Subscribers: aadg, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D30571 llvm-svn: 298380
2017-03-21 15:59:17 +01:00
def : ARMInstSubst<"bic${s}${p} $Rdn, $imm",
[ARM] Allowing SP/PC for AND/BIC mod_imm_not AND/BIC instructions do accept SP/PC, so the register class should be more generic (rGPR -> GPR) to cope with that case. Adding more tests. llvm-svn: 255034
2015-12-08 19:10:58 +01:00
(ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm,
ARM assembly aliases for BIC<-->AND (immediate). When the immediate operand of an AND or BIC instruction isn't representable in the immediate field of the instruction, but the bitwise negation of the immediate is, assemble the instruction as the inverse operation instead with the inverted immediate as the operand. rdar://10550057 llvm-svn: 146283
2011-12-09 23:02:17 +01:00
pred:$p, cc_out:$s)>;
[ARM] [Assembler] Support negative immediates for A32, T32 and T16 Summary: To support negative immediates for certain arithmetic instructions, the instruction is converted to the inverse instruction with a negated (or inverted) immediate. For example, "ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD instruction. However, "SUB r0, r1, #1" is equivalent. These conversions are different from instruction aliases. An alias maps several assembler instructions onto one encoding. A conversion, however, maps an *invalid* instruction--e.g. with an immediate that cannot be represented in the encoding--to a different (but equivalent) instruction. Several instructions with negative immediates were being converted already, but this was not systematically tested, nor did it cover all instructions. This patch implements all possible substitutions for ARM, Thumb1 and Thumb2 assembler and adds tests. It also adds a feature flag (-mattr=+no-neg-immediates) to turn these substitutions off. This is helpful for users who want their code to assemble to exactly what they wrote. Reviewers: t.p.northover, rovka, samparker, javed.absar, peter.smith, rengolin Reviewed By: javed.absar Subscribers: aadg, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D30571 llvm-svn: 298380
2017-03-21 15:59:17 +01:00
def : ARMInstSubst<"and${s}${p} $Rd, $Rn, $imm",
[ARM] Allowing SP/PC for AND/BIC mod_imm_not AND/BIC instructions do accept SP/PC, so the register class should be more generic (rGPR -> GPR) to cope with that case. Adding more tests. llvm-svn: 255034
2015-12-08 19:10:58 +01:00
(BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
ARM assembly aliases for BIC<-->AND (immediate). When the immediate operand of an AND or BIC instruction isn't representable in the immediate field of the instruction, but the bitwise negation of the immediate is, assemble the instruction as the inverse operation instead with the inverted immediate as the operand. rdar://10550057 llvm-svn: 146283
2011-12-09 23:02:17 +01:00
pred:$p, cc_out:$s)>;
[ARM] [Assembler] Support negative immediates for A32, T32 and T16 Summary: To support negative immediates for certain arithmetic instructions, the instruction is converted to the inverse instruction with a negated (or inverted) immediate. For example, "ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD instruction. However, "SUB r0, r1, #1" is equivalent. These conversions are different from instruction aliases. An alias maps several assembler instructions onto one encoding. A conversion, however, maps an *invalid* instruction--e.g. with an immediate that cannot be represented in the encoding--to a different (but equivalent) instruction. Several instructions with negative immediates were being converted already, but this was not systematically tested, nor did it cover all instructions. This patch implements all possible substitutions for ARM, Thumb1 and Thumb2 assembler and adds tests. It also adds a feature flag (-mattr=+no-neg-immediates) to turn these substitutions off. This is helpful for users who want their code to assemble to exactly what they wrote. Reviewers: t.p.northover, rovka, samparker, javed.absar, peter.smith, rengolin Reviewed By: javed.absar Subscribers: aadg, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D30571 llvm-svn: 298380
2017-03-21 15:59:17 +01:00
def : ARMInstSubst<"and${s}${p} $Rdn, $imm",
[ARM] Allowing SP/PC for AND/BIC mod_imm_not AND/BIC instructions do accept SP/PC, so the register class should be more generic (rGPR -> GPR) to cope with that case. Adding more tests. llvm-svn: 255034
2015-12-08 19:10:58 +01:00
(BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm,
ARM assembly aliases for BIC<-->AND (immediate). When the immediate operand of an AND or BIC instruction isn't representable in the immediate field of the instruction, but the bitwise negation of the immediate is, assemble the instruction as the inverse operation instead with the inverted immediate as the operand. rdar://10550057 llvm-svn: 146283
2011-12-09 23:02:17 +01:00
pred:$p, cc_out:$s)>;
[ARM] Cleanup so_imm* tblgen defintions No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
2015-01-06 16:55:09 +01:00
// Likewise, "add Rd, mod_imm_neg" -> sub
[ARM] [Assembler] Support negative immediates for A32, T32 and T16 Summary: To support negative immediates for certain arithmetic instructions, the instruction is converted to the inverse instruction with a negated (or inverted) immediate. For example, "ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD instruction. However, "SUB r0, r1, #1" is equivalent. These conversions are different from instruction aliases. An alias maps several assembler instructions onto one encoding. A conversion, however, maps an *invalid* instruction--e.g. with an immediate that cannot be represented in the encoding--to a different (but equivalent) instruction. Several instructions with negative immediates were being converted already, but this was not systematically tested, nor did it cover all instructions. This patch implements all possible substitutions for ARM, Thumb1 and Thumb2 assembler and adds tests. It also adds a feature flag (-mattr=+no-neg-immediates) to turn these substitutions off. This is helpful for users who want their code to assemble to exactly what they wrote. Reviewers: t.p.northover, rovka, samparker, javed.absar, peter.smith, rengolin Reviewed By: javed.absar Subscribers: aadg, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D30571 llvm-svn: 298380
2017-03-21 15:59:17 +01:00
def : ARMInstSubst<"add${s}${p} $Rd, $Rn, $imm",
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
(SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
[ARM] [Assembler] Support negative immediates for A32, T32 and T16 Summary: To support negative immediates for certain arithmetic instructions, the instruction is converted to the inverse instruction with a negated (or inverted) immediate. For example, "ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD instruction. However, "SUB r0, r1, #1" is equivalent. These conversions are different from instruction aliases. An alias maps several assembler instructions onto one encoding. A conversion, however, maps an *invalid* instruction--e.g. with an immediate that cannot be represented in the encoding--to a different (but equivalent) instruction. Several instructions with negative immediates were being converted already, but this was not systematically tested, nor did it cover all instructions. This patch implements all possible substitutions for ARM, Thumb1 and Thumb2 assembler and adds tests. It also adds a feature flag (-mattr=+no-neg-immediates) to turn these substitutions off. This is helpful for users who want their code to assemble to exactly what they wrote. Reviewers: t.p.northover, rovka, samparker, javed.absar, peter.smith, rengolin Reviewed By: javed.absar Subscribers: aadg, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D30571 llvm-svn: 298380
2017-03-21 15:59:17 +01:00
def : ARMInstSubst<"add${s}${p} $Rd, $imm",
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
(SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
[ARM] [Assembler] Support negative immediates for A32, T32 and T16 Summary: To support negative immediates for certain arithmetic instructions, the instruction is converted to the inverse instruction with a negated (or inverted) immediate. For example, "ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD instruction. However, "SUB r0, r1, #1" is equivalent. These conversions are different from instruction aliases. An alias maps several assembler instructions onto one encoding. A conversion, however, maps an *invalid* instruction--e.g. with an immediate that cannot be represented in the encoding--to a different (but equivalent) instruction. Several instructions with negative immediates were being converted already, but this was not systematically tested, nor did it cover all instructions. This patch implements all possible substitutions for ARM, Thumb1 and Thumb2 assembler and adds tests. It also adds a feature flag (-mattr=+no-neg-immediates) to turn these substitutions off. This is helpful for users who want their code to assemble to exactly what they wrote. Reviewers: t.p.northover, rovka, samparker, javed.absar, peter.smith, rengolin Reviewed By: javed.absar Subscribers: aadg, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D30571 llvm-svn: 298380
2017-03-21 15:59:17 +01:00
// Likewise, "sub Rd, mod_imm_neg" -> add
def : ARMInstSubst<"sub${s}${p} $Rd, $Rn, $imm",
(ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
def : ARMInstSubst<"sub${s}${p} $Rd, $imm",
(ADDri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
def : ARMInstSubst<"adc${s}${p} $Rd, $Rn, $imm",
(SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
def : ARMInstSubst<"adc${s}${p} $Rdn, $imm",
(SBCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
def : ARMInstSubst<"sbc${s}${p} $Rd, $Rn, $imm",
(ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
def : ARMInstSubst<"sbc${s}${p} $Rdn, $imm",
(ADCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
[ARM] Cleanup so_imm* tblgen defintions No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
2015-01-06 16:55:09 +01:00
// Same for CMP <--> CMN via mod_imm_neg
[ARM] [Assembler] Support negative immediates for A32, T32 and T16 Summary: To support negative immediates for certain arithmetic instructions, the instruction is converted to the inverse instruction with a negated (or inverted) immediate. For example, "ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD instruction. However, "SUB r0, r1, #1" is equivalent. These conversions are different from instruction aliases. An alias maps several assembler instructions onto one encoding. A conversion, however, maps an *invalid* instruction--e.g. with an immediate that cannot be represented in the encoding--to a different (but equivalent) instruction. Several instructions with negative immediates were being converted already, but this was not systematically tested, nor did it cover all instructions. This patch implements all possible substitutions for ARM, Thumb1 and Thumb2 assembler and adds tests. It also adds a feature flag (-mattr=+no-neg-immediates) to turn these substitutions off. This is helpful for users who want their code to assemble to exactly what they wrote. Reviewers: t.p.northover, rovka, samparker, javed.absar, peter.smith, rengolin Reviewed By: javed.absar Subscribers: aadg, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D30571 llvm-svn: 298380
2017-03-21 15:59:17 +01:00
def : ARMInstSubst<"cmp${p} $Rd, $imm",
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
(CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
[ARM] [Assembler] Support negative immediates for A32, T32 and T16 Summary: To support negative immediates for certain arithmetic instructions, the instruction is converted to the inverse instruction with a negated (or inverted) immediate. For example, "ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD instruction. However, "SUB r0, r1, #1" is equivalent. These conversions are different from instruction aliases. An alias maps several assembler instructions onto one encoding. A conversion, however, maps an *invalid* instruction--e.g. with an immediate that cannot be represented in the encoding--to a different (but equivalent) instruction. Several instructions with negative immediates were being converted already, but this was not systematically tested, nor did it cover all instructions. This patch implements all possible substitutions for ARM, Thumb1 and Thumb2 assembler and adds tests. It also adds a feature flag (-mattr=+no-neg-immediates) to turn these substitutions off. This is helpful for users who want their code to assemble to exactly what they wrote. Reviewers: t.p.northover, rovka, samparker, javed.absar, peter.smith, rengolin Reviewed By: javed.absar Subscribers: aadg, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D30571 llvm-svn: 298380
2017-03-21 15:59:17 +01:00
def : ARMInstSubst<"cmn${p} $Rd, $imm",
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 11:53:20 +01:00
(CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
ARM assembly parsing for ASR(immediate). Start of rdar://9704684 llvm-svn: 144293
2011-11-10 17:44:55 +01:00
// The shifter forms of the MOV instruction are aliased to the ASR, LSL,
// LSR, ROR, and RRX instructions.
// FIXME: We need C++ parser hooks to map the alias to the MOV
// encoding. It seems we should be able to do that sort of thing
// in tblgen, but it could get ugly.
ARM let TableGen handle a few two-operand aliases. No need for these explicit aliases anymore. Nuke 'em. llvm-svn: 155173
2012-04-20 01:59:26 +02:00
let TwoOperandAliasConstraint = "$Rm = $Rd" in {
ARM assembly parsing for ASR(immediate). Start of rdar://9704684 llvm-svn: 144293
2011-11-10 17:44:55 +01:00
def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
ARM assembly parsing for LSR/LSL/ROR(immediate). More of rdar://9704684 llvm-svn: 144301
2011-11-10 20:18:01 +01:00
(ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
cc_out:$s)>;
def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
(ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
cc_out:$s)>;
def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
(ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
cc_out:$s)>;
def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
(ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
ARM assembly parsing for ASR(immediate). Start of rdar://9704684 llvm-svn: 144293
2011-11-10 17:44:55 +01:00
cc_out:$s)>;
ARM let TableGen handle a few two-operand aliases. No need for these explicit aliases anymore. Nuke 'em. llvm-svn: 155173
2012-04-20 01:59:26 +02:00
}
ARM assembly parsing for RRX mnemonic. rdar://9704684 llvm-svn: 144812
2011-11-16 20:05:59 +01:00
def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
This is a simple patch that changes RRX and RRXS to accept all registers as operands. According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp. llvm-svn: 183307
2013-06-05 15:23:51 +02:00
(ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
ARM let TableGen handle a few two-operand aliases. No need for these explicit aliases anymore. Nuke 'em. llvm-svn: 155173
2012-04-20 01:59:26 +02:00
let TwoOperandAliasConstraint = "$Rn = $Rd" in {
ARM mode aliases for bitwise instructions w/ register operands. rdar://9704684 llvm-svn: 144803
2011-11-16 19:31:45 +01:00
def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
(ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
cc_out:$s)>;
def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
(ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
cc_out:$s)>;
def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
(ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
cc_out:$s)>;
def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
(ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
cc_out:$s)>;
ARM let TableGen handle a few two-operand aliases. No need for these explicit aliases anymore. Nuke 'em. llvm-svn: 155173
2012-04-20 01:59:26 +02:00
}
ARM pre-UAL NEG mnemonic for convenience when porting old code. llvm-svn: 146511
2011-12-13 21:23:22 +01:00
// "neg" is and alias for "rsb rd, rn, #0"
def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
(RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
ARM assemly parsing and validation of IT instruction. "Although a Thumb2 instruction, the IT mnemonic shall be permitted in ARM mode, and the condition verified to match the condition code(s) on the following instruction(s)." PR11853 llvm-svn: 148969
2012-01-25 20:52:01 +01:00
ARM pre-v6 alias for 'nop' to 'mov r0, r0' llvm-svn: 152185
2012-03-07 01:52:41 +01:00
// Pre-v6, 'mov r0, r0' was used as a NOP encoding.
def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
Requires<[IsARM, NoV6]>;
Add missing mul aliases for armv4 support. Add checks that armv4 can assemble the various mul instructions. llvm-svn: 199026
2014-01-12 04:35:18 +01:00
// MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
// the instruction definitions need difference constraints pre-v6.
// Use these aliases for the assembly parsing on pre-v6.
def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
ARM target does not use printAliasInstr machinery which forces having special checks in ArmInstPrinter::printInstruction. This patch addresses this issue. Not all special checks could be removed: either they involve elaborated conditions under which the alias is emitted (e.g. ldm/stm on sp may be pop/push but only if the number of registers is >= 2) or the number of registers is multivalued (like happens again with ldm/stm) and they do not match the InstAlias pattern which assumes single-valued operands in the pattern. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20237 llvm-svn: 271667
2016-06-03 15:19:43 +02:00
(MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>,
Add missing mul aliases for armv4 support. Add checks that armv4 can assemble the various mul instructions. llvm-svn: 199026
2014-01-12 04:35:18 +01:00
Requires<[IsARM, NoV6]>;
Add MLA alias for ARMv4 support. Fix MLA defs to use register class GPRnopc. Add encoding tests for multiply instructions. (Alias for MUL/SMLAL/UMLAL added by r199026.) Patch by Zhaoshi. llvm-svn: 199491
2014-01-17 14:53:08 +01:00
def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
(MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
ARM target does not use printAliasInstr machinery which forces having special checks in ArmInstPrinter::printInstruction. This patch addresses this issue. Not all special checks could be removed: either they involve elaborated conditions under which the alias is emitted (e.g. ldm/stm on sp may be pop/push but only if the number of registers is >= 2) or the number of registers is multivalued (like happens again with ldm/stm) and they do not match the InstAlias pattern which assumes single-valued operands in the pattern. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20237 llvm-svn: 271667
2016-06-03 15:19:43 +02:00
pred:$p, cc_out:$s), 0>,
Add MLA alias for ARMv4 support. Fix MLA defs to use register class GPRnopc. Add encoding tests for multiply instructions. (Alias for MUL/SMLAL/UMLAL added by r199026.) Patch by Zhaoshi. llvm-svn: 199491
2014-01-17 14:53:08 +01:00
Requires<[IsARM, NoV6]>;
Add missing mul aliases for armv4 support. Add checks that armv4 can assemble the various mul instructions. llvm-svn: 199026
2014-01-12 04:35:18 +01:00
def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
ARM target does not use printAliasInstr machinery which forces having special checks in ArmInstPrinter::printInstruction. This patch addresses this issue. Not all special checks could be removed: either they involve elaborated conditions under which the alias is emitted (e.g. ldm/stm on sp may be pop/push but only if the number of registers is >= 2) or the number of registers is multivalued (like happens again with ldm/stm) and they do not match the InstAlias pattern which assumes single-valued operands in the pattern. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20237 llvm-svn: 271667
2016-06-03 15:19:43 +02:00
(SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
Add missing mul aliases for armv4 support. Add checks that armv4 can assemble the various mul instructions. llvm-svn: 199026
2014-01-12 04:35:18 +01:00
Requires<[IsARM, NoV6]>;
def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
ARM target does not use printAliasInstr machinery which forces having special checks in ArmInstPrinter::printInstruction. This patch addresses this issue. Not all special checks could be removed: either they involve elaborated conditions under which the alias is emitted (e.g. ldm/stm on sp may be pop/push but only if the number of registers is >= 2) or the number of registers is multivalued (like happens again with ldm/stm) and they do not match the InstAlias pattern which assumes single-valued operands in the pattern. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20237 llvm-svn: 271667
2016-06-03 15:19:43 +02:00
(UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
Add missing mul aliases for armv4 support. Add checks that armv4 can assemble the various mul instructions. llvm-svn: 199026
2014-01-12 04:35:18 +01:00
Requires<[IsARM, NoV6]>;
ARM pre-v6 assembly parsing for umull/smull. llvm-svn: 152188
2012-03-07 02:09:17 +01:00
def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
ARM target does not use printAliasInstr machinery which forces having special checks in ArmInstPrinter::printInstruction. This patch addresses this issue. Not all special checks could be removed: either they involve elaborated conditions under which the alias is emitted (e.g. ldm/stm on sp may be pop/push but only if the number of registers is >= 2) or the number of registers is multivalued (like happens again with ldm/stm) and they do not match the InstAlias pattern which assumes single-valued operands in the pattern. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20237 llvm-svn: 271667
2016-06-03 15:19:43 +02:00
(SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
ARM pre-v6 assembly parsing for umull/smull. llvm-svn: 152188
2012-03-07 02:09:17 +01:00
Requires<[IsARM, NoV6]>;
def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
ARM target does not use printAliasInstr machinery which forces having special checks in ArmInstPrinter::printInstruction. This patch addresses this issue. Not all special checks could be removed: either they involve elaborated conditions under which the alias is emitted (e.g. ldm/stm on sp may be pop/push but only if the number of registers is >= 2) or the number of registers is multivalued (like happens again with ldm/stm) and they do not match the InstAlias pattern which assumes single-valued operands in the pattern. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20237 llvm-svn: 271667
2016-06-03 15:19:43 +02:00
(UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
ARM pre-v6 assembly parsing for umull/smull. llvm-svn: 152188
2012-03-07 02:09:17 +01:00
Requires<[IsARM, NoV6]>;
ARM assemly parsing and validation of IT instruction. "Although a Thumb2 instruction, the IT mnemonic shall be permitted in ARM mode, and the condition verified to match the condition code(s) on the following instruction(s)." PR11853 llvm-svn: 148969
2012-01-25 20:52:01 +01:00
// 'it' blocks in ARM mode just validate the predicates. The IT itself
// is discarded.
[ARM] Warn on deprecated IT blocks in v8 AArch32 assembly. Patch by Artyom Skrobov. llvm-svn: 191885
2013-10-03 11:31:51 +02:00
def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
ComplexDeprecationPredicate<"IT">;
ARM: add @llvm.arm.space intrinsic for testing ConstantIslands. Creating tests for the ConstantIslands pass is very difficult, since it depends on precise layout details. Having the ability to precisely inject a number of bytes into the stream helps greatly. llvm-svn: 221903
2014-11-13 18:58:48 +01:00
let mayLoad = 1, mayStore =1, hasSideEffects = 1 in
def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
NoItinerary,
[(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>;
ARM: use a pseudo-instruction for cmpxchg at -O0. The fast register-allocator cannot cope with inter-block dependencies without spilling. This is fine for ldrex/strex loops coming from atomicrmw instructions where any value produced within a block is dead by the end, but not for cmpxchg. So we lower a cmpxchg at -O0 via a pseudo-inst that gets expanded after regalloc. Fortunately this is at -O0 so we don't have to care about performance. This simplifies the various axes of expansion considerably: we assume a strong seq_cst operation and ensure ordering via the always-present DMB instructions rather than v8 acquire/release instructions. Should fix the 32-bit part of PR25526. llvm-svn: 266679
2016-04-18 23:48:55 +02:00
//===----------------------------------
// Atomic cmpxchg for -O0
//===----------------------------------
// The fast register allocator used during -O0 inserts spills to cover any VRegs
// live across basic block boundaries. When this happens between an LDXR and an
// STXR it can clear the exclusive monitor, causing all cmpxchg attempts to
// fail.
// Unfortunately, this means we have to have an alternative (expanded
// post-regalloc) path for -O0 compilations. Fortunately this path can be
// significantly more naive than the standard expansion: we conservatively
// assume seq_cst, strong cmpxchg and omit clrex on failure.
ARM: Fix CMP_SWAP expansion Clean up after my misguided attempt in r304267 to "fix" CMP_SWAP returning an uninitialized status value. - I was always using tMOVi8 to zero the status register which cannot encode higher register numbers and llvm would silently miscompile) - Nobody was ever looking at that status value outside the expansion. ARMDAGToDAGISel::SelectCMP_SWAP() the only place creating CMP_SWAP instructions was not mapping anything to it. (The cmpxchg status value from llvm IR is lowered to a manual comparison after the CMP_SWAP) So this: - Renames the register from "status" to "temp" it make it obvious that it isn't used outside the expansion. - Remove the zeroing status/temp register. - Keep the live-in list improvements from r304267 Fixes http://llvm.org/PR34056 llvm-svn: 310534
2017-08-10 00:22:05 +02:00
let Constraints = "@earlyclobber $Rd,@earlyclobber $temp",
ARM: use a pseudo-instruction for cmpxchg at -O0. The fast register-allocator cannot cope with inter-block dependencies without spilling. This is fine for ldrex/strex loops coming from atomicrmw instructions where any value produced within a block is dead by the end, but not for cmpxchg. So we lower a cmpxchg at -O0 via a pseudo-inst that gets expanded after regalloc. Fortunately this is at -O0 so we don't have to care about performance. This simplifies the various axes of expansion considerably: we assume a strong seq_cst operation and ensure ordering via the always-present DMB instructions rather than v8 acquire/release instructions. Should fix the 32-bit part of PR25526. llvm-svn: 266679
2016-04-18 23:48:55 +02:00
mayLoad = 1, mayStore = 1 in {
ARM: Fix CMP_SWAP expansion Clean up after my misguided attempt in r304267 to "fix" CMP_SWAP returning an uninitialized status value. - I was always using tMOVi8 to zero the status register which cannot encode higher register numbers and llvm would silently miscompile) - Nobody was ever looking at that status value outside the expansion. ARMDAGToDAGISel::SelectCMP_SWAP() the only place creating CMP_SWAP instructions was not mapping anything to it. (The cmpxchg status value from llvm IR is lowered to a manual comparison after the CMP_SWAP) So this: - Renames the register from "status" to "temp" it make it obvious that it isn't used outside the expansion. - Remove the zeroing status/temp register. - Keep the live-in list improvements from r304267 Fixes http://llvm.org/PR34056 llvm-svn: 310534
2017-08-10 00:22:05 +02:00
def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
ARM: use a pseudo-instruction for cmpxchg at -O0. The fast register-allocator cannot cope with inter-block dependencies without spilling. This is fine for ldrex/strex loops coming from atomicrmw instructions where any value produced within a block is dead by the end, but not for cmpxchg. So we lower a cmpxchg at -O0 via a pseudo-inst that gets expanded after regalloc. Fortunately this is at -O0 so we don't have to care about performance. This simplifies the various axes of expansion considerably: we assume a strong seq_cst operation and ensure ordering via the always-present DMB instructions rather than v8 acquire/release instructions. Should fix the 32-bit part of PR25526. llvm-svn: 266679
2016-04-18 23:48:55 +02:00
(ins GPR:$addr, GPR:$desired, GPR:$new),
NoItinerary, []>, Sched<[]>;
ARM: Fix CMP_SWAP expansion Clean up after my misguided attempt in r304267 to "fix" CMP_SWAP returning an uninitialized status value. - I was always using tMOVi8 to zero the status register which cannot encode higher register numbers and llvm would silently miscompile) - Nobody was ever looking at that status value outside the expansion. ARMDAGToDAGISel::SelectCMP_SWAP() the only place creating CMP_SWAP instructions was not mapping anything to it. (The cmpxchg status value from llvm IR is lowered to a manual comparison after the CMP_SWAP) So this: - Renames the register from "status" to "temp" it make it obvious that it isn't used outside the expansion. - Remove the zeroing status/temp register. - Keep the live-in list improvements from r304267 Fixes http://llvm.org/PR34056 llvm-svn: 310534
2017-08-10 00:22:05 +02:00
def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
ARM: use a pseudo-instruction for cmpxchg at -O0. The fast register-allocator cannot cope with inter-block dependencies without spilling. This is fine for ldrex/strex loops coming from atomicrmw instructions where any value produced within a block is dead by the end, but not for cmpxchg. So we lower a cmpxchg at -O0 via a pseudo-inst that gets expanded after regalloc. Fortunately this is at -O0 so we don't have to care about performance. This simplifies the various axes of expansion considerably: we assume a strong seq_cst operation and ensure ordering via the always-present DMB instructions rather than v8 acquire/release instructions. Should fix the 32-bit part of PR25526. llvm-svn: 266679
2016-04-18 23:48:55 +02:00
(ins GPR:$addr, GPR:$desired, GPR:$new),
NoItinerary, []>, Sched<[]>;
ARM: Fix CMP_SWAP expansion Clean up after my misguided attempt in r304267 to "fix" CMP_SWAP returning an uninitialized status value. - I was always using tMOVi8 to zero the status register which cannot encode higher register numbers and llvm would silently miscompile) - Nobody was ever looking at that status value outside the expansion. ARMDAGToDAGISel::SelectCMP_SWAP() the only place creating CMP_SWAP instructions was not mapping anything to it. (The cmpxchg status value from llvm IR is lowered to a manual comparison after the CMP_SWAP) So this: - Renames the register from "status" to "temp" it make it obvious that it isn't used outside the expansion. - Remove the zeroing status/temp register. - Keep the live-in list improvements from r304267 Fixes http://llvm.org/PR34056 llvm-svn: 310534
2017-08-10 00:22:05 +02:00
def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
ARM: use a pseudo-instruction for cmpxchg at -O0. The fast register-allocator cannot cope with inter-block dependencies without spilling. This is fine for ldrex/strex loops coming from atomicrmw instructions where any value produced within a block is dead by the end, but not for cmpxchg. So we lower a cmpxchg at -O0 via a pseudo-inst that gets expanded after regalloc. Fortunately this is at -O0 so we don't have to care about performance. This simplifies the various axes of expansion considerably: we assume a strong seq_cst operation and ensure ordering via the always-present DMB instructions rather than v8 acquire/release instructions. Should fix the 32-bit part of PR25526. llvm-svn: 266679
2016-04-18 23:48:55 +02:00
(ins GPR:$addr, GPR:$desired, GPR:$new),
NoItinerary, []>, Sched<[]>;
ARM: Fix CMP_SWAP expansion Clean up after my misguided attempt in r304267 to "fix" CMP_SWAP returning an uninitialized status value. - I was always using tMOVi8 to zero the status register which cannot encode higher register numbers and llvm would silently miscompile) - Nobody was ever looking at that status value outside the expansion. ARMDAGToDAGISel::SelectCMP_SWAP() the only place creating CMP_SWAP instructions was not mapping anything to it. (The cmpxchg status value from llvm IR is lowered to a manual comparison after the CMP_SWAP) So this: - Renames the register from "status" to "temp" it make it obvious that it isn't used outside the expansion. - Remove the zeroing status/temp register. - Keep the live-in list improvements from r304267 Fixes http://llvm.org/PR34056 llvm-svn: 310534
2017-08-10 00:22:05 +02:00
def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp),
ARM: use a pseudo-instruction for cmpxchg at -O0. The fast register-allocator cannot cope with inter-block dependencies without spilling. This is fine for ldrex/strex loops coming from atomicrmw instructions where any value produced within a block is dead by the end, but not for cmpxchg. So we lower a cmpxchg at -O0 via a pseudo-inst that gets expanded after regalloc. Fortunately this is at -O0 so we don't have to care about performance. This simplifies the various axes of expansion considerably: we assume a strong seq_cst operation and ensure ordering via the always-present DMB instructions rather than v8 acquire/release instructions. Should fix the 32-bit part of PR25526. llvm-svn: 266679
2016-04-18 23:48:55 +02:00
(ins GPR:$addr, GPRPair:$desired, GPRPair:$new),
NoItinerary, []>, Sched<[]>;
}
ARM: lower "fence singlethread" to a pure compiler barrier. Single-threaded fences aren't required to provide any synchronization with other processing elements so there's no need for a DMB. They should still be a barrier for compiler optimizations though. llvm-svn: 300904
2017-04-20 23:56:52 +02:00
def CompilerBarrier : PseudoInst<(outs), (ins i32imm:$ordering), NoItinerary,
[(atomic_fence imm:$ordering, 0)]> {
let hasSideEffects = 1;
let Size = 0;
let AsmString = "@ COMPILER BARRIER";
}
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