..
GlobalISel
[GISel]: Don't create G_MUL with 1 during translation of GEP
2018-01-05 02:56:28 +00:00
128bit_load_store.ll
a57-csel.ll
aarch64_f16_be.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
aarch64_tree_tests.ll
aarch64_win64cc_vararg.ll
aarch64-2014-08-11-MachineCombinerCrash.ll
aarch64-2014-12-02-combine-soften.ll
aarch64-a57-fp-load-balancing.ll
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
aarch64-address-type-promotion-assertion.ll
aarch64-address-type-promotion.ll
aarch64-addv.ll
aarch64-be-bv.ll
aarch64-codegen-prepare-atp.ll
aarch64-combine-fmul-fsub.mir
[AArch64] Fix -mcpu option in aarch64-combine-fmul-fsub.mir (NFC)
2018-01-05 11:17:48 +00:00
aarch64-DAGCombine-findBetterNeighborChains-crash.ll
aarch64-dynamic-stack-layout.ll
aarch64-fix-cortex-a53-835769.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
aarch64-fold-lslfast.ll
Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding""
2017-10-03 16:59:13 +00:00
aarch64-gep-opt.ll
aarch64-loop-gep-opt.ll
[AArch64] Use LateSimplifyCFG after expanding atomic operations.
2017-10-03 22:39:24 +00:00
aarch64-minmaxv.ll
aarch64-named-reg-w18.ll
aarch64-named-reg-x18.ll
aarch64-neon-v1i1-setcc.ll
aarch64-smax-constantfold.ll
aarch64-smull.ll
aarch64-stp-cluster.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
aarch64-tbz.ll
aarch64-tryBitfieldInsertOpFromOr-crash.ll
aarch64-vcvtfp2fxs-combine.ll
aarch64-wide-shuffle.ll
aarch-multipart.ll
adc.ll
addcarry-crash.ll
addsub_ext.ll
addsub-shifted.ll
addsub.ll
alloca.ll
analyze-branch.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
analyzecmp.ll
and-mask-removal.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
and-sink.ll
andandshift.ll
argument-blocks.ll
arm64-2011-03-09-CPSRSpill.ll
arm64-2011-03-17-AsmPrinterCrash.ll
Canonicalize the representation of empty an expression in DIGlobalVariableExpression
2017-08-30 18:06:51 +00:00
arm64-2011-03-21-Unaligned-Frame-Index.ll
arm64-2011-04-21-CPSRBug.ll
arm64-2011-10-18-LdStOptBug.ll
arm64-2012-01-11-ComparisonDAGCrash.ll
arm64-2012-05-07-DAGCombineVectorExtract.ll
arm64-2012-05-07-MemcpyAlignBug.ll
arm64-2012-05-09-LOADgot-bug.ll
arm64-2012-05-22-LdStOptBug.ll
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
arm64-2012-06-06-FPToUI.ll
arm64-2012-07-11-InstrEmitterBug.ll
arm64-2013-01-13-ffast-fcmp.ll
arm64-2013-01-23-frem-crash.ll
arm64-2013-01-23-sext-crash.ll
arm64-2013-02-12-shufv8i8.ll
arm64-aapcs-be.ll
arm64-aapcs.ll
arm64-abi_align.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-abi-varargs.ll
arm64-abi.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-addp.ll
arm64-addr-mode-folding.ll
arm64-addr-type-promotion.ll
arm64-addrmode.ll
arm64-AdvSIMD-Scalar.ll
[AArch64][TableGen] Skip tied result operands for InstAlias
2017-11-20 14:36:40 +00:00
arm64-alloc-no-stack-realign.ll
arm64-alloca-frame-pointer-offset.ll
arm64-andCmpBrToTBZ.ll
arm64-ands-bad-peephole.ll
arm64-AnInfiniteLoopInDAGCombine.ll
arm64-anyregcc-crash.ll
arm64-anyregcc.ll
arm64-arith-saturating.ll
arm64-arith.ll
arm64-arm64-dead-def-elimination-flag.ll
arm64-atomic-128.ll
arm64-atomic.ll
Fix some misc. -enable-var-scope violations
2017-11-13 01:47:52 +00:00
arm64-basic-pic.ll
arm64-bcc.ll
arm64-big-endian-bitconverts.ll
arm64-big-endian-eh.ll
arm64-big-endian-varargs.ll
arm64-big-endian-vector-callee.ll
arm64-big-endian-vector-caller.ll
arm64-big-imm-offsets.ll
arm64-big-stack.ll
arm64-bitfield-extract.ll
arm64-blockaddress.ll
arm64-build-vector.ll
[AArch64] Improve code generation of vector build
2018-01-04 21:43:12 +00:00
arm64-builtins-linux.ll
arm64-call-tailcalls.ll
arm64-cast-opt.ll
arm64-ccmp-heuristics.ll
arm64-ccmp.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
arm64-clrsb.ll
arm64-coalesce-ext.ll
arm64-coalescing-MOVi32imm.ll
arm64-code-model-large-abs.ll
arm64-codegen-prepare-extload.ll
Fix some misc. -enable-var-scope violations
2017-11-13 01:47:52 +00:00
arm64-collect-loh-garbage-crash.ll
arm64-collect-loh-str.ll
arm64-collect-loh.ll
arm64-complex-copy-noneon.ll
arm64-complex-ret.ll
[ARM][AArch64][DAG] Reenable post-legalize store merge
2017-12-06 15:30:13 +00:00
arm64-const-addr.ll
arm64-convert-v4f64.ll
arm64-copy-tuple.ll
arm64-crc32.ll
arm64-crypto.ll
arm64-cse.ll
arm64-csel.ll
arm64-csldst-mmo.ll
[MIR] Add support for the frame-destroy MachineInstr flag
2018-01-09 11:33:22 +00:00
arm64-cvt.ll
arm64-dagcombiner-convergence.ll
arm64-dagcombiner-dead-indexed-load.ll
arm64-dagcombiner-load-slicing.ll
arm64-dead-def-frame-index.ll
arm64-dead-register-def-bug.ll
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
arm64-detect-vec-redux.ll
arm64-dup.ll
[AArch64][TableGen] Skip tied result operands for InstAlias
2017-11-20 14:36:40 +00:00
arm64-early-ifcvt.ll
arm64-elf-calls.ll
arm64-elf-constpool.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-elf-globals.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-EXT-undef-mask.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-ext.ll
arm64-extend-int-to-fp.ll
arm64-extend.ll
arm64-extern-weak.ll
arm64-extload-knownzero.ll
arm64-extract_subvector.ll
arm64-extract.ll
arm64-fast-isel-addr-offset.ll
arm64-fast-isel-alloca.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-fast-isel-br.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-fast-isel-call.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-fast-isel-conversion-fallback.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-fast-isel-conversion.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-fast-isel-fcmp.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-fast-isel-gv.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-fast-isel-icmp.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-fast-isel-indirectbr.ll
arm64-fast-isel-intrinsic.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-fast-isel-materialize.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-fast-isel-noconvert.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-fast-isel-rem.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-fast-isel-ret.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-fast-isel-store.ll
arm64-fast-isel.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-fastcc-tailcall.ll
arm64-fastisel-gep-promote-before-add.ll
arm64-fcmp-opt.ll
AArch64: work around how Cyclone handles "movi.2d vD, #0 ".
2017-12-18 10:36:00 +00:00
arm64-fcopysign.ll
arm64-fixed-point-scalar-cvt-dagcombine.ll
arm64-fma-combine-with-fpfusion.ll
arm64-fma-combines.ll
arm64-fmadd.ll
arm64-fmax-safe.ll
arm64-fmax.ll
arm64-fminv.ll
arm64-fml-combines.ll
arm64-fmuladd.ll
arm64-fold-address.ll
arm64-fold-lsl.ll
arm64-fp128-folding.ll
arm64-fp128.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
arm64-fp-contract-zero.ll
arm64-fp-imm.ll
arm64-fp.ll
arm64-frame-index.ll
arm64-global-address.ll
arm64-hello.ll
arm64-i16-subreg-extract.ll
arm64-icmp-opt.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
arm64-illegal-float-ops.ll
arm64-indexed-memory.ll
arm64-indexed-vector-ldst-2.ll
arm64-indexed-vector-ldst.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
arm64-inline-asm-error-I.ll
arm64-inline-asm-error-J.ll
arm64-inline-asm-error-K.ll
arm64-inline-asm-error-L.ll
arm64-inline-asm-error-M.ll
arm64-inline-asm-error-N.ll
arm64-inline-asm-zero-reg-error.ll
arm64-inline-asm.ll
arm64-join-reserved.ll
arm64-jumptable.ll
[SimplifyCFG] Avoid quadratic on a predecessors number behavior in instruction sinking.
2017-12-21 01:22:13 +00:00
arm64-large-frame.ll
arm64-ld1.ll
arm64-ld-from-st.ll
arm64-ldp-aa.ll
arm64-ldp-cluster.ll
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
arm64-ldp.ll
[AArch64] Extend tests of loads and stores of register pairs
2017-09-19 15:46:35 +00:00
arm64-ldst-unscaled-pre-post.mir
arm64-ldur.ll
arm64-ldxr-stxr.ll
arm64-leaf.ll
arm64-long-shift.ll
arm64-memcpy-inline.ll
arm64-memset-inline.ll
[AArch64] Fix bug in store of vector 0 DAGCombine.
2017-09-21 21:10:06 +00:00
arm64-memset-to-bzero.ll
TargetLoweringBase: Followup to r321035
2017-12-19 00:43:00 +00:00
arm64-misaligned-memcpy-inline.ll
arm64-misched-basic-A53.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
arm64-misched-basic-A57.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
arm64-misched-forwarding-A53.ll
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
arm64-misched-memdep-bug.ll
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
arm64-misched-multimmo.ll
[MachineOperand][MIR] Add isRenamable to MachineOperand.
2017-12-12 17:53:59 +00:00
arm64-movi.ll
arm64-mul.ll
arm64-named-reg-alloc.ll
arm64-named-reg-notareg.ll
arm64-narrow-st-merge.ll
[ARM][AArch64][DAG] Reenable post-legalize store merge
2017-12-06 15:30:13 +00:00
arm64-neg.ll
arm64-neon-2velem-high.ll
arm64-neon-2velem.ll
[AArch64] Expand test coverage of vector element shuffling to Exynos
2017-12-18 22:17:39 +00:00
arm64-neon-3vdiff.ll
arm64-neon-aba-abd.ll
arm64-neon-across.ll
arm64-neon-add-pairwise.ll
arm64-neon-add-sub.ll
arm64-neon-compare-instructions.ll
arm64-neon-copy.ll
[AArch64][TableGen] Skip tied result operands for InstAlias
2017-11-20 14:36:40 +00:00
arm64-neon-copyPhysReg-tuple.ll
arm64-neon-mul-div.ll
arm64-neon-scalar-by-elem-mul.ll
arm64-neon-select_cc.ll
arm64-neon-simd-ldst-one.ll
arm64-neon-simd-shift.ll
arm64-neon-simd-vget.ll
arm64-neon-v1i1-setcc.ll
arm64-neon-v8.1a.ll
[AArch64] Add basic support for Qualcomm's Saphira CPU.
2017-09-25 14:05:00 +00:00
arm64-neon-vector-list-spill.ll
arm64-nvcast.ll
arm64-opt-remarks-lazy-bfi.ll
[MC] Adding code padding for performance stability - infrastructure. NFC.
2017-10-24 06:16:03 +00:00
arm64-patchpoint-scratch-regs.ll
arm64-patchpoint-webkit_jscc.ll
[MC] Suppress .Lcfi labels when emitting textual assembly
2017-10-10 00:57:36 +00:00
arm64-patchpoint.ll
arm64-pic-local-symbol.ll
arm64-platform-reg.ll
arm64-popcnt.ll
arm64-prefetch.ll
arm64-promote-const.ll
arm64-redzone.ll
arm64-reg-copy-noneon.ll
arm64-register-offset-addressing.ll
arm64-register-pairing.ll
arm64-regress-f128csel-flags.ll
arm64-regress-interphase-shift.ll
arm64-regress-opt-cmp.mir
MIR: Print the register class or bank in vreg defs
2017-10-24 18:04:54 +00:00
arm64-return-vector.ll
arm64-returnaddr.ll
arm64-rev.ll
arm64-rounding.ll
arm64-scaled_iv.ll
arm64-scvt.ll
Fix some misc. -enable-var-scope violations
2017-11-13 01:47:52 +00:00
arm64-setcc-int-to-fp-combine.ll
arm64-shifted-sext.ll
arm64-shrink-v1i64.ll
arm64-shrink-wrapping.ll
arm64-simd-scalar-to-vector.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-simplest-elf.ll
arm64-sincos.ll
arm64-sitofp-combine-chains.ll
arm64-sli-sri-opt.ll
arm64-smaxv.ll
[AArch64][TableGen] Skip tied result operands for InstAlias
2017-11-20 14:36:40 +00:00
arm64-sminv.ll
[AArch64][TableGen] Skip tied result operands for InstAlias
2017-11-20 14:36:40 +00:00
arm64-spill-lr.ll
arm64-spill-remarks-treshold-hotness.ll
[opt-remarks] If hotness threshold is set, ignore remarks without hotness
2017-12-01 20:41:38 +00:00
arm64-spill-remarks.ll
arm64-spill.ll
arm64-sqshl-uqshl-i64Contant.ll
arm64-st1.ll
[AArch64] Avoid SIMD interleaved store instruction for Exynos.
2017-12-08 00:58:49 +00:00
arm64-stack-no-frame.ll
arm64-stackmap-nops.ll
arm64-stackmap.ll
arm64-stackpointer.ll
arm64-stacksave.ll
arm64-storebytesmerge.ll
[ARM][AArch64][DAG] Reenable post-legalize store merge
2017-12-06 15:30:13 +00:00
arm64-stp-aa.ll
arm64-stp.ll
[AArch64][TableGen] Skip tied result operands for InstAlias
2017-11-20 14:36:40 +00:00
arm64-strict-align.ll
arm64-stur.ll
arm64-subsections.ll
arm64-subvector-extend.ll
arm64-summary-remarks.ll
arm64-swizzle-tbl-i16-layout.ll
arm64-tbl.ll
arm64-this-return.ll
arm64-tls-darwin.ll
arm64-tls-dynamic-together.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-tls-dynamics.ll
arm64-tls-execs.ll
arm64-trap.ll
arm64-triv-disjoint-mem-access.ll
arm64-trn.ll
arm64-trunc-store.ll
arm64-umaxv.ll
[AArch64][TableGen] Skip tied result operands for InstAlias
2017-11-20 14:36:40 +00:00
arm64-uminv.ll
[AArch64][TableGen] Skip tied result operands for InstAlias
2017-11-20 14:36:40 +00:00
arm64-umov.ll
arm64-unaligned_ldst.ll
arm64-uzp.ll
arm64-vaargs.ll
arm64-vabs.ll
arm64-vadd.ll
arm64-vaddlv.ll
arm64-vaddv.ll
[AArch64][TableGen] Skip tied result operands for InstAlias
2017-11-20 14:36:40 +00:00
arm64-variadic-aapcs.ll
[ARM][AArch64][DAG] Reenable post-legalize store merge
2017-12-06 15:30:13 +00:00
arm64-vbitwise.ll
arm64-vclz.ll
arm64-vcmp.ll
arm64-vcnt.ll
arm64-vcombine.ll
[AArch64][TableGen] Skip tied result operands for InstAlias
2017-11-20 14:36:40 +00:00
arm64-vcvt_f32_su32.ll
arm64-vcvt_f.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
arm64-vcvt_n.ll
arm64-vcvt_su32_f32.ll
arm64-vcvt.ll
arm64-vcvtxd_f32_f64.ll
arm64-vecCmpBr.ll
arm64-vecFold.ll
arm64-vector-ext.ll
arm64-vector-imm.ll
arm64-vector-insertion.ll
[AArch64] Improve code generation of vector build
2018-01-04 21:43:12 +00:00
arm64-vector-ldst.ll
arm64-vext_reverse.ll
arm64-vext.ll
arm64-vfloatintrinsics.ll
[AArch64] allow v8f16 types when FullFP16 is supported
2017-09-15 09:24:48 +00:00
arm64-vhadd.ll
arm64-vhsub.ll
arm64-virtual_base.ll
arm64-vmax.ll
arm64-vminmaxnm.ll
arm64-vmovn.ll
arm64-vmul.ll
arm64-volatile.ll
arm64-vpopcnt.ll
arm64-vqadd.ll
arm64-vqsub.ll
arm64-vselect.ll
arm64-vsetcc_fp.ll
arm64-vshift.ll
arm64-vshr.ll
arm64-vshuffle.ll
arm64-vsqrt.ll
arm64-vsra.ll
arm64-vsub.ll
arm64-weak-reference.ll
arm64-xaluo.ll
[AArch64] Improve codegen for inverted overflow checking intrinsics
2017-10-09 15:15:09 +00:00
arm64-zero-cycle-regmov.ll
Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding""
2017-10-03 16:59:13 +00:00
arm64-zero-cycle-zeroing.ll
AArch64: fix one more place movi.2d could be created.
2017-12-20 10:45:39 +00:00
arm64-zeroreg.ll
arm64-zext.ll
arm64-zextload-unscaled.ll
arm64-zip.ll
asm-large-immediate.ll
asm-print-comments.ll
assertion-rc-mismatch.ll
atomic-ops-lse.ll
[AArch64] Add basic support for Qualcomm's Saphira CPU.
2017-09-25 14:05:00 +00:00
atomic-ops-not-barriers.ll
atomic-ops.ll
basic-pic.ll
bics.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
bitcast-v2i8.ll
bitcast.ll
bitfield-extract.ll
bitfield-insert-0.ll
bitfield-insert.ll
bitfield.ll
bitreverse.ll
[AArch64][TableGen] Skip tied result operands for InstAlias
2017-11-20 14:36:40 +00:00
blockaddress.ll
bool-loads.ll
br-cond-not-merge.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
br-to-eh-lpad.ll
br-undef-cond.ll
branch-folder-merge-mmos.ll
branch-relax-alignment.ll
branch-relax-asm.ll
branch-relax-bcc.ll
branch-relax-cbz.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
breg.ll
bswap-known-bits.ll
build-one-lane.ll
[AArch64] Improve code generation of vector build
2018-01-04 21:43:12 +00:00
callee-save.ll
ccmp-successor-probs.mir
cfi_restore.mir
[AsmPrinterDwarf] Add support for .cfi_restore directive
2017-11-02 12:00:58 +00:00
chkstk.ll
[AArch64] Implement stack probing for windows
2017-12-20 06:51:45 +00:00
cmp-const-max.ll
cmp-frameindex.ll
AArch64: account for possible frame index operand in compares.
2017-10-17 21:43:52 +00:00
cmpwithshort.ll
cmpxchg-idioms.ll
[SimplifyCFG] use pass options and remove the latesimplifycfg pass
2017-10-28 18:43:07 +00:00
cmpxchg-O0.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
code-model-large-abs.ll
combine-and-like.ll
[DAGCombine] visitANDLike - ensure APInt is is in range for getSExtValue/getZExtValue
2017-12-26 23:27:44 +00:00
combine-comparisons-by-cse.ll
compare-branch.ll
compiler-ident.ll
complex-copy-noneon.ll
complex-fp-to-int.ll
complex-int-to-fp.ll
concat_vector-scalar-combine.ll
[AArch64][TableGen] Skip tied result operands for InstAlias
2017-11-20 14:36:40 +00:00
concat_vector-truncate-combine.ll
concat_vector-truncated-scalar-combine.ll
cond-br-tuning.ll
cond-sel-value-prop.ll
cond-sel.ll
cpus.ll
[AArch64] Add basic support for Qualcomm's Saphira CPU.
2017-09-25 14:05:00 +00:00
csel-zero-float.ll
cxx-tlscc.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
dag-combine-invaraints.ll
dag-combine-mul-shl.ll
dag-combine-select.ll
dag-numsignbits.ll
directcond.ll
div_minsize.ll
divrem.ll
dllexport.ll
[AArch64] Support COFF linker directives
2017-08-31 08:28:48 +00:00
dllimport.ll
[AArch64] Add support for dllimport of values and functions
2017-10-25 07:25:18 +00:00
dont-take-over-the-world.ll
dp1.ll
dp2.ll
dp-3source.ll
dwarf-cfi.ll
[AArch64] Use dwarf exception handling on MinGW
2017-11-03 07:33:20 +00:00
eliminate-trunc.ll
emutls_generic.ll
[AArch64] Allow using emulated tls on platforms other than ELF
2017-12-04 09:09:04 +00:00
emutls.ll
eon.ll
extern-weak.ll
extract.ll
f16-convert.ll
f16-imm.ll
[AArch64] Add FMOVH0: materialize 0 using zero register for f16 values
2017-08-24 14:47:06 +00:00
f16-instructions.ll
Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding""
2017-10-03 16:59:13 +00:00
fadd-combines.ll
falkor-hwpf-fix.ll
falkor-hwpf-fix.mir
[AArch64][Falkor] Ignore SP based loads in HW prefetch fixups.
2017-09-27 17:14:10 +00:00
falkor-hwpf.ll
fast-isel-address-extends.ll
fast-isel-addressing-modes.ll
fast-isel-assume.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
fast-isel-atomic.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
fast-isel-branch_weights.ll
fast-isel-branch-cond-mask.ll
fast-isel-branch-cond-split.ll
fast-isel-call-return.ll
fast-isel-cbz.ll
fast-isel-cmp-branch.ll
fast-isel-cmp-vec.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
fast-isel-cmpxchg.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
fast-isel-folded-shift.ll
fast-isel-folding.ll
fast-isel-gep.ll
fast-isel-int-ext2.ll
fast-isel-int-ext3.ll
fast-isel-int-ext4.ll
fast-isel-int-ext5.ll
fast-isel-int-ext.ll
fast-isel-intrinsic.ll
fast-isel-logic-op.ll
fast-isel-memcpy.ll
fast-isel-mul.ll
fast-isel-runtime-libcall.ll
fast-isel-sdiv.ll
fast-isel-select.ll
fast-isel-shift.ll
fast-isel-sp-adjust.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
fast-isel-sqrt.ll
fast-isel-switch-phi.ll
fast-isel-tail-call.ll
fast-isel-tbz.ll
fast-isel-trunc.ll
fast-isel-vector-arithmetic.ll
fast-isel-vret.ll
fastcc-reserved.ll
fastcc.ll
[AArch64] Fix bug in store of vector 0 DAGCombine.
2017-09-21 21:10:06 +00:00
fcmp.ll
fcopysign.ll
fcsel-zero.ll
fcvt_combine.ll
fcvt-fixed.ll
fcvt-int.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
fdiv_combine.ll
fdiv-combine.ll
fence-singlethread.ll
flags-multiuse.ll
Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding""
2017-10-03 16:59:13 +00:00
floatdp_1source.ll
floatdp_2source.ll
fold-constants.ll
fp16-v4-instructions.ll
[AArch64][TableGen] Skip tied result operands for InstAlias
2017-11-20 14:36:40 +00:00
fp16-v8-instructions.ll
[AArch64][TableGen] Skip tied result operands for InstAlias
2017-11-20 14:36:40 +00:00
fp16-v16-instructions.ll
[AArch64][TableGen] Skip tied result operands for InstAlias
2017-11-20 14:36:40 +00:00
fp16-vector-bitcast.ll
fp16-vector-load-store.ll
fp16-vector-nvcast.ll
fp16-vector-shuffle.ll
[AArch64][TableGen] Skip tied result operands for InstAlias
2017-11-20 14:36:40 +00:00
fp128-folding.ll
fp-cond-sel.ll
AArch64: work around how Cyclone handles "movi.2d vD, #0 ".
2017-12-18 10:36:00 +00:00
fp-dp3.ll
fpconv-vector-op-scalarize.ll
fpimm.ll
fptouint-i8-zext.ll
frameaddr.ll
free-zext.ll
func-argpassing.ll
func-calls.ll
Re-land MachineInstr: Reason locally about some memory objects before going to AA.
2017-08-30 14:57:12 +00:00
funcptr_cast.ll
function-subtarget-features.ll
gep-nullptr.ll
ghc-cc.ll
global-alignment.ll
global-merge-1.ll
global-merge-2.ll
global-merge-3.ll
global-merge-4.ll
global-merge-group-by-use.ll
global-merge-ignore-single-use-minsize.ll
global-merge-ignore-single-use.ll
global-merge.ll
got-abuse.ll
half.ll
hints.ll
i1-contents.ll
i128-align.ll
i128-fast-isel-fallback.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
ifcvt-select.ll
illegal-float-ops.ll
implicit-sret.ll
init-array.ll
inline-asm-constraints-badI.ll
inline-asm-constraints-badK2.ll
inline-asm-constraints-badK.ll
inline-asm-constraints-badL.ll
inline-asm-globaladdress.ll
inlineasm-ldr-pseudo.ll
inlineasm-X-allocation.ll
inlineasm-X-constraint.ll
intrinsics-memory-barrier.ll
jump-table.ll
large_shift.ll
large-consts.ll
ldp-stp-scaled-unscaled-pairs.ll
ldst-opt-aa.mir
ldst-opt-zr-clobber.mir
ldst-opt.ll
[AArch64] Fix bug in store of vector 0 DAGCombine.
2017-09-21 21:10:06 +00:00
ldst-opt.mir
ldst-paired-aliasing.ll
Revert r321089: "[DAG] Elide overlapping store" (and subsequent fix in r321204)
2018-01-02 14:38:52 +00:00
ldst-regoffset.ll
ldst-unscaledimm.ll
ldst-unsignedimm.ll
ldst-zero.ll
legalize-bug-bogus-cpu.ll
lit.local.cfg
literal_pools_float.ll
live-interval-analysis.mir
load-combine-big-endian.ll
load-combine.ll
local_vars.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
logical_shifted_reg.ll
logical-imm.ll
loh.mir
[CodeGen] Print global addresses as @foo in both MIR and debug output
2017-12-14 10:03:09 +00:00
loop-micro-op-buffer-size-t99.ll
[AArch64] Improve loop unrolling performance on Cavium T99
2017-12-09 23:59:55 +00:00
loopvectorize_pr33804_double.ll
[LoopVectorizer] Add more testcases for PR33804.
2017-09-18 17:28:15 +00:00
lower-range-metadata-func-call.ll
machine_cse_impdef_killflags.ll
machine_cse.ll
machine-combiner-madd.ll
machine-combiner.ll
Recommit [MachineCombiner] Update instruction depths incrementally for large BBs.
2017-09-20 11:54:37 +00:00
machine-combiner.mir
[MachineCombiner] Fix initialisation of LastUpdate for incremental update.
2017-10-11 20:25:58 +00:00
machine-copy-prop.ll
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
machine-copy-remove.ll
machine-copy-remove.mir
machine-dead-copy.mir
machine-outliner-remarks.ll
[CodeGen] Always use printReg to print registers in both MIR and debug
2017-11-30 16:12:24 +00:00
machine-outliner.ll
[MachineOutliner] Disable outlining from LinkOnceODRs by default
2017-10-07 00:16:34 +00:00
machine-outliner.mir
[MachineOutliner] AArch64: Handle instrs that use SP and will never need fixups
2018-01-09 00:26:18 +00:00
machine-scheduler.mir
machine-sink-kill-flags.ll
machine-sink-zr.mir
machine-zero-copy-remove.mir
macho-global-symbols.ll
madd-combiner.ll
madd-lohi.ll
mature-mc-support.ll
max-jump-table.ll
[CodeGen] Print jump-table index operands as %jump-table.0 in both MIR and debug output
2017-12-13 10:30:59 +00:00
memcpy-f128.ll
merge-store-dependency.ll
Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding""
2017-10-03 16:59:13 +00:00
merge-store.ll
mergestores_noimplicitfloat.ll
min-jump-table.ll
[CodeGen] Print jump-table index operands as %jump-table.0 in both MIR and debug output
2017-12-13 10:30:59 +00:00
minmax-of-minmax.ll
[AArch64] fix typos in comments; NFC
2018-01-02 21:04:08 +00:00
minmax.ll
misched-fusion-aes.ll
misched-fusion-lit.ll
misched-fusion.ll
misched-stp.ll
movimm-wzr.mir
movw-consts.ll
movw-shift-encoding.ll
mul_pow2.ll
mul-lohi.ll
neg-imm.ll
Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding""
2017-10-03 16:59:13 +00:00
neon-bitcast.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
neon-bitwise-instructions.ll
neon-compare-instructions.ll
neon-diagnostics.ll
neon-extract.ll
neon-fma-FMF.ll
neon-fma.ll
neon-fpround_f128.ll
neon-idiv.ll
neon-inline-asm-16-bit-fp.ll
neon-mla-mls.ll
neon-mov.ll
neon-or-combine.ll
neon-perm.ll
neon-scalar-by-elem-fma.ll
neon-scalar-copy.ll
neon-shift-left-long.ll
neon-truncStore-extLoad.ll
nest-register.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
no-fp-asm-clobbers-crash.ll
Don't crash when we see unallocatable registers in clobbers
2017-10-23 20:46:36 +00:00
no-quad-ldp-stp.ll
nonlazybind.ll
nontemporal.ll
nzcv-save.ll
optimize-cond-branch.ll
optimize-imm.ll
or-combine.ll
paired-load.ll
PBQP-chain.ll
PBQP-coalesce-benefit.ll
PBQP-csr.ll
PBQP.ll
phi-dbg.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
2017-11-28 17:15:09 +00:00
pic-eh-stubs.ll
pie.ll
postra-mi-sched.ll
pr27816.ll
pr33172.ll
preferred-alignment.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
preferred-function-alignment.ll
prefixdata.ll
preserve_mostcc.ll
print-mrs-system-register.ll
prologue-epilogue-remarks.mir
ragreedy-csr.ll
rbit.ll
readcyclecounter.ll
recp-fastmath.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
redundant-copy-elim-empty-mbb.ll
Redundantstore.ll
reg-scavenge-frame.mir
regcoal-physreg.mir
MIR: Print the register class or bank in vreg defs
2017-10-24 18:04:54 +00:00
regress-bitcast-formals.ll
regress-f128csel-flags.ll
regress-fp128-livein.ll
regress-tail-livereg.ll
regress-tblgen-chains.ll
regress-w29-reserved-with-fp.ll
rem_crash.ll
remat-float0.ll
remat.ll
[AArch64] Add basic support for Qualcomm's Saphira CPU.
2017-09-25 14:05:00 +00:00
returnaddr.ll
rm_redundant_cmp.ll
rotate.ll
round-conv.ll
sched-past-vector-ldst.ll
scheduledag-constreg.mir
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
sdivpow2.ll
selectcc-to-shiftand.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
selectiondag-order.ll
setcc-takes-i32.ll
setcc-type-mismatch.ll
shrink-wrap.ll
sibling-call.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
simple-macho.ll
sincos-expansion.ll
sincospow-vector-expansion.ll
sitofp-fixed-legal.ll
special-reg.ll
spill-fold.ll
spill-undef.mir
MIR: Print the register class or bank in vreg defs
2017-10-24 18:04:54 +00:00
sqrt-fastmath.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
stack_guard_remat.ll
stack-guard-remat-bitcast.ll
stack-protector-target.ll
stackmap-frame-setup.ll
stackmap-liveness.ll
store_merge_pair_offset.ll
strqro.ll
[AArch64][Falkor] Avoid generating STRQro* instructions
2017-08-28 20:48:43 +00:00
subs-to-sub-opt.ll
swift-error.ll
AArch64: support SwiftCC properly on AAPCS64
2017-09-22 04:31:44 +00:00
swift-return.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
swiftcc.ll
swifterror.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
swiftself-scavenger.ll
swiftself.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
tail-call.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
tailcall_misched_graph.ll
[CodeGen] Print stack object references as %(fixed-)stack.0 in both MIR and debug output
2017-12-15 16:33:45 +00:00
tailcall-ccmismatch.ll
tailcall-explicit-sret.ll
[ARM][AArch64][DAG] Reenable post-legalize store merge
2017-12-06 15:30:13 +00:00
tailcall-fastisel.ll
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
2018-01-02 16:30:47 +00:00
tailcall-implicit-sret.ll
[ARM][AArch64][DAG] Reenable post-legalize store merge
2017-12-06 15:30:13 +00:00
tailcall-mem-intrinsics.ll
tailcall-string-rvo.ll
tailmerging_in_mbp.ll
tbi.ll
tbz-tbnz.ll
trunc-v1i64.ll
tst-br.ll
vcvt-oversize.ll
vector_merge_dep_check.ll
vector-fcopysign.ll
[AArch64][TableGen] Skip tied result operands for InstAlias
2017-11-20 14:36:40 +00:00
win64_vararg.ll
xbfiz.ll
xray-attribute-instrumentation.ll
[XRay][CodeGen] Use PIC-friendly code in XRay sleds and remove synthetic references in .text
2017-09-04 05:34:58 +00:00
xray-tail-call-sled.ll
[XRay][CodeGen] Use PIC-friendly code in XRay sleds and remove synthetic references in .text
2017-09-04 05:34:58 +00:00
zero-reg.ll
